Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract: A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.

Abstract: In a multi-processor architecture, a plurality of processors share a coprocessor for certain instructions. Each processor may supply the coprocessor with a number of instructions and operands for those instructions. Other operations may be performed while waiting for the results. When the results are needed, the processor may be configured to force synchronization by suspending operations until the results are received. While waiting for the results, the processor enters a low-power state, waking up automatically when the last result waited upon is received.

Abstract: An apparatus and method are provided for managing a branch information storage. The apparatus has a processor to process instructions, comprising fetch circuitry to fetch instructions from a plurality of threads for processing by the processor. The branch information storage has a plurality of entries, each entry storing a virtual address identifier for a branch instruction, branch information about the branch instruction, and thread identifier information indicating which of the plurality of threads that entry is valid for. The fetch circuitry is arranged to access the branch information storage using a virtual address of an instruction to be fetched for one of the plurality of threads, in order to determine whether a hit condition exists, and in that event to obtain the branch information stored in the entry that gave rise to the hit condition.

Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure.

Abstract: The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.

Abstract: A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.

Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.

Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

Abstract: An electronic apparatus and a booting method thereof are provided. Control a sensing unit to sense a barcode before an operation system is executed by the electronic apparatus. Determine whether the barcode meets a preset barcode. Continue a booting operation of the electronic apparatus if the barcode meets the preset barcode.

Abstract: The present invention provides a method and a system for accelerating intelligent terminal boot speed, wherein the method for accelerating intelligent terminal boot speed includes: defining a delay time to delay the startup of a CPU hotplug algorithm during a flow of booting for performing a CPU algorithm; setting a running mode of the CPU as a performance mode, so that the CPU is under a highest frequency state and the CPU is under a multi-core state; and switching the running mode of the CPU to a normal mode when the defined delay time terminates, so that the CPU adjusts the CPU frequency according to a normal boot load.

Abstract: Technologies for securely booting a computing device includes a security engine of the computing device that consecutively determines a hash value for each block of initial boot firmware and generates an aggregated hash value from the hash value determined for each of the blocks. A processor of the computing device determines whether the aggregated hash value matches a reference checksum value. Initialization of the processor is completed in response to a determination that the aggregated hash value matches the reference checksum value. In some embodiments, the security engine consecutively retrieves each block of the initial boot firmware from a memory of the computing device, stores each retrieved block in a secure memory of the security engine, and determines the hash value for each stored block. Each block stored in the secure memory is copied to a portion of a cache memory of the processor initialized as Cache as RAM.

Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.

Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.

Abstract: There are disclosed various methods and apparatuses for a device setup. In some embodiments of the method a signal from a peripheral device is detected by an apparatus and biometric data is received from the peripheral device. The biometric data is transmitted to a server. An indication whether the server has found biometric identification corresponding to the biometric data or other information indicative of that the apparatus and the peripheral device are attached to a same user is received from the server. If the indication reveals that the server has found biometric identification corresponding to the biometric data or other information indicative of that the apparatus and the peripheral device are attached to a same user configuration data is received from the server and used for configuring at least one of the apparatus and the peripheral device. In some embodiments the apparatus comprises means for implementing the method.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to store a first set of instructions in a first portion of the non-volatile memory, the first set of instructions to configure a second portion of the non-volatile memory, cause the processing unit to process the first set of instructions to configure the second portion with one or more regions, and cause a configuration of the memory controller based on the first set of instructions.

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

Abstract: A method for conserving power in a computing device having a volatile system memory, a non-volatile storage device, and a processor executing an operating system and including an internal non-volatile memory (NVM). The method includes receiving, at the processor, a request to enter the computing device into a hibernation mode, suspending, by the processor, execution of the operating system, copying, by the processor, substantially the entire contents of the volatile system memory into the non-volatile storage device, storing, in the internal NVM of the processor, a hibernate flag, and turning off power to the computing device.

Abstract: A method of simultaneously creating a website and an app including providing, at the at least one server, a first coding template operably configured to create a website and a second coding template operably configured to create a mobile app; receiving a client selection of one of a plurality of pre-determined website-app templates stored at the at least one server; and creating a channel including the website and the corresponding mobile app by executing the first code template to create the website and simultaneously executing the second coding template to create the corresponding mobile app with the client-selected one of the plurality of pre-determined website-app templates being an input to each of the first and second coding templates.

Abstract: An apparatus and a method for configuring an idle screen in a terminal is provided.

Abstract: In a method of controlling and managing an electronic device, which is executed by at least one control device to control and manage at least one electronic device, a projectable space instance is provided for each the at least one control device to create a workspace, wherein at least one unified tool for driving the at least one electronic device is selectively added to the projectable space instance. The projectable space instance is then parsed with a projector by the corresponding control device to automatically generate a projected workspace corresponding to the workspace to be created via the projectable space instance, wherein the at least one unified tool drives the at least one electronic device to execute at least one task in response to an operation on the corresponding control device.

Abstract: The present technology provides for an IO module system (e.g., an industrial control system) that can provide multiple-channel analog and digital interfaces to a number of sensor devices of different types, where each channel of the IO module is programmably configurable as a digital input, a digital output, an analog input, and an analog output. Each sensor interface is implemented on an individual channel basis using discrete components in communication with a microcontroller. The present technology enables the rapid implementation of an IO channel operable in a wide range of voltage and current modes needed for common sensor interfaces.

Abstract: The present technology utilizes agents to monitor and report data from Java virtual machines (JVM) to a controller as part of application performance monitoring. When a JVM is loaded, code defining an interface for agents is loaded as well. A determination may be made as to whether the loaded agent implements the interface defined at the JVM. If the loaded agent does not implement the interface, for example if it is missing one or more methods defined by the interface, the agent class may be modified to define the missing methods. The modification to the agent class may be made after compilation but before the class is loaded into the JVM.

Abstract: The current application is directed to architected hardware support within computer processors for detecting and monitoring various types of potential performance imbalances with respect to simultaneously executing hardware threads in simultaneous multi-threading (“SMT”) processors and SMT-processor cores. The architected hardware support may include various types of performance-imbalance-monitoring registers that accumulate indications of performance imbalances and that can be used, by performance-monitoring software and by human analysts to detect performance-degrading conflicts between simultaneously executing hardware threads. Such conflicts can be ameliorated by changing the scheduling of virtual machines, tasks, and other computational entities, by redesigning and re-implementing all or portions of performance-limited and performance-degrading applications, by altering resource-allocation strategies, and by other means.

Abstract: A hypervisor receives a request pertaining to a multi-function device managed by the hypervisor from a guest operating system of a virtual machine where the multi-function device comprises a main function and a plurality of sub-functions and the request identifies an address within a configuration space associated with one of the plurality of sub-functions of the multi-function device. The hypervisor determines the main function of the multi-function device in view of the address of the configuration space associated with the sub-function, accesses a data structure associated with the main function to obtain an indicator of availability of the main function to the guest operating system, and determines, view of the indicator of availability, whether the main function is available to the guest operating system.

Abstract: Methods, systems, and computer program products are provided for migrating memory pages. A virtual machine is run by a hypervisor. The virtual machine includes a guest that is allocated a plurality of guest memory pages. A data structure is initialized corresponding to a memory page of the plurality of guest memory pages. A first status is assigned in the data structure to the memory page. The memory page is migrated to a destination and the data structure is modified to assign the memory page a second status.

Abstract: A method and a computer program product for causing a processor to perform the method are provided. The method includes creating a virtual machine having a virtual machine identifier, and storing an entry in a temporary virtual machine registry, wherein the entry includes the virtual machine identifier, inactivity criteria for the virtual machine, and a responsive action for the virtual machine. The method further includes monitoring the activity of the virtual machine, and initiating the responsive action associated with the virtual machine in response to the virtual machine satisfying the inactivity criteria.

Abstract: For managing a pool of virtual computer systems, master status and a rebasing task are assigned to at least one virtual computer system of the pool. A non-reserved status is assigned to virtual computer systems of the pool that are not assigned tasks. A virtual computer system of the pool is selected to respond to a rebasing request. The selecting includes selecting one of the at least one virtual computer system that currently has a master status and that currently has a processing load less than a predetermined threshold and, when no virtual computer system of the pool currently has a master status and a processing load less than the predetermined threshold, selecting a non-reserved one of the virtual computer systems to perform rebasing for the request and changing the non-reserved status of the selected, non-reserved one of the virtual computer systems to master status.

Abstract: In an example embodiment, a hypervisor exposes a first guest device to a first virtual machine and a second guest device to a second virtual machine. The hypervisor exposes a first virtual host device and a second virtual host device to a third virtual machine. The hypervisor maps a first memory and a second memory into the third virtual machine at a first base address register and a second base address register associated with each virtual host device. The hypervisor sends a first mapping from a first virtual machine and a second mapping from a second virtual machine to the third virtual machine. The hypervisor sends a first address of a first ring of the first guest device and a second address of a second ring of the second guest device to the third virtual machine through the respective virtual host devices.

Abstract: A method, system, and computer program product are disclosed for creating an in-memory application image. Embodiments can include receiving an application from a storage. Embodiments can also include loading the received application into a memory storage pool. Embodiments can also include receiving an indication of a request to execute the in-memory application image on a first virtual machine of a plurality of virtual machines. Embodiments can also include receiving an indication to execute the in-memory application image on the first virtual machine. Embodiments can also include removing the in-memory application image from the memory storage pool, in response to the receiving the indication to execute the in-memory application. Embodiments can also include assigning the removed in-memory application image to the first virtual machine.

Abstract: In an example embodiment, a hypervisor exposes a virtual input-output memory management unit (IOMMU) to a first virtual machine. The first virtual machine includes a first guest operating system (OS). The hypervisor exposes a first virtual device to the first virtual machine. The hypervisor exposes a shared memory device to a second virtual machine. The second virtual machine includes a second guest OS. The hypervisor detects that the first guest OS modified the virtual IOMMU to provide access to a memory page of the first virtual machine. The hypervisor receives a base address from the second virtual machine. The base address is programmed into the shared memory device by the second virtual machine. The hypervisor maps the memory page into the second virtual machine at a page address, which is determined from the base address and a bus address.

Abstract: A system and method for programming a timer in a virtualized system are disclosed. In accordance with one embodiment, a hypervisor executed by a processing device stores, in a first memory location that is readable by a virtual machine (VM), a first time that is associated with a first future interrupt. The hypervisor programs a timer to trigger at the first time, and detects a request by the VM for a second future interrupt at a second time, wherein the detecting comprises reading the second time from a second memory location that is writeable by the VM.

Abstract: In an example embodiment, a hypervisor exposes a first guest device to a first virtual machine. The hypervisor exposes a virtual host device and a pass-through device to a second virtual machine. The hypervisor maps a first memory and a second memory into the second virtual machine at a first base address register and a second base address register associated with the virtual host device and pass-through device. The hypervisor sends a mapping from the first virtual machine to the second virtual machine. The hypervisor sends a first address of a first ring of the first guest device and a second address of a second ring of an assigned device to the second virtual machine.

Abstract: An embodiment includes a system, comprising: a communication interface configured to communicate with a remote system external to the system; a memory; and a processor coupled to the communication interface and the memory and configured to: receive performance data from the remote system through the communication interface; maintain a virtual performance register in response to the performance data; receive a performance register access associated with the remote system through the communication interface; and respond to the performance data access through the communication interface based on the virtual performance register.

Abstract: An estimated time to migrate a VM from a source hypervisor to a target hypervisor is calculated. The estimated time is compared to a threshold time and based on the estimated time meeting the threshold time, a migration of the VM from the source hypervisor to the target hypervisor via the network is initiated. Based on the estimated time not meeting the threshold time, it is determined whether an additional path can be added to the network between the source hypervisor and the target hypervisor. If an additional path cannot be added to the network, a migration of the VM from the source hypervisor to the target hypervisor via the network is initiated. If an additional path can be added to the network, the additional path is added and the migration via the network is initiated.

Abstract: Systems and method for the management of virtual machine instances are provided. A network data transmission analysis system can use contextual information in the execution of virtual machine instances to isolate and migrate virtual machine instances onto physical computing devices. The contextual information may include information obtained in observing the execution of virtual machines instances, information obtained from requests submitted by users, such as system administrators. Still further, the network data transmission analysis system can also include information collection and retention for identified virtual machine instances.

Abstract: A method, system, and computer program product are disclosed for creating an in-memory application image. Embodiments can include receiving an application from a storage. Embodiments can also include loading the received application into a memory storage pool. Embodiments can also include receiving an indication of a request to execute the in-memory application image on a first virtual machine of a plurality of virtual machines. Embodiments can also include receiving an indication to execute the in-memory application image on the first virtual machine. Embodiments can also include removing the in-memory application image from the memory storage pool, in response to the receiving the indication to execute the in-memory application. Embodiments can also include assigning the removed in-memory application image to the first virtual machine.

Abstract: A method includes monitoring performance of a plurality of workloads that run on multiple compute nodes. Respective time series of anomalous performance events are established for at least some of the workloads. A selected workload is placed on a selected compute node, so as to reduce cross-interference between two or more of the workloads, by comparing two or more of the time series.

Abstract: Methods, systems, and apparatus, including computer program products, for discovering entities in a first portion of a data center network, examining information associated with the discovered entities to determine relationships that exist between pairs of entities in the first portion of the data center network, and generating a specification of the relationships that exist between pairs of entities in the first portion of the data center network based on results of the examining.

Abstract: A method and system may provide virtual port communications. A data frame, containing a destination identifier in a destination field and payload, may be modified by inserting a first virtual machine tag therein.

Abstract: A streams manager monitors performance of parallel portions of a streaming application implemented in multiple virtual machines (VMs). When the performance provided by the multiple VMs is no longer needed, one or more of the VMs can be torn down. The performance of the VMs is monitored. When the least performing VM can be torn down, it is torn down. When the least performing VM cannot be torn down, information regarding a better performing VM is gathered, and it is determined whether the least performing VM can be made more similar to the better performing VM. When the least performing VM can be made more similar to the better performing VM, the least performing VM is changed to improve its performance, and the better performing VM is torn down.

Abstract: Execution state information corresponding to an instantiated virtual machine are retrieved. A score to indicate a target memory location is able to be determined based at least in part on a source memory location is computed based at least in part on the execution state information. The score and the target memory location are indicated.

Abstract: Described herein are systems, methods, and software for translating data requests in a data processing cluster. In one example, a method of operating a cache service to interface between a virtual machine cluster and job data associated with a job executed by the virtual machine cluster includes identifying a request initiated by the virtual machine cluster to access at least a portion of the job data in accordance with a first distributed object access protocol. The method further includes in response to the request, accessing at least the portion of the job data in accordance with a second distributed object access protocol, and presenting at least the portion of the job data to the virtual machine cluster in accordance with the first distributed object access protocol.

Abstract: For managing a pool of virtual computer systems, master status and a rebasing task are assigned to at least one virtual computer system of the pool. A non-reserved status is assigned to virtual computer systems of the pool that are not assigned tasks. A virtual computer system of the pool is selected to respond to a rebasing request. The selecting includes selecting one of the at least one virtual computer system that currently has a master status and that currently has a processing load less than a predetermined threshold and, when no virtual computer system of the pool currently has a master status and a processing load less than the predetermined threshold, selecting a non-reserved one of the virtual computer systems to perform rebasing for the request and changing the non-reserved status of the selected, non-reserved one of the virtual computer systems to master status.