Abstract: A method and system for deploying a component of a composite application in a data center. An example method includes receiving access data from a traffic manager implementing global load balancing, where the access data is related to client accesses to a composite web application including multiple components hosted by virtual machines in a virtualization infrastructure. The method further includes determining, based on the access data, determining that one of the components of the composite web application receives client accesses that exceed a threshold, identifying a new geographic location for the client accesses that exceed the threshold, instructing the virtualization infrastructure to deploy a new virtual machine at the new geographic location, the deployed virtual machine implementing the determined component of the composite web application, and providing information pertaining to the deployed virtual machine to the traffic manager.

Abstract: Briefly, methods and apparatus to rebalance workloads among processing cores utilizing a hybrid work donation and work stealing technique are disclosed that improve workload imbalances within processing devices such as, for example, GPUs. In one example, the methods and apparatus allow for workload distribution between a first processing core and a second processing core by providing queue elements from one or more workgroup queues associated with workgroups executing on the first processing core to a first donation queue that may also be associated with the workgroups executing on the first processing core. The method and apparatus also determine if a queue level of the first donation queue is beyond a threshold, and if so, steal one or more queue elements from a second donation queue associated with workgroups executing on the second processing core.

Abstract: Hybrid threading in a processor is described. An integrated circuit that implements hybrid threading includes a power control unit (PCU), a first functional hardware unit coupled to the PCU, and a second functional hardware unit coupled to the PCU. The first functional hardware unit and the second functional hardware unit are heterogeneous functional hardware units. The PCU is configured to monitor at least one power attribute of the first and second functional hardware units. The PCU is further configured to calculate an aggregate power value based on the monitored at least one power attribute. Upon determining that the aggregate power value is below a power threshold, the PCU is also configured to calculate a first frequency for the first functional hardware unit and a second frequency for the second functional hardware unit that results in an updated aggregate power value that is closer to the power threshold.

Abstract: A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract: A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a secondary terminal environment. The mobile computing device may be a smartphone running the Android mobile OS and a full desktop Linux distribution on a modified Android kernel.

Abstract: Embodiments relate to a concept for ordering events of an event stream, comprising out-of-order events, for an event detector, wherein the events have associated thereto individual event occurrence times (ei·ts) and individual event propagation delays up to a maximum delay of K time units. Event received from the event stream are provided to an event buffer. Received events in the event buffer are ordered according their respective occurrence times to obtain ordered events. An ordered event (ei) having an event occurrence time ei·ts is speculatively forwarded from the event buffer to the event detector at an earliest time instant clk, such that ei·ts+?*K?clk, wherein ? denotes a speculation quantity with 0<?<1.

Abstract: In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each receive entry includes addressing information for one or more mailboxes into which messages can be injected, a send data structure including send entries each uniquely corresponding to a send window, where each send entry includes a receive window field that identifies one or more receive windows, and switch logic. The switch logic, responsive to a request to push a message to one or more receiving threads, accesses a send entry that corresponds to a send window of the sending thread, utilizes contents of the receive window field of the send entry to access one or more of the receive entries, and pushes the message to one or more mailboxes of one or more receiving threads utilizing the addressing information of the receive entry or entries.

Abstract: A method, an apparatus, and a system for mutual communication between processes of a many-core processor are provided that relate to the field of many-core operating systems The method is executed by a target kernel, where the target kernel corresponds to a target processor core. The method includes acquiring a message header of a message from a quick message channel (QMC); executing a central processing unit (CPU) pre-fetching command according to the message header, so that a message body that is in the message stored in a shared memory and corresponds to the message header is loaded to a cache that corresponds to the target processor core; and switching to a target process, so that the target process acquires the message body from the cache. The embodiments of the present invention apply to a scenario of mutual communication between processes of a many-core processor.

Abstract: A process and system for implementing a Java method by a second computer for a first computer to which the second computer is connected via a communication line. The second computer receives from the first computer a first message instructing the second computer to execute a Java method that is included in the first message. The Java method includes source code. After receiving the first message, the second computer executes the Java method that is in the first message. After said executing the Java method, the second computer transmits to the first computer a second message that includes the Java method and a result of executing the Java method.

Abstract: There is provided a technique of enabling to easily identify the association between process results in a plurality of components which are executed in association with an RPC. An information processing system in which an application of a first component performs an RPC for a functional function of a second component, the system comprises: a stub of the first component configured to receive the RPC and transmit an RPC message to the second component; and a skeleton of the second component configured to receive the RPC message from the stub and control execution of a predetermined function. The stub generates an RPC message having a header in which a sequence identifier acquired from the first management unit is embedded, and transmits the generated RPC message, and the skeleton extracts a sequence identifier from the header of the received RPC message.

Abstract: Probes are employed to inject errors into code. In response to a function-entry trigger event, a probe writes a predefined test value to a return value register. The probe then cause function execution to be skipped such that the test value is returned in lieu of the value which would otherwise be returned by the function. Behavior after the error is injected may then be observed, data collected, etc. such that undesired behavior (e.g., crashes) can be identified and/or corrected. In an alternative embodiment, the probe which is triggered may write a test value to a given memory address.

Abstract: A method for improving a global lifespan of a storage system of a computing system is provided. The method includes: providing a prediction engine associated with the storage system including at least one storage device, the prediction engine being initiated at an installation time of the at least one storage device; automatically determining lifespan values of the at least one storage device to assign the global lifespan of the storage system, the global lifespan being dependent on the installation time of the at least one storage device; replacing, responsive to a time-based failure event, a storage device of the at least one storage device; and subsequently monitoring, using the prediction engine, the global lifespan of the storage system based on the time-based failure event to define, at least in part, an optimized lifespan of the storage system.

Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

Abstract: A history of transmission/reception via a line is stored in association with the line, and it is detected whether or not a communication apparatus is physically connected to the line. Then if the line is detected to be disconnected, it is determined whether or not a history of transmission/reception regarding the disconnected line is stored. If it is determined that the history of transmission/reception regarding the disconnected line is stored, notification is given to a user that the line is disconnected.

Abstract: The present disclosure is related to systems, methods, and non-transitory machine readable media for alerting with duplicate suppression. An example non-transitory machine readable medium can store instructions executable by a processing resource to cause a computing system to receive an alert at a first virtual computing instance (VCI) from a second VCI, compare the alert with at least one previously received alert to determine if the alert is a duplicate alert, and send the alert to an alert notification queue associated with the first VCI in response to a determination that the alert is not a duplicate alert. In some embodiments, the medium can store instructions to confirm that the alert has been sent in response to the determination that the alert is a duplicate alert.

Abstract: A method is provided for operating a trace procedure, which traces execution of a computer program, where the program uses different callable modules. A program stack is used to store trace buffer information and an error state, and the modules include calls of the trace procedure. The method includes: (i) when entering execution of a module, storing the current write position of the trace buffer and a cleared error flag in the current frame of the stack; (ii) in case of an error condition during execution of the program, setting the error flag in the current frame; and (iii) when leaving execution of a module, determining if the error flag is set, and if not, then rewinding the trace buffer to the write position stored in the current frame, and deleting the current write position of the trace buffer and the error flag from the stack.

Abstract: Embodiments for categorizing a real-time log event are described. In one example, a Term Frequency-Inverse Document Frequency (TF-IDF) vector for the log event is computed based on pre-calculated TF-IDF matrix of log corpus and number of new words in log event, where log corpus comprises one or more pre-existing log events, and where the log event is indicative of error message. Further, distance between TF-IDF vector and cluster centroid of each cluster in the log corpus is calculated. Thereafter, cluster having closest cluster centroid is identified from amongst the clusters based on distance between TF-IDF vector and cluster centroid of each of the clusters, where closest cluster centroid is cluster centroid closest to TF-IDF vector. Subsequently, log event is categorized into one or more log categories based on comparison of distance between TF-IDF vector and closest cluster centroid pre-determined silhouette threshold corresponding to cluster with closest cluster centroid.

Abstract: An apparatus includes a memory configured to hold a condition for determining whether or not to migrate a virtual machine that runs on a certain information processing apparatus included in a plurality of information processing apparatuses, to other information processing apparatus included in the plurality of information processing apparatuses, and a processor coupled to the memory and configured to when the condition is satisfied in a first information processing apparatus included in the plurality of information processing apparatuses, migrate a first virtual machine that runs on the first information processing apparatus to another information processing apparatus included in the plurality of information processing apparatuses, after migrating the first virtual machine, detect a status of an error occurring in the first information processing apparatus, and change the condition, based on the detected status of the error.

Abstract: Embodiments include evaluating durability and availability of a distributed storage system. Aspects include receiving a configuration of the distributed storage system, identifying a failure model for each component of the distributed storage system. Aspects also include generating a series of failure events for each component of the distributed storage system based on the failure model and calculating a recovery time for each failed component based on a network recovery bandwidth, a disk recovery bandwidth, a total capacity of simultaneous failed storage devices and a resiliency scheme used by the in the distributed storage system. Aspects further include collecting data regarding the series of failures and the recovery times, calculating an observed distribution of component failures from the collected data and calculating the availability and durability of the distributed storage system based on the observed distribution of component failures and using probabilistic durability and availability models.

Abstract: A processor determines that a requested action is a failed action. The processor determines that the failed action is a valid action. The processor determines that the failed action is not properly configured. The processor generates a reconfigured action by reconfiguring the failed action. The reconfiguration of the failed action includes one or both of a) changing the preconditions of the failed action, or b) creating a recovery path in addition to the failed action.

Abstract: A fault isolation method, computer system, and apparatus, which are capable of monitoring a state of a second endpoint device in the extended domain, and setting a device state record according to the state of the second endpoint device; after an access request between the second endpoint device and the primary domain is received, querying the device state record according to identifier information that is of the second endpoint device and in the access request, and determining the state of the second endpoint device; and if the state of the second endpoint device is a fault state, discarding the access request to prevent communication between the faulty second endpoint device and the primary domain and prevent spreading a fault to the primary domain, thereby ensuring system reliability.

Abstract: A data storage device includes a controller configured to update an access request count and an access count corresponding to a target region based on an access request for the target region, and initialize the access count each time the access request count reaches a first threshold, and a nonvolatile memory apparatus including the target region, and configured to access the target region based on a control of the controller.

Abstract: A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission.

Abstract: An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.

Abstract: Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

Abstract: The present invention discloses an error correction method applied to a memory device, wherein the memory device has a plurality of pages. The error correction method includes: sequentially retrieving data of a plurality of first sectors of a first page of the pages in response to a first read command; performing a first error correction by an error correction module during retrieval the data of the first page; producing a second read command when the data of the first sectors of the first page are all retrieved; and starting to sequentially retrieve data of a plurality of second sectors of a second page of the pages in response to the second read command after the data of the first sectors of the first page are all retrieved.

Abstract: A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided.

Abstract: A storage controller, when writing n sets of data into a first storage device, adds dummy data to other sets of data except for a first set of data having a largest size among the n sets of data such that sizes of other sets of data become equal to the size of the first set of data, calculates (n?1) parities based on the first set of data and the other sets of data, and when reading the n sets of data from the first storage device, concurrently performs a processing of reading a second set of data having a smallest size among the n sets of data from the first storage device and a processing of restoring each of two or more sets of data in the n sets of data except for the second set of data, by using the (n?1) parities and the dummy data.

Abstract: A method for promoting fault tolerance and recovery in a computing system including at least one processing node includes promoting availability and recovery of a first processing node, by, at the first processing node, generating first spawn using a spawner that has been assigned a first generation-indicator so that its spawn inherits the first generation indicator, beginning a checkpoint interval to generate nodal recovery information, suspending the spawner from generating spawn, assigning, to the spawner, a second generation-indicator that differs from the first one, resuming the spawner, so that it generates second spawn that inherits the second generation-indicator, controlling an extent to which the second spawn writes to memory, and after committing nodal recovery information acquired during the checkpoint to durable storage, releasing control over the extent to which the second spawn can write to memory.

Abstract: According to one embodiment of the present invention, a system for managing data within a plurality of data management architectures comprises at least one processor. The system persists an entity managed by a first data management architecture to a second data management architecture. The first data management architecture manages entity data within one or more data sources, while the second data management architecture manages persisted entities with data from the one or more data sources within a common repository. A modification to data of the persisted entity is detected within the one or more data sources, and the modified data is synchronized with the persisted entity in the repository of the second data management architecture. Embodiments of the present invention further include a method and computer program product for managing data within a plurality of data management architectures in substantially the same manner described above.

Abstract: A computer-implemented method for managing data protection of storage units may include 1) providing a user interface that enables a user to configure data protection policies for storage units, 2) selecting at least one storage unit for data protection, 3) enabling the user to configure, through the user interface, a data protection policy to schedule a data backup of the storage unit, and 4) enabling the user to configure, through the same user interface, the same data protection policy to schedule a data transfer operation from the storage unit to an additional storage unit. The data transfer operation may include at least one of a replication operation and a continuous data protection operation. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A variable checkpoint mechanism in a streams manager checkpoints a streaming application based on periodic time periods for checkpoints. The variable checkpoint mechanism can take a checkpoint before a periodic time period ends when a spike is coming, or can take a checkpoint after the periodic time period ends when there is backpressure in a consistent region of the streaming application. When there is no anticipated spike coming and when there is no backpressure in a consistent region of the streaming application, the checkpoint is performed at the normal end of the periodic time period for checkpoints. In this manner the checkpoint timing of the variable checkpoint mechanism can be adjusted real-time to minimize the negative impact of checkpointing on the performance of the streaming application.

Abstract: Systems and techniques are described for protecting virtual machines from network failures. A described technique includes running a virtual machine on a first source host; replicating, over a first network, data related to the virtual machine to a destination host; determining that the destination host has become unreachable, over the first network, from the first source host; determining whether a second source host can reach the destination host over the first network or a second network; determining whether the virtual machine can run on the second source host; and running the virtual machine on the second source host.

Abstract: Scalable data storage techniques are described. In one or more implementations, data is obtained by one or more computing devices that describes fault domains in a storage hierarchy and available storage resources in a data storage pool. Operational characteristics are ascertained, by the one or more computing devices, of devices associated with the available storage resources within one or more levels of the storage hierarchy. Distribution of metadata is assigned by the one or more computing devices to one or more particular data storage devices within the data storage pool based on the described fault domains and the ascertained operational characteristics of devices within one or more levels of the storage hierarchy.

Abstract: According to one aspect, a control entity (such as a policy server) in communication with a plurality of border routers in a network, generates failover entries for one or more traffic flows. Each failover entry specifies a backup path to be used by a border router when the border router determines that a wide area network interface of the border router has failed. The control entity sends the failover entries to each of the border routers. A border router operating in a network stores failover entries for one or more traffic flows. For packets received at the border router either from a local area network interface or via a tunnel from another border router, when the border router detects that the wide area network interface has failed, the border router determines how to handle the packets based on the stored failover entries.

Abstract: Described herein are methods, systems, and software for accommodating failover of a content node in a content delivery network. In one example, a method of operating a control node includes receiving content requests issued by end user devices. The method further provides, for at least a first content request, mapping a first connection between a first end user device and a first content node, the first connection defined by at least a network address of the first end user device and a virtual next hop network address, and directing traffic associated with the first connection to the first content node using at least the virtual next hop network address. The method also includes identifying a service interruption associated with the first content node and, responsive to the service interruption, identifying a second content node to handle the communications for the first connection.

Abstract: A PCIE switch-based server system, switching method and device are disclosed. The system includes: an active PCIE switch device, where the active PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; a standby PCIE switch device, where the standby PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; where the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device are interconnected, so that the standby PCIE switch device obtains switch network configuration information of the active PCIE switch device through the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device.

Abstract: In one or more aspects, a determination is made as to whether a connector is securely fastened, whether the connector connected within a socket structure is the expected connector for that socket structure, and/or whether connectors coupled to one another via one or more cables are properly positioned for communication between them. Information on selected physical connection elements of a connector is used to determine one or more structural characteristics of the cable(s) connected to the connector and to determine whether the connector is the expected connector for a particular socket structure.

Abstract: Remote computing resource service providers, including online retailer, provide externally facing computer systems that allow users to interact with the service provider. Furthermore, the service provider may maintain computer systems and service inside an isolated network not exposed to users. Occasionally, service providers may test these externally facing computer systems using one or more external hosts operating on a public network. A coordinator may archive aggregated testing resources located on the isolated network and deploy the testing resources to the one or more external hosts. A database may be used to track the deployment state of the one or more external hosts in order to allow the coordinator to manage the testing process.

Abstract: An object of the present invention is to provide an abnormality diagnostic system that can enhance diagnostic precision even if a computer arranged on the machine side does not have sufficient throughput in diagnosing a condition of a machine or equipment based upon time series data generated by a sensor and can reduce communication capacity because communication data volume decreases and industrial machinery provided with the abnormality diagnostic system. A diagnostic device on the machine side 2 diagnoses time series data generated by a sensor, acquires a primary diagnostic result, extracts time series data related to the primary diagnostic result and outputs it to a diagnostic device on the server side 3 together with the primary diagnostic result, the diagnostic device on the server side 3 diagnoses the time series data, acquires a secondary diagnostic result, and displays the secondary diagnostic result together with the primary diagnostic result.

Abstract: A service data record system (SDR) and a data record method used to record data of an electronic device, such as a point of sale or service (POS) device. The electronic device includes a plurality of electronic units and a control unit. The control unit is used to receive and sift electronic data set of the electronic units. The service data record system includes a storage unit and a micro processing unit, and the micro processing unit is connected with the storage unit and the control unit. The micro processing unit is used to receive the sifted electronic data and transmit all the received electronic data to the storage unit.

Abstract: A controller area network (CAN) includes a CAN bus having a CAN-H wire, a CAN-L wire, and a pair of CAN bus terminators located at opposite ends of the CAN bus. The CAN further includes a plurality of nodes including controllers wherein at least one of the controllers is a monitoring controller. The monitoring controller includes a CAN monitoring routine for detecting a wire short fault in the CAN bus and its location.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: A processing method includes: collecting processing information indicating a processing state of an application executed by an information processing device and operational information indicating operational states of processing elements that are identified on the basis of configuration information stored in a storage unit and are involved in the execution of the application; determining whether or not there is a correlation between the processing state and an operational state of each of the processing elements on the basis of the processing information and the operational information when a delay of a process of the application is detected on the basis of the processing information; and extracting, from among the processing elements, a processing element of which an operational state has a correlation with the processing state on the basis of the determination.

Abstract: A method and system for data pipeline monitoring receives an event data object and a current status data object from one or more subsystems of a pipeline. The system analyzes the event data object and the current status data object to determine a first and second validation value. The system, in response to determining that either the first or second validation value is not valid, sends a notification.

Abstract: A set of entry blocks is allocated. An entry block is configured with a set of monitoring attributes to store monitoring data corresponding to a monitoring request. The entry block is updated with an identifier supplied in the monitoring request. The entry block is used to store the monitoring data responsive to the monitoring request. The monitoring data comprises a continuous record of data changes at a requested location in memory from a beginning to an end a of an event corresponding to the monitoring request. A size of the monitoring data is distinct from another size of another monitoring data stored in another entry block in the set of entry blocks responsive to another monitoring request. An operation specified in the monitoring request is performed on a part of the monitoring data accessible from a monitoring attribute in the set of monitoring attributes of the entry block.

Abstract: An apparatus for processing data is disclosed in which the operations of data processing circuitry are monitored by one or more trace data sources which generate items of trace data indicative of the data processing operations performed by the data processing circuitry. Trace data source identifiers in a resulting trace stream indicate the source of items of trace data and a selected trace data source identifier is included in the trace stream in response to a received flush request signal. All items of trace data generated before the apparatus received the flush request signal are included in the trace stream before the selected trace data source identifier, such that the conclusion of the response of the apparatus to the flush request signal can be identified.

Abstract: A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.

Abstract: To identify a source of a memory leak in an application, a pattern of objects is identified in an object hierarchy of a heap dump, the pattern including an indication of the memory leak. The pattern is matched with a metadata of the application. A static entry in the metadata describes a relationship between a component of the application and an object of a class used in the component. A flow entry in the metadata describes a relationship between a pattern of instantiation of a set of objects corresponding to a set of classes and an operation performed using the application. When the pattern matches the flow entry in the flow section of the metadata, a conclusion is drawn that the memory leak is caused in the operation identified in the flow entry. A portion of a code that participates in the operation is selected for modification.