Abstract: The present disclosure relates to maintaining assertions in an integrated development environment (IDE) tool. According to one embodiment, while the IDE tool is compiling the source code of a development project, the IDE tool generates at least a first compiler warning. The first compiler warning generally corresponds to at least one line of source code in a first source code component of the development project. A first set of assertions to add to the source code of the development project is determined based on the line of source code that resulted in the first compiler warning. The IDE tool adds the first set of assertions to the source code of the development project. The first set of assertions are compiled as part of the source code of the development project.

Abstract: In general, in one aspect, the technology relates to a method for composable testing. The method may include executing a story by, for at least one step in the story: identifying, from a plurality of generic compiled code interfaces, a code interface matching the step, identifying a user interface (UI) widget referenced in the step, issuing a call to testing script code, the call having a parameter of the UI widget, and executing the call using the testing script code. The method may further include generating a story report from executing the story, and storing the story report.

Abstract: A method for listing optimal machine instances in a computing environment based on user context is provided. The method includes receiving a task request based on a first task to be performed within the computing environment, identifying one or more similar tasks by comparing metadata for the first task to metadata for a plurality of other tasks based on a classification analysis, selecting the one or more similar tasks based on a result from the classification analysis exceeding a predetermined confidence level, and generating a list of one or more previous machine instances corresponding to the one or more similar tasks. The list of previous machine instances is associated with instructions to commence the previous machine instances. The plurality of other tasks include previous tasks performed within the computing environment on corresponding previous machine instances. The machine instances may include a virtual machine (VM) instance or a physical machine instance.

Abstract: A test coverage analysis method and corresponding apparatus are disclosed, wherein, by executing the program under test using one or more test cases, generating one or more heapdump files containing the call stack information of the program under test, and analyzing the call stack information in the one or more heapdump files, the coverage information of the one or more test cases in terms of functions in the program under test is obtained.

Abstract: Detecting error states when interacting with web applications is performed by accessing a first web page of a web application, determining that the first web page includes an input validation operation, configuring an input to cause the input validation operation to effect an error state, providing the input to the first web page, thereby effecting the error state, identifying a feature that is absent from the first web page before the input is provided to the first web page and present in the first web page after the input is provided to the first web page, and detecting that a second web page of the web application is in an error state if the feature is present in the second web page.

Abstract: A computing system can include memory management capabilities. In one embodiment, the system receives a request to update a first size of each of a plurality of portions of memory to a second size. The plurality of portions of memory can be associated with a first memory pool and the first memory pool can be associated with a memory pool instance. The system creates a memory pool subinstance based on the request. The memory pool subinstance can be associated with the memory pool instance. The system associates a second memory pool with the memory pool subinstance. The second memory pool comprises portions of memory of the second size and the second memory pool is associated with the memory pool instance.

Abstract: A data storage system can automatically improve the layout of data blocks on a mass storage subsystem by collecting optimization information during both read and write activities, then processing the optimization information to limit the impact of optimization activities on the system's response to client requests. Processing read-path optimization information and write-path optimization information through shared rate-limiting logic simplifies system administration and promotes phased implementation, which can reduce the difficulty of developing a self-optimizing storage server.

Abstract: A computer system, having a non-volatile storage unit (152), a main storage unit (151), and a data processor (102) including a memory management unit (102A) for managing a program stored in the non-volatile storage unit and the main storage unit to transfer a program stored in the non-volatile storage unit to the main storage unit, wherein the memory management unit (102A) includes a program storage control function of storing a program subjected to predetermined data conversion and a program yet to be subjected to predetermined data conversion in the non-volatile storage unit, and a function of combining programs subjected to predetermined data conversion so as not to bridge over a boundary between blocks at the execution of the program storage control function, as well as, at a first access to a certain block, expanding all the data included in the block to a corresponding block of the main storage unit.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid checkpointed memory. A method includes referencing data of a range of virtual memory of a host. The referenced data is already stored by a non-volatile medium. A method includes writing, to a non-volatile medium, data of a range of virtual memory that is not stored by the non-volatile medium. A method includes providing access to data of a range of virtual memory from a non-volatile medium using a persistent identifier associated with referenced data and written data.

Abstract: A device includes one or more data storage media having a main storage area, and includes a non-volatile cache memory and a controller. The controller stores a plurality of data packets into a plurality of physical locations in the main storage area. Each of the data packets is associated with a different logical block address (LBA), and each of the physical locations is associated with a different physical location address (PLA). The controller generates mapping information that links the different LBAs to the different PLAs. Upon detecting a soft error when reading a data packet stored in a physical location, the controller relocates the data packet associated with the soft error to a physical location of the non-volatile cache memory. The controller also marks the physical location as a suspect location. The controller updates the mapping information to reflect the relocation of the data packet associated with the soft error.

Abstract: Examples of techniques for pre-allocating save areas of memory of a computer processing system are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include initiating, by a host processing device, a control program. The method may further include, responsive to initiating the control program, pre-allocating, by the host processing device, a plurality of save areas for each of a plurality of processors, wherein the plurality of save areas are anchored in a fixed area of the memory for each of the plurality of processors.

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract: A method for changing software in a memory of an electronic control unit, wherein each memory address from the overlay memory can be assigned to a memory address in the read-only memory by an assignment information item. During a run time of the control unit, at least a functional part of a bypass routine that is to at least partially replace an original program routine is stored in an address range in the overlay memory, or a jump instruction is stored in the overlay memory as the first part of a bypass routine that refers to a second part of the bypass routine that is stored in an address range accessible to the processor. To activate an overlay functionality the address and/or the address range of the overlay memory are assigned to an address or address range of the program routine to be replaced.

Abstract: A method for a device to optimize memory includes: when a newly created process needs to be added into a control group, detecting whether a total resource value of memory resources occupied by all processes in the control group at a current moment reaches a critical resource value; if it is detected that the total resource value of memory resources occupied by all processes in the control group at the current moment reaches the critical resource value, cancelling restriction of the predetermined resource threshold on the control group and adding the newly created process into the control group that is not restricted by the predetermined resource threshold; and performing a swap-out operation on memory resources occupied by an idle process in the control group, so that the total resource value of memory resources occupied by all processes in the control group is less than the predetermined resource threshold.

Abstract: Described are techniques for processing I/O operations. A read operation is received to read first data from a first location. It is determined whether the read operation is a read miss and whether non-location metadata for the first location is stored in cache. Responsive to determining that the read operation is a read miss and that the non-location metadata for the first location is not stored in cache, first processing is performed that includes issuing concurrently a first read request to read the first data from physical storage and a second read request to read the non-location metadata for the first location from physical storage.

Abstract: A diagnostic apparatus comprises a diagnostic data buffer constituting a volatile memory, and a non-volatile memory capable of receiving data from the buffer. A data buffer controller is also provided and is operably coupled to the buffer and has an event alert input and a data channel monitoring input for receiving diagnostic data. The buffer receives, when the state of a buffer status memory indicates that the buffer is in an unprotected state, at least part of the diagnostic data received by the controller via the data channel monitoring input to the buffer and the controller sets the state of the buffer status memory to indicate the protected state in response to receipt of an event alert received via the event alert input. A controller monitors the buffer status memory and copies a portion of the buffer to the non-volatile memory in response to the buffer status memory being set to be indicative of the protected state.

Abstract: A group table includes one or more groups. A synch command including a synch address range is received. An order data of the one or more groups is flushed is determined by whether the synch address range is included in the one or more groups.

Abstract: A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores.

Abstract: In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote computing nodes, responsive to the cache miss. A request for a state of the cache line on the one or more remote computing nodes is broadcast to the one or more remote computing nodes, responsive to the cache miss. A resource credit is received from a first remote computing node of the one or more remote computing nodes, responsive to the request. The resource credit indicates that the first remote computing node will not participate in completing the request. The resource on the first remote computing node is released, responsive to receiving the resource credit from the first remote computing node.

Abstract: An apparatus, system, and method are disclosed for managing eviction of data. A cache write module stores data on a non-volatile storage device sequentially using a log-based storage structure having a head region and a tail region. A direct cache module caches data on the non-volatile storage device using the log-based storage structure. The data is associated with storage operations between a host and a backing store storage device. An eviction module evicts data of at least one region in succession from the log-based storage structure starting with the tail region and progressing toward the head region.

Abstract: Providing shared cache memory allocation control in shared cached memory systems is disclosed. In one aspect, a cache controller of a shared cache memory system comprising a plurality of cache lines is provided. The cache controller comprises a cache allocation circuit providing a minimum mapping bitmask for mapping a Quality of Service (QoS) class to a minimum partition of the cache lines, and a maximum mapping bitmask for mapping the QoS class to a maximum partition of the cache lines. The cache allocation circuit receives a memory access request comprising a QoS identifier (QoSID) of the QoS class, and is configured to determine whether the memory access request corresponds to a cache line of the plurality of cache lines. If not, the cache allocation circuit selects, as a target partition, the minimum partition mapped to the QoS class or the maximum partition mapped to the QoS class.

Abstract: A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: Methods for encoding file system metadata are described herein. According to one embodiment, a file system cache is maintained including information representing relationships between inodes and disk blocks of a disk having disk sections. Each disk section includes a data segment and a header encoding metadata for describing the data section of each disk section. The metadata is encoded using a set partitioning algorithm and each set represents a set of disk blocks. In response to a file system request for reading a disk section, metadata associated with the disk section is retrieved and decoded to extract information representing a relationship between inodes and disk blocks associated with the requested disk section. The file system request is then serviced using the decoded metadata and the associated data segment and one or more entries of the file system cache are updated using the decoded metadata.

Abstract: A method and a system for cache management in system interfacing to a cloud storage. The cache has two layers: the filter layer for tracing read access to the data blocks and the cache layer for keeping the actual data blocks. The layer two consists of two modules—a main cache and a boot cache. The boot cache is filled during the short period of time after the first file open operation. The boot cache also has a limit on the amount of data that can be put into the cache for the particular file. The filter layer detects continuous read access pattern and avoids caching data, if the data is read continuously beyond some limit.

Abstract: A data distribution device includes: a memory configured to store cache data of data to be distributed; and a processor coupled to the memory and configured to: read the cache data from the memory in accordance with a request message received from other devices to distribute the cache data to the other devices, update, when the request message is received, a counter value that gets closer to a given value with time, so as to make the counter value move away from the given value in accordance with a reference value that is a reciprocal of a threshold value of a reception rate of the request message, whether or not to store the cache data being determined based on the reception rate; and discard the cache data in the memory when the counter value becomes the given value.

Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.

Abstract: In one embodiment, a method for detecting false sharing includes running code on a plurality of cores, where the code includes instrumentation and tracking cache invalidations in the code while running the code to produce tracked invalidations in accordance with the instrumentation, where tracking the cache invalidations includes tracking cache accesses to a plurality of cache lines by a plurality of tasks. The method also includes reporting false sharing in accordance with the tracked invalidations to produce a false sharing report.

Abstract: A method, computer program product, and computing system for receiving an indication of a cold cache event within a storage system. The storage system includes a multi-tiered data array including at least a faster data tier and a slower data tier. A data list that identifies at least a portion of the data included within the faster data tier of the multi-tiered data array is obtained from the multi-tiered data array. At least a portion of the data identified within the data list is requested from the multi-tiered data array, thus defining the requested data. The requested data is received from the multi-tiered data array.

Abstract: A method and circuit arrangement selectively perform regular expression matching in connection with accessing data with a processing unit based upon one or more regular expression matching-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A regular expression matching-related attribute in such a data structure may be used to control whether data being communicated between the processing unit and a communications bus is routed through an expression engine integrated with the processing unit such that regular expression matching may be performed in association with the data communication.

Abstract: Embodiments are directed to a method of accessing a data frame, wherein a first portion of the data frame is in a first memory block, and wherein a second portion of the data frame is in a second memory block. The method includes determining that an access of the data frame crosses a boundary between the first second memory blocks, determining that an attempted translation of an address of the first portion of the data frame in the first memory block did not result in a translation fault, and accessing the first portion of the data frame. The method further includes, based at least in part on a determination that an attempted translation of an address of the second portion of the data frame in the second memory block resulted in a translation fault, accessing at least one default character as a replacement for accessing the second portion of the data frame.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: A page compression strategy classifies uncompressed pages selected for compression. Similarly classified pages are compressed and bound into a single logical page. For logical pages having pages with more than one classification, a weighting factor is determined for the logical page.

Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A device includes a Standard Bus Interface Circuit (SBIC), a memory interface circuit, a Direct Memory Access (DMA) controller, and an Interlaken Look-Aside (ILA) interface circuit. A search key data set including multiple search keys is received via the SBIC and is written to an external memory via the memory interface circuit. The DMA controller receives a descriptor via the SBIC, generates a search key data request, receives the search key data set, and selects a single search key from the set. The ILA interface circuit receives the search key from the DMA controller, generates and ILA packet including the search key, and sends the ILA packet to an external transactional memory device that generates a result data value. The DMA controller receives the result data value via the ILA interface circuit, writes the result data value to the external memory, and sends a DMA completion notification.

Abstract: An I/O DMA address may be translated for a flexible number of entries in a translation validation table (TVT) for a partitionable endpoint number, when a particular entry in the TVT is accessed based on the partitionable endpoint number. A presence of an extended mode bit can be detected in a particular TVT entry. Based on the presence of the extended mode bit, an entry in the extended TVT can be accessed and used to translate the I/O DMA address to a physical address.

Abstract: The present invention relates to a secure caching technique for shared distributed caches. A method in accordance with an embodiment of the present invention includes: encrypting a key K to provide a secure key, the key K corresponding to a value to be stored in a cache; and storing the value in the cache using the secure key.

Abstract: Systems, apparatuses and methods may provide for receiving an incoming request to access a memory region protected by counter mode encryption and a counter tree structure having a plurality of levels. Additionally, the incoming request may be accepted and a determination may be made as to whether to suspend the incoming request on a per-level basis with respect to the counter tree structure.

Abstract: Embodiments of techniques and systems associated with roots-of-trust (RTMs) for measurement of virtual machines (VMs) are disclosed. In some embodiments, a computing platform may provide a virtual machine RTM (vRTM) in a first secure enclave of the computing platform. The computing platform may be configured to perform an integrity measurement of the first secure enclave. The computing platform may provide a virtual machine trusted platform module (vTPM), for a guest VM, outside the first secure enclave of the computing platform. The computing platform may initiate a chain of integrity measurements between the vRTM and a resource of the guest VM. Other embodiments may be described and/or claimed.

Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.

Abstract: A streaming multiprocessor in a parallel processing subsystem processes atomic operations for multiple threads in a multi-threaded architecture. The streaming multiprocessor receives a request from a thread in a thread group to acquire access to a memory location in a lock-protected shared memory, and determines whether a address lock in a plurality of address locks is asserted, where the address lock is associated the memory location. If the address lock is asserted, then the streaming multiprocessor refuses the request. Otherwise, the streaming multiprocessor asserts the address lock, asserts a thread group lock in a plurality of thread group locks, where the thread group lock is associated with the thread group, and grants the request. One advantage of the disclosed techniques is that acquired locks are released when a thread is preempted. As a result, a preempted thread that has previously acquired a lock does not retain the lock indefinitely.

Abstract: There is described a chip comprising a one-time programmable (OTP) memory programmable to store chip configuration data, and a verification module operable to access the OTP memory. The verification module is operable to receive a verification request relating to a specified portion of the OTP memory, the verification request comprising mask data defining the specified portion of the OTP memory. In response to the verification request, the verification module is operable to use the mask data and the OTP memory to generate verification data relating to the specified portion of the OTP memory, the verification data further being generated based on a secret key of the chip. There is also described a chip-implemented method of generating verification data relating to a specified portion of a one-time programmable (OTP) memory of the chip. There are also described methods for primary or secondary verification systems to verify a configuration of a specified portion of the OTP memory the above mentioned-chip.

Abstract: A method for providing memory protection within a signal processing system comprises receiving a memory access signal comprising at least one instruction memory region (IMR) indication. The IMR indication comprises an indication of a region of memory from which a memory access instruction was fetched, execution of said memory access instruction having resulted in the generation of the received memory access signal. The method further comprises comparing the IMR indication for the received memory access signal to at least one permitted memory region (PMR) indication for a target address of the received memory access signal, and determining whether a memory access being attempted by the memory access signal is permitted based at least partly on the comparison of the IMR indication for the received memory access signal to the PMR indication for the target address of the received memory access signal.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.

Abstract: A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority.

Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.

Abstract: PCIe devices and corresponding methods are provided wherein a length of data to be transferred is aligned to a multiple of a double word length.

Abstract: In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.