Patents Issued in July 27, 2017
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Publication number: 20170212680Abstract: Methods, systems, apparatus including computer programming encoded on a computer storage medium for efficiently storing data across memory hierarchy on one or plurality of nodes include creating ordered partitions of data based on key where partition order is achieved using highly space optimized prefix tree index. Within a partition, data is fully or partially ordered based on key. Multiple prefix tree indices are created one for each memory hierarchy and all are stored in fast memory like DRAM. Data is merged or moved from faster memory to slower memory in the hierarchy as the space is used up. Checkpoint mechanism along with WAL provides recovery guarantee and data snapshots. Distributed data storage systems like databases/key value stores can utilize this data storage mechanism to store and retrieve data efficiently across memory hierarchy on one or plurality of nodes.Type: ApplicationFiled: December 31, 2016Publication date: July 27, 2017Inventor: Suraj Prabhakar Waghulde
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Publication number: 20170212681Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes receiving a slice write request via a network that includes a data slice and extracting metadata from the data slice. The metadata is stored in a metadata storage tree in a first memory device of the DST execution unit and the data slice is stored in a slice storage tree in a second memory device of the DST execution unit based on tree utilization parameters.Type: ApplicationFiled: January 3, 2017Publication date: July 27, 2017Inventor: Renars W. Narubin
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Publication number: 20170212682Abstract: A time de-interleaving method is applied to a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a first time interleaved block and a second time interleaved block. The time de-interleaving method includes: reading a first part of cells of the first time interleaved block from a memory; releasing a memory space corresponding to the first part of the cells in the memory; and writing a second part of cells of the second time interleaved block into the memory space before the first time interleaved block is completely read out from memory.Type: ApplicationFiled: January 5, 2017Publication date: July 27, 2017Inventor: CHUN-CHIEH WANG
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Publication number: 20170212683Abstract: A computing device includes an interface configured to interface and communicate with a dispersed or distributed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations including to DSN traffic and storage usage among storage units (SUs) that distributedly store encoded data slices (EDSs) associated with a data object based on a Decentralized, or Distributed, Agreement Protocol (DAP) system configuration. For some instances of the DSN traffic, the computing device configures and deploys additional computing device(s) to service EDS data access operations. For some instances of the storage usage among the SUs, the computing device configures and deploys additional SU(s) to store distributedly the set of EDSs and updates the DAP system configuration.Type: ApplicationFiled: January 9, 2017Publication date: July 27, 2017Inventors: Thomas D. Cocagne, Justin M. Jarczyk, Andrew G. Peake, John R. Wachowski
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Publication number: 20170212684Abstract: According to one aspect, a method includes determining whether at least one memory storage unit in a first stage of a multi-stage array is available for use by a first counter associated with the first stage, and allocating the at least one memory storage unit for use by the first counter when the at least one memory storage unit is available. When the at least one memory storage unit is not available for use by the first counter, the method includes identifying a second counter stored in a first location in the first stage, the first location including a first memory storage unit and a second memory storage unit, and moving the second counter to a second stage of the multi-stage array, storing a pointer to the second stage in the first memory storage unit, and allocating the second memory storage unit to the first counter.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Inventors: Sarang Dharmapurikar, Ganlin Wu, Alex Seibulescu, Wanli Wu
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Publication number: 20170212685Abstract: A control device to be connected to a host and a disk device including at least one Redundant Arrays of Independent Disks (RAID) set, the control device includes circuitry that performs data communication with the host by a protocol capable of connecting one logical device in the RAID set to each port, virtually sets a plurality of ports which are defined by the protocol, sets a plurality of logical devices in the RAID set included in the disk device, and connects the plurality of logical devices to the plurality of ports, respectively, and the circuitry is to be connected to the host through an interface.Type: ApplicationFiled: January 24, 2017Publication date: July 27, 2017Applicants: BIOS CORPORATION, MELCO HOLDINGS INC.Inventor: Seimei MATSUMURA
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Publication number: 20170212686Abstract: A cluster of computer system nodes connected by a storage area network include two classes of nodes. The first class of nodes can act as clients or servers, while the other nodes can only be clients. The client-only nodes require much less functionality and can be more easily supported by different operating systems. To minimize the amount of data transmitted during normal operation, the server responsible for maintaining a cluster configuration database repeatedly multicasts the IP address, its incarnation number and the most recent database generation number. Each node stores this information and when a change is detected, each node can request an update of the data needed by that node. A client-only node uses the IP address of the server to connect to the server, to download the information from the cluster database required by the client-only node and to upload local disk connectivity information.Type: ApplicationFiled: February 8, 2017Publication date: July 27, 2017Inventors: Daniel Moore, Andrew Gildfind
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Publication number: 20170212687Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A number of pages that may be treated as non-volatile may be determined based on demand for non-volatile storage by at least one application executing on the computing device.Type: ApplicationFiled: August 30, 2016Publication date: July 27, 2017Inventors: Bryan D. Kelly, Mallik Bulusu, Ravi Mysore Shantamurthy, Tom L. Nguyen
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Publication number: 20170212688Abstract: Methods and systems are described for controlling an automation and security system. According to at least one embodiment, an apparatus for data storage in an automation and security system includes a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions are executable by a processor to receive data at a first device, store a copy of the data on the first device, fragment the data into a plurality of data fragments, transmit the plurality of data fragments to a plurality of remote devices, and store some of the plurality of data fragments on each of the plurality of remote devices.Type: ApplicationFiled: February 6, 2017Publication date: July 27, 2017Inventors: Jungtaik Hwang, Matthew J. Eyring, Jeremy B. Warren, James Ellis Nye
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Publication number: 20170212689Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Enrique Musoll, Weihuang Wang
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Publication number: 20170212690Abstract: A technique recovers from a low space condition associated with storage space reserved in an extent store to accommodate write requests received from a host and associated metadata managed by a layered file system of a storage input/output (I/O) stack executing on one or more nodes of a cluster. The write requests, including user data, are persistently recorded on non-volatile random access memory (NVRAM) prior to returning an acknowledgement to the host by a persistence layer of the storage I/O stack. Volume metadata managed by a volume layer of the layered file system is embodied as mappings from logical block addresses (LBAs) of a logical unit (LUN) accessible by the host to extent keys maintained by an extent store layer of the layered file system. Extent store metadata managed by the extent store layer is embodied as mappings from the extent keys to the storage locations of the extents on storage devices of storage arrays coupled to the nodes of the cluster.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Inventors: SRIRANJANI BABU, MANDAR NAIK, SRINATH KRISHNAMACHARI, DHAVAL PATEL
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Publication number: 20170212691Abstract: A first block storage device sharing an object storage device with a second block storage device has: plural kinds of physical devices having different access response performances; and a hierarchical logical disk created by using the storage areas of the physical devices and the storage area of the object storage device. When the access frequency of a logical block stored in a hierarchy one level above a lowest hierarchy falls below a threshold, the first block storage device searches the object storage device for a logical block having the hash of the logical block as a content address. When the search fails, the first block storage device transmits the logical block to the object storage device to change a hierarchy to store the logical block to the lowest hierarchy, whereas when the search succeeds, omits the transmission and changes a hierarchy to store the logical block to the lowest hierarchy.Type: ApplicationFiled: January 18, 2017Publication date: July 27, 2017Applicant: NEC CORPORATIONInventor: Yoshiyuki KATSUKI
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Publication number: 20170212692Abstract: A mechanism is provided in a non-volatile memory controller for reducing read access latency by straddling pages across non-volatile memory channels. Responsive to a request to write a logical page to a non-volatile memory array, the non-volatile memory controller determines whether the logical page fits into a current physical page. Responsive to determining the logical page does not fit into the current physical page, the non-volatile memory controller writes a first portion of the logical page to a first physical page in a first block and writes a second portion of the logical page to a second physical page in a second block. The first physical page and the second physical page are on different non-volatile memory channels.Type: ApplicationFiled: January 25, 2016Publication date: July 27, 2017Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Thomas Parnell, Roman Pletka, Sasa Tomic
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Publication number: 20170212693Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. The controller may be coupled to the memory and configured to process a plurality of read/write operations to/from the memory, store data in the plurality of memory devices using units of super-blocks, and generate a number of unique weight statistics in a single read operation by reading a number of dies within a super-block with dissimilar read reference voltages. Each super-block generally includes a block from a die of each of the plurality of memory devices. The controller may be further configured to split the number of dies in each super-block into two sets and collect page weights for upper pages from one of the two sets and page weights for lower pages from the other of the two sets.Type: ApplicationFiled: April 6, 2017Publication date: July 27, 2017Inventors: Sundararajan Sankaranarayanan, Erich F. Haratsch
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Publication number: 20170212694Abstract: Described embodiments include Memory Systems that may shadow certain data stored in a first memory device (e.g. NAND flash device) onto a second memory device (e.g. DRAM device). Memory systems may train and/or re-organize stored data to facilitate the selection of data to be shadowed. Initial responses to memory commands may be serviced from the first memory device, which may have a lower latency than the second memory device. The remaining data may be serviced from the second memory device. A controller may begin to access the remaining data while the initial response is being provided from the first memory device, which may reduce the apparent latency associated with the second memory device.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: YI Chen, Yukiyasu Murakami
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Publication number: 20170212695Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Timothy Hollis, Roy E. Greeff
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Publication number: 20170212696Abstract: A memory device comprises an output buffer and a control circuit. The control circuit is configured to receive a system clock signal at an input of the control circuit. The control circuit is configured to generate a data transition signal based on the system clock signal. The control circuit is configured to provide the data transition signal to the output buffer of the memory device. The output buffer is configured to output memory data based on the data transition signal.Type: ApplicationFiled: January 26, 2016Publication date: July 27, 2017Applicant: Macronix International Co., Ltd.Inventors: Shang-Chi Yang, Su-Chueh Lo
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Publication number: 20170212697Abstract: A sequence of storage devices of a data store may include one or more stripesets for storing data stripes of different lengths and of different types. Each data stripe may be stored in a prefix or other portion of a stripeset. Each data stripe may be identified by an array of addresses that identify each page of the data stripe on each included storage device. When a first storage device of a stripeset becomes full, the stripeset may be shifted by removing the full storage device from the stripeset, and adding a next storage device of the data store to the stripeset.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Colin Reid, Philip A. Bernstein
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Publication number: 20170212698Abstract: A computing system includes: a host processor configured to: determine a compression possibility based on a data type; compress data based on the compression possibility; determine a caching possibility based on the data; execute a batch write request including multiple instances of a write request based on the caching possibility, a store capacity meeting or exceeding a store threshold, or a combination thereof; and a nonvolatile memory, coupled to the host processor, configured to store the data based on the batch write request.Type: ApplicationFiled: April 11, 2016Publication date: July 27, 2017Inventors: Varun Singh Bhadauria, Kenneth Yip, Tejas Chopra, Pradeep Bisht
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Publication number: 20170212699Abstract: When user configuration data recorded in a recording medium is written into a PLC, the PLC determines, in accordance with a combination table stored in the recording medium, if a combination of the user configuration data and firmware already stored in the PLC is suitable. In addition, when firmware recorded in the recording medium is written into the PLC, the PLC determines, in accordance with the combination table stored in the recording medium, if a combination of the firmware and user configuration data already stored in the PLC is suitable.Type: ApplicationFiled: January 15, 2015Publication date: July 27, 2017Applicant: OMRON CorporationInventors: Takehiko HIOKA, Yutaka ABE, Shinsuke KAWANOUE
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Publication number: 20170212700Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.Type: ApplicationFiled: September 2, 2016Publication date: July 27, 2017Inventor: Hyun LEE
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Publication number: 20170212701Abstract: Aspects of embodiments relate to a system for decentralized and distributed storing of data. The system comprises an application provider operative to provide a data storage (DTS) engine that is configured to generate data fragments that are associated with a source dataset received at an end-user data source (DT) device. The DTS engine is also configured such that the generated data fragments are stored on a multitude of end-user DT devices. The DTS engine is further configured to reconstruct, based on the data fragments, the source dataset.Type: ApplicationFiled: July 7, 2015Publication date: July 27, 2017Applicant: OSR Enterprises AGInventors: Orit Shifman, Elhanan Shifman
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Publication number: 20170212702Abstract: An asynchronous circuit including an asynchronous pipeline including two or more stages, each stage having: a buffering circuit for temporarily storing data to be transferred from one stage to the next based on a handshake protocol, the buffering circuit including a non-volatile memory; and a data presence detection circuit adapted to generate a data presence detection value indicating whether or not data is stored by the buffering circuit; and a control circuit adapted to perform a data back-up operation by independently controlling each buffering circuit to back-up the data it stores to its non-volatile memory based on the corresponding data presence detection value.Type: ApplicationFiled: January 26, 2017Publication date: July 27, 2017Applicants: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche ScientifiqueInventors: Eldar Zianbetov, Edith Beigne, Gregory Di Pendina
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Publication number: 20170212703Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.Type: ApplicationFiled: April 7, 2017Publication date: July 27, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Riki Suzuki, Toshikatsu Hida, Tokumasa Hara
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Publication number: 20170212704Abstract: A method for reducing power consumption of a memory of a computer device is presented. The memory includes at least two channels, each channel includes at least two storage units, a dirty data storage area is set in the memory, and the dirty data storage area includes at least one storage unit in each channel. After the computer device encounters a power failure, a backup power supply is turned on to supply power to the memory, then the storage unit included in the dirty data storage area is kept in a normal operating state, and a storage unit outside the dirty data storage area in the memory is caused to enter a self-refreshing state. Data in the dirty data storage area is then written to a non-volatile storage area of the computer device.Type: ApplicationFiled: April 7, 2017Publication date: July 27, 2017Inventors: Zhibing Li, Yongjiang Yi
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Publication number: 20170212705Abstract: A system and method for improving the distribution of data extent allocation in dynamic disk pool systems is disclosed. A storage system includes a storage controller that calls a hashing function to select storage devices on which to allocate data extents when such is requested. The hashing function takes into consideration a weight associated with each storage device in the dynamic disk pool. Once a storage device is selected, the weight associated with that storage device is reduced by a predetermined amount. This reduces the probability that the selected storage device is selected at a subsequent time. When the data extent is de-allocated, the weight associated with the affected storage device containing the now-de-allocated data extent is increased by a predetermined amount. This increases the probability that the storage device is selected at a subsequent time.Type: ApplicationFiled: January 26, 2016Publication date: July 27, 2017Inventors: Kevin Kidney, Austin Longo
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Publication number: 20170212706Abstract: Techniques are disclosed herein for paging I/O translation table entries. A host bridge of system hardware receives a request to fetch a first segment of an I/O translation table associated with one of a plurality of logical partitions executing in a computing system. The host bridge identifies a control register associated with the first segment. Upon determining that the first segment is paged out to the storage volume, a second segment is paged out from a location in memory to the storage volume. The first segment is paged in to the location.Type: ApplicationFiled: July 25, 2016Publication date: July 27, 2017Inventors: Travis PIZEL, Naveen RATHI
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Publication number: 20170212707Abstract: Techniques to managing non-disruptive SAN availability in a partitioned cluster comprising one or more components configured to determine whether to separate a cluster into two or more partitions, notify one or more responsive cluster nodes to separate the cluster into a first partition and a second partition, update one or more access states, notify the host that access states of one or more network paths has been updated, and provide the one or more access states. Other embodiments are described and claimed.Type: ApplicationFiled: April 5, 2017Publication date: July 27, 2017Inventors: John Hildebrand, Geoffrey Stewart Brown, Nathan Baker, John Meneghini, Frederick Knight, Santosh Rao
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DYNAMIC GARBAGE COLLECTION P/E POLICIES FOR REDUNDANT STORAGE BLOCKS AND DISTRIBUTED SOFTWARE STACKS
Publication number: 20170212708Abstract: A Solid State Drive (SSD) (110) is disclosed. The SSD (110) may include storage (218) for data, and reception circuitry (203) to receive various instructions and data. The reception circuitry (203) may receive an instruction (257) from a host machine (105) to perform garbage collection, along with a selected P/E strategy (260). The SSD (110) may include garbage collection logic (209) to perform garbage collection, possibly with a delayed Program operation if an adaptive P/E strategy (1110) is selected. The SSD (110) may also include a mapping table (221) that may identify which pages were not Programmed before victim blocks (233, 236) were erased, and therefore require replication during a delayed Program operation.Type: ApplicationFiled: April 19, 2016Publication date: July 27, 2017Inventors: SUHAS, Ashwini BATRAHALLI, Tameesh SURI -
Publication number: 20170212709Abstract: A memory device includes a memory unit comprising one or more storage regions, and a control logic suitable for generating status information representing individualized states for the one or more storage regions.Type: ApplicationFiled: June 28, 2016Publication date: July 27, 2017Inventor: Yoon-Jo OH
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Publication number: 20170212710Abstract: In one general embodiment, a computer-implemented method includes receiving at a first system a request for data, searching one or more local buffers within the first system for the requested data, determining whether the requested data is located within an additional buffer of an additional system in communication with the first system, in response to determining that the one or more local buffers within the first system do not contain the requested data, receiving the requested data by the first system from the additional buffer of the additional system, in response to determining that the requested data is located within the additional buffer of the additional system, and retrieving the requested data from a data disk within the first system, in response to determining that the requested data is not located within the additional buffer of the additional system.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Inventors: Neal E. Bohling, Roity Prieto Perez
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Publication number: 20170212711Abstract: According to one embodiment, there is provided a disk apparatus including a disk medium, a buffer memory, and a controller. The controller includes an interface circuit used to connect to the buffer memory, in an execution of a command from a host to instruct a first access operation to the disk medium by using the buffer memory. The controller is configured to perform, if a second access operation to the disk medium by using the buffer memory is performed in background, a first wait process by a time according to the second access operation. The first wait process delays a response process of the command. The response process includes the first access operation.Type: ApplicationFiled: March 9, 2016Publication date: July 27, 2017Inventor: Hiroaki Inoue
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Publication number: 20170212712Abstract: Systems, methods, devices and computer program products enable capture, processing, storage, communication and transactions related to 3-dimensional (3D) data. A system for managing 3D data includes a cloud comprising data storage devices and processors coupled to a network to receive, store and transmit data including 3D data. The system includes an entry point coupled to a 3D data generation device that receives data produced from 3D scans of an object and converts the data into a customized format for ingestion by the network. The customized format includes data and header sections, and a field for activating an algorithm including a data conversion algorithm to produce 3D data in a first data format that is different from the customized format. The system also includes an exit point that receives and produces the 3D data in the first data format that is compatible for consumption by a device at the exit point.Type: ApplicationFiled: July 8, 2015Publication date: July 27, 2017Inventors: Braxton CARTER, Justim E CARLSON
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Publication number: 20170212713Abstract: Printing images on a printing medium by means of a printer, comprising the receiving of image data for each image of a list of images to be printed on said printing medium; splitting up of the received image data of the list of images into N successive sequences corresponding to N printing steps, N being an integer greater or equal to 1, of M groups of image data of individual images, M being an integer greater than 1, each group of image data of a printing step comprising image data of at least one individual image, the number of individual images in the M groups of a given printing step corresponding to the total number of images to be printed at this printing step; sequentially for each printing step, distributing of the M groups of image data to, respectively, M distinct processing units, each processing unit sequentially processing image data of each individual image data from a received group of image data to generate a corresponding set of printable individual image data; and upon all said M processingType: ApplicationFiled: July 1, 2015Publication date: July 27, 2017Inventor: Damien IELSCH
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Publication number: 20170212714Abstract: There is provided an information distribution system including an electronic apparatus and an information distribution apparatus connected through a network, the information distribution apparatus comprising an apparatus usage information collection unit configured to collect apparatus usage information indicating usage situation of the electronic apparatus; a distribution information generating unit configured to generate distribution information to be distributed to the electronic apparatus based on the apparatus usage information; and a distribution unit configured to distribute the distribution information to the electronic apparatus; the electronic apparatus comprising a distribution information acquiring unit configured to acquire the distribution information; and a display control unit configured to display the distribution information in a display unit of the electronic apparatus.Type: ApplicationFiled: August 26, 2015Publication date: July 27, 2017Applicant: Ricoh Company, Ltd.Inventors: Hidehiko WATANABE, Hiroshi KAKII, Junya JIMBO, Naoki CHIYO
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Publication number: 20170212715Abstract: An image processing apparatus includes an executing circuitry, a macro executing circuitry, and a managing circuitry. The executing circuitry executes one or more types of image processing. The macro executing circuitry executes, with the executing circuitry, a first macro to which predetermined one or more types of image processing out of the one or more types of image processing are assigned. The predetermined one or more types of image processing includes a first type of image processing. The managing circuitry manages execution authority setting of the first type of image processing and execution authority setting of the first macro, and temporarily changes the execution authority setting of the first type of image processing on a basis of the execution authority setting of the first macro upon the execution of the first macro by the macro executing circuitry.Type: ApplicationFiled: December 19, 2016Publication date: July 27, 2017Inventor: Kimitoshi SATO
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Publication number: 20170212716Abstract: A method of controlling an image reproduction system, wherein a process duration is estimated on the basis of a measured time (D) for the processing of a number (n) of pages that have been processed already, the method comprising storing a digital table which contains a number of pre-defined job types as well as a respective correction factor (A4) for each job type; when a job is received (S1), assigning (S2) a job type to the received job; calculating (S3) a first estimate (D1) for a time needed for processing at least a specified collection of pages from the job; calculating (S4) a second estimate (D2) by multiplying the first estimate (D1) with the correction factor (A4); when said specified collection of pages has been processed, calculating a deviation of the first estimate (D1), and updating (S9) the correction factor (A4); and storing the updated correction factor.Type: ApplicationFiled: January 24, 2017Publication date: July 27, 2017Applicant: Océ Holding B.V.Inventors: Edy I.H.C. KLOMP, Tim F.P. PAFFEN
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Publication number: 20170212717Abstract: A hybrid display includes a first display having a first interface and a second display having a second interface. A third interface is configured to receive a first command that includes a first value indicating a modification of pixels in the hybrid display. A finite state machine is configured to translate the first value to a second value indicating a modification of pixels in the first display and a third value indicating a modification of pixels in the second display. The first interface transmits a second command including the second value to the first interface and a third command including the third value to the second interface. The first and second commands are transmitted at times determined by a relative delay between the first display and the second display.Type: ApplicationFiled: December 15, 2016Publication date: July 27, 2017Inventor: Zhibin Zhang
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Publication number: 20170212718Abstract: An open collaboration approach using an interactive whiteboard appliance is presented. An interactive whiteboard application executes on a computing device and causes performing receiving a request to invoke a web application. The request comprises an Internet address of the web application. A data management application executes on the computing device and causes accessing the web application using the Internet address. Upon accessing the web application, the web application is launched on the computing interactive whiteboard appliance. Upon detecting that first data has been received from the web application, a first window instance is generated and displayed on the display of the computing interactive whiteboard appliance. The first data to be processed by the first window instance is displayed on the display of the computing interactive whiteboard appliance.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Applicant: RICOH COMPANY, LTD.Inventors: Steven A. Nelson, Rathnakara Malatesha, Hiroshi Kitada, Lana Wong
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Publication number: 20170212719Abstract: A display system includes an information processing apparatus and a projector, in which the information processing apparatus includes a display unit, a communication unit, and a PC control unit that causes the display unit to display information regarding the projector with which communication is performed via the communication unit. The projector includes a communication unit, a remote control light receiving unit, and a PJ control unit that transmits an operation detection command via the communication unit in a case where the operation is received by the remote control light receiving unit. In a case where the operation detection command is received via the communication unit, the PC control unit changes an appearance of information regarding the projector having transmitted the operation detection command among information pieces displayed by the display unit.Type: ApplicationFiled: January 20, 2017Publication date: July 27, 2017Inventor: Toshiki Fujimori
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Publication number: 20170212720Abstract: An information management system includes: an audio signal acquisitor configured to acquire an audio signal representing a guide voice; a related information acquisitor configured to acquire related information that is related to the guide voice; an association manager configured to associate the related information acquired by the related information acquisitor for the guide voice with identification information that is notified to a terminal device upon emission of the guide voice corresponding to the audio signal; and an information provider configured to receive from the terminal device an information request including the identification information notified to the terminal device and to transmit to the terminal device the related information associated by the association manager with the identification information.Type: ApplicationFiled: July 27, 2015Publication date: July 27, 2017Inventors: Shota MORIGUCHI, Takahiro IWATA, Yuki SETO
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Publication number: 20170212721Abstract: A processing path may include a controller and a plurality of processing paths including a first processing path and a second processing path. The first path may be configured to generate a first digital signal based on an analog input signal and the second path may be configured to generate a second digital signal based on the analog input signal, wherein the first path has a lower gain and a higher noise floor than the second path. The controller may be configured to determine that a transition between the first path and the second path needs to occur based on the analog input signal crossing a threshold or a prediction that the input signal will cross the threshold and in response to determining the transition between the first path and the second path needs to occur, blend the transition during or near zero cross points of the analog input signal.Type: ApplicationFiled: January 21, 2016Publication date: July 27, 2017Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Aniruddha Satoskar, Daniel J. Allen, Edmund Mark Schneider, Tejasvi Das, Ku He, John L. Melanson
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Publication number: 20170212722Abstract: Disclosed is a platform enabling users to generate animations synchronized to a musical track in an app-based environment which facilitates collaboration. A method of generating such animations involves first receiving, by a host device executing an app input data from one or more input devices. The app utilizes a layers module to assign the input data to one or more layers. The app assigns input data to layers and allows modification of inputs and timestamps of the input data. The app further allows application of one or more media assets to the inputs. Users of the platform may each execute the app, or execute a companion app that allow communication to the host device. The app may also facilitate compiling the one or more layers into a musical animation file. The musical animation file may store the one or more layers and metadata identifying the musical track.Type: ApplicationFiled: January 26, 2016Publication date: July 27, 2017Inventor: Christian Grant Campbell
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Publication number: 20170212723Abstract: The following invention is a vocally activated control system for controlling an apparatus in a surgical setting, the system comprises: a. a voice sensor configured to detect vocal commands generated by surgeons during surgery; b. a signal transmitter connected to the voice sensor, the transmitter is configured to convert a vocal command into a transmittable signal and transmit it; c. a processor connected to a signal transmitter configured to receive a transmittable vocal signal, the processor is configured to convert a vocal signal to a predetermined set of operative instructions associated with the apparatus, the predetermined set of operative instructions comprising at least one instruction; and d. control means connected to the processor and apparatus; the control means is configured to receive a predetermined set of operative instructions and to cause the apparatus to operate accordingly; Said voice sensor and said transmitter are integrated within a wearable element.Type: ApplicationFiled: April 7, 2017Publication date: July 27, 2017Applicant: M.S.T. MEDICAL SURGERY TECHNOLOGIES LTDInventors: Gal ATAROT, Motti FRIMER, Tal NIR, Lior ALPERT
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Publication number: 20170212724Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.Type: ApplicationFiled: December 27, 2013Publication date: July 27, 2017Inventors: John HOWARD, Steven B. MCGOWAN, Krzysztof PERYCZ
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Publication number: 20170212725Abstract: A method and system for validating data. Warehouse data is generated by transforming source data via an ETL transformation model. A data cube is generated by transforming the warehouse data via an OLAP transformation model. A report dataset (MDS1) is generated from the data cube. A reference dataset (S) is generated from the source data. A data validation is performed, the data validation being based on a matching relationship between MDS1 and S.Type: ApplicationFiled: May 7, 2012Publication date: July 27, 2017Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xue C. Li, Xiao J. Fu, Xue F. Gao, Xin Xin
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Publication number: 20170212726Abstract: An approach for dynamically providing a prioritized list of relevant cases includes a computer generating a set of tags for a case and retrieving a set of tags for completed cases. The approach includes the computer sorting the set of tags for the case and the set of tags for the completed cases into a set of tag types. The approach includes the computer determining a set of matching tags for each of the set of tag types between the case and completed cases. Furthermore, the approach includes the computer determining an ordered list of the completed cases. The ordered list is based, at least in part, on a number of matching tags in the set of matching tags corresponding to the completed case in the completed cases, and a number of matching tags in the set of matching tags in a tag type in the set of tag types.Type: ApplicationFiled: April 5, 2017Publication date: July 27, 2017Inventors: Srinivas N.V. Gannavarapu, Praveen K. Midde, Saisaran Yaratapalli
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Publication number: 20170212727Abstract: A semiconductor chip is described that includes an instruction execution unit having a functional unit, said functional unit having minimum and maximum comparison circuitry followed by interleaving circuitry, said minimum and maximum comparison circuitry to respectively identify minimums and maximums of same positioned elements from two different sets of sorted elements, said interleaving circuitry to interleave said minimums and maximums to help form a third sorted set composed of elements from said different sets and being larger than each of said different sets.Type: ApplicationFiled: March 30, 2012Publication date: July 27, 2017Inventors: Jatin CHHUGANI, Nadathur Rajagopalan SATISH
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Publication number: 20170212728Abstract: A magnetic random number generator is disclosed. The magnetic random number generator comprises: a) a Hall cross structure comprising at least one magnetic nanowire with perpendicular magnetic anisotropy; b) an in-plane pulsed current generator operable to generate stochastic nucleation of domain walls (DWs) in the Hall cross structure; and c) a sensor configured to measure a parameter of the Hall cross structure upon DW nucleation, wherein said parameter has a value representing a random number. A greater number of Hall cross structures may be employed to generate a random number having a greater number of bits.Type: ApplicationFiled: January 20, 2017Publication date: July 27, 2017Inventors: Pankaj SETHI, Chandrasekhar MURAPAKA, Wen Siang LEW, Arindam BASU
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Publication number: 20170212729Abstract: A method, non-transitory computer readable medium, and a template management computing device that assists with generating smart architecture templates includes identifying one or more technical keywords from received data associated with one or more business requirements by comparing the received data associated with the one or more business requirements against information stored in a technical keyword database. Next, one or more template configuration files are identified based on the identified one or more technical keywords. The architecture template is generated for the received data associated with the one or more business requirements using the determined one or more template configuration files. The generated architecture template is provided wherein the provided application is template is ready to be deployed in a development and a testing environment.Type: ApplicationFiled: March 9, 2016Publication date: July 27, 2017Inventors: Kavitha Sridhar, Udayakumar Kuppuswamy