Abstract: In some examples, a container image is received, where a container is to be launched from the container image. An executable process is deployable in the container to isolate the executable process from another executable process. The container image is annotated with metadata specifying a policy. Compliance of the container image with the policy is checked in a test environment prior to publication of the container image to a registry for use in a production environment.

Abstract: In one example, reclaiming obsolete regions includes a memory organized in aligned memory blocks and storing valid variables in valid regions and obsolete variables in the obsolete regions. A memory includes a buffer region to cache the memory. A controller can search the buffer region for the obsolete regions and pair with respective valid regions and determine if start addresses of the obsolete regions are memory aligned and if not aligned, to write a small portion content of a first valid region to the start address of the aligned memory block, and to write any remaining respective valid region beginning at the start address of the aligned memory block and in multiples of the aligned memory block. Upon completion of a writing, moved respective valid regions begin at the starting address of the obsolete regions and new obsolete regions begin at end addresses of the moved respective valid regions.

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract: Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further configured to perform one or more operations to render the memory system inoperable in response to the destruct command received from the host.

Abstract: A method and apparatus for implementing a storage optimization process is provided. The method includes identifying a file for storage on a storage device. The storage device determines that the file comprises a file size that exceeds multiple physical disk blocks of the storage device by a fractional value. The file is divided into a first portion and a second portion. The first portion comprises a file size such that the first portion fits entirely within a first single block of the storage device. The second portion comprises a size such that the second portion exceeds a size of a second single block of the storage device by the fractional value. The first portion is stored within the first single block. The second portion is compressed such that a resulting compressed file fits entirely within the second single block.

Abstract: A computing system includes: a storage component including a volatile-memory device and a non-volatile memory device configured to enable persistent storage of information along with block-oriented mass storage of information; and a controller component, coupled to the storage component, configured to implement a smart memory driver configured to dynamically manage the volatile-memory device including managing a persistent memory (PM) portion, a hardware cache (HWC) portion, a block window (BW) portion, or a combination thereof within the volatile-memory device.

Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes executing a modification of a first locally cached item. A first cache broadcast is generated for transmission via a network to a plurality of additional DST processing units in response to executing the modification. Revision data is generated by evaluating a first local revision level of a second locally cached item. An update of the second locally cached item is executed when the revision data indicates that the second locally cached item is outdated.

Abstract: Enhanced adaptive profiling of ranges of values in a stream of events includes identifying a set of contiguous ranges of the values and corresponding access frequencies in the stream of events. The enhanced adaptive profiling uses a merge threshold value and a split threshold value. The set of contiguous ranges spans an entire range space of the values. Periodic traversal of the set of contiguous ranges of values and corresponding access frequencies identifies a target set of ranges of the values having corresponding access frequencies above a predetermined threshold access frequency. The target set of ranges of values has a total number of ranges less than or equal to a predetermined number of ranges. The target ranges of values span at least some of the entire range space of values. A first operation uses the target set of ranges of values.

Abstract: A method for managing cache space between one electronic device and multiple storage devices includes identifying and quantifying storage devices connected to an electronic device, and acquiring efficiency information of each identified storage device on preset occasions. Cache space of each storage device is computed on being connected to or being disconnected from the electronic device, taking account of information acquired as to efficiency and quantity of each of the storage devices. A core switch of the electronic device is controlled to allocate a computed cache space to a storage device.

Abstract: A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of DST processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

Abstract: Providing scalable dynamic random access memory (DRAM) cache management using tag directory caches is provided. In one aspect, a DRAM cache management circuit is provided to manage access to a DRAM cache in a high-bandwidth memory. The DRAM cache management circuit comprises a tag directory cache and a tag directory cache directory. The tag directory cache stores tags of frequently accessed cache lines in the DRAM cache, while the tag directory cache directory stores tags for the tag directory cache. The DRAM cache management circuit uses the tag directory cache and the tag directory cache directory to determine whether data associated with a memory address is cached in the DRAM cache of the high-bandwidth memory. Based on the tag directory cache and the tag directory cache directory, the DRAM cache management circuit may determine whether a memory operation can be performed using the DRAM cache and/or a system memory DRAM.

Abstract: A computing system includes a memory storage unit, having memory blocks, configured as a memory cache to store values of key-value pairs; and a device control unit, coupled to the memory storage unit, configured to: identify eviction targets from key-value eviction candidates in a key-value registry based on an eviction policy; calculate an associated eviction count of associated eviction candidates within the same instance of the memory blocks as the eviction targets; select an erase block as the memory blocks associated with the highest value of the associated eviction count; and interface with the memory storage unit to perform an erase operation on the erase block.

Abstract: Methods and systems for normalizing a read-write cache allocation pool for virtual desktop infrastructure (VDI) workloads are disclosed. The method includes determining a cache allocation policy; determining a range of expected input/output (I/O) levels of a storage system; determining a current I/O level of the storage system; determining a target cache allocation based on the cache allocation policy, the range of expected I/O levels, and the current I/O level, the target cache allocation including a first memory region allocated to read cache operations and a second memory region allocated to write cache operations; and reallocating cache memory based on the target cache allocation.

Abstract: A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively.

Abstract: An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also includes translation latency measuring circuitry to measure a latency of at least part of an address translation process performed by the address translation circuitry in response to a given instruction.

Abstract: A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main memory corresponding to the working footprint of main memory to the region migration cache. A method includes profiling a stream of memory accesses to generate an access frequency ranked list of address ranges of main memory and corresponding access frequencies based on memory addresses in the stream of memory accesses. The method includes periodically migrating to a region migration cache contents of a region of main memory selected based on the access frequency ranked list. The method includes storing a memory address range corresponding to the contents of the region migration cache in a tag map.

Abstract: In one general embodiment, a computer-implemented method includes identifying a record having a lock being held being held by a first process, where the process is running within a first system of a plurality of systems, sending an identification of the lock for the record to a second system of the plurality of systems, receiving, at the first system, from the second system, information associated with a first request for the lock of the record, determining at the first system a second request for the lock of the record held by the first process, and conditionally releasing the lock being held by the first process, based on an analysis of the information associated with the first request and information associated with the second request.

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

Abstract: A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

Abstract: Priority-based data communication over multiple communication buses is disclosed. In this regard, an electronic device is communicatively coupled to a first communication bus and a second communication bus. The electronic device is configured to detect communication signals communicated over the first communication bus and the second communication bus. If the communication signals are detected on both the first communication bus and the second communication bus, the electronic device is further configured to protect data received over the second communication bus from being overwritten by data received over the first communication bus. By configuring the electronic device to support multiple communication buses, it is possible to configure one of the multiple communication buses as a priority communication bus, thus allowing time-critical communications to be carried out over the priority communication bus in a timely manner without preempting ongoing communications on other communication buses.

Abstract: The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. During operation, an interrupt controller in the computing device receives an indication of an interrupt. The interrupt controller then determines a processor type for processing the interrupt. Next, the interrupt controller causes the interrupt to be processed by one of the plurality of processors that is the determined processor type.

Abstract: An apparatus and method are provided for interrupt handling. A method includes receiving, by an accelerator unit, an interrupt request; stacking, by the accelerator unit, a plurality of general purpose registers in an inbuilt last in first out (LIFO) unit; and sending, by the accelerator unit, a vector address corresponding to the interrupt request to a processor, which processes the interrupt request.

Abstract: A semiconductor device is provided, which can supply efficiently plural pieces of data required for operation to an arithmetic unit processing plural pieces of data concurrently. The microcomputer includes a data transfer controller and a filter arithmetic unit. The data transfer controller transfers plural pieces of data from a source address area to a destination address area continuously, based on data transfer information, when a start request is received. The filter arithmetic unit performs operation using concurrently plural pieces of data received from the data transfer controller.

Abstract: The invention provides a data accessing system and a method for the same. The data accessing system comprises a data access unit and a data storage unit. When the data access unit is configured to access a plurality of data with continuous or discrete addresses, it issues a plurality of request instructions. The request instructions are encapsulated into a special instruction by an encapsulation module, and transmitted to the data storage unit by a data transmission interface. The data storage unit obtains the plurality of request instructions by using a de-encapsulation module to de-encapsulate the special request instruction, and executes the plurality of request instructions to access the plurality of data, so as to enhance the efficiency of data access.

Abstract: Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing non-standard bus information.

Abstract: Example implementations relate to a server including a platform controller hub (PCH), where the PCH includes a peripheral device manager, a management processor coupled to the peripheral device manager, and a peripheral device interface to couple with a peripheral device and provide out of band access of the peripheral device via the management processor and peripheral device manager to a memory of the server.

Abstract: An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.

Abstract: A system for switching between a high performance mode and dual path mode is disclosed. The system includes a first device, a second device, a third device, and a switch configured to receive control signals, and in response causing the switch to selectively couple one or more first lanes of the first device or one or more second lanes of the second device to third lanes of the third device to yield enabled lanes. The system also include a number of the enabled lanes is less than or equal to a number of the third lanes, and the switch is configured to route the enabled lanes associated with the first device to a first portion of the third lanes in an increasing order and to route the enabled lanes associated with the second device to a second portion of the third lanes in a decreasing order.

Abstract: A mass storage device selector (1000) operatively couplable between a host computer (12) and a plurality of mass storage devices (14), for allowing a user of the host computer (12) to securely and exclusively select, access and interface with only one of the mass storage devices (14) operatively coupled thereto.

Abstract: A tunable bus-mediated coupling system is provided that includes a first input port coupled to a first end of a variable inductance coupling element through a first resonator and a second input port coupled to a second end of the variable inductance coupling element through a second resonator. The first input port is configured to be coupled to a first qubit, and the second output port is configured to be coupled to a second qubit. A controller is configured to control the inductance of the variable inductance coupling element between a low inductance state to provide strong coupling between the first qubit and the second qubit and a high inductance state to provide isolation between the first qubit and the second qubit.

Abstract: A clock tree implementation method, system-on-chip and computer storage medium, being applied to the system-on-chip comprising a core module (10) and an externally connected module (20); an interconnection matrix (12) in the core module (10) is connected to the externally connected module (20) by a bus converting bridge (11) comprising a protocol bridge (111) and a frequency dropping bridge (112); converting a data bus into a first configuration bus (S100) through the protocol bridge (111), the frequency of the first configuration being the frequency of the protocol bridge; converting the first configuration bus into a second configuration bus (S101) through the frequency dropping bridge (112), the frequency of the second configuration bus being the frequency of the configuration bus of the externally connected module.

Abstract: Provided is a terminal for controlling an external device, not equipped with its own memory or controller, connected to the terminal. The portable terminal, when being connected to at least one external device, changes its setting with an extracted setting data matching the connected external device. Accordingly, the connected external device in a connection state to the portable terminal performs corresponding operations under control of the portable terminal.

Abstract: A multisite sensing system including two or more analyte sensors, an interface device, and a shared bus. The interface device may be configured to receive a power signal and generate power for powering the analyte sensors and to convey data signals generated by the analyte sensors. The shared bus connected to the interface device and each of the analyte sensors and configured to provide the power generated by the interface device to the analyte sensors and to provide the data signals generated by the analyte sensors to the interface device. The interface device may be an inductive element. The shared bus may be a two wire, multiplexed bus. The analyte sensors may be spatially separated for analyte sensing at least two different locations. The analyte sensors may generate data signals indicative of the presence and/or amount of the same analyte or of one or more different analytes.

Abstract: A virtual switch executes on a computer system to forward packets to one or more destinations. A method of the disclosure includes receiving, by a virtual switch application being executed by a processing device, a packet comprising a header, determining, that the packet does not match a distribution table associated with the virtual switch and storing, by the processing device, the packet to a shared memory buffer that is accessible to a network controller application being executed by the processing device.

Abstract: Certain aspects of the present disclosure relate to methods and apparatus for improving buffer size setting for one or more buffer status reports, such as one or more extended buffer status reports (eBSRs) in a wireless communication system. According to certain aspects, a method is provided herein for wireless communications performed by a user equipment (UE). The method generally includes determining a first amount of data stored in a buffer at the UE; and if the first amount of the data satisfies (e.g., is equal to or greater than) a threshold, sending a first BSR indicating a second amount of buffered data at the UE greater than the first amount. As a result, the UE may be scheduled by the base station for a greater amount uplink resources for transmitting the buffered data.

Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.

Abstract: A classical way of finding the harmonic map is to minimize the harmonic energy by the time evolution of the solution of a nonlinear heat diffusion equation. To arrive at the desired harmonic map, which is a steady state of this equation, an efficient quasi-implicit Euler method (QIEM) is revealed and its convergence under some simplifications is analyzed. It is difficult to find the stability region of the time steps if the initial map is not close to the steady state solution. A two-phase approach for the quasi-implicit Euler method (QIEM) is disclosed to overcome this drawback. In order to accelerate the convergence, a variant time step scheme and a heuristic method used to determine an initial time step have been developed. Numerical results clearly demonstrate that the present method far computing the spherical conformal and Riemnann mappings achieves high performance.

Abstract: A method for computing conformal parameterizations is revealed. First discrete conformal maps are reviewed for computing a generalized eigenvalue problem (GEP) arising from spectral conformal parameterization. Then nonequivalence deflation and null-space free compression techniques are applied to transform the GEP to a small-scaled compressed and deflated standard eigenvalue problem (CDSEP). Lastly a skew-Hamiltonian isotropic Lanczos algorithm (SHILA) is used to solve the CDSEP. Numerical experiments and comparisons are presented to show that the present method compute the conformal parameterization accurately and efficiently.

Abstract: Disclosed is a document viewing system including: a document dividing unit configured to analyze a format of a document to be displayed in a reflow display, divide the document into predetermined elements, and prepare a second document by adding identifiers to the elements; and a plurality of display terminals configured to display the second document in the reflow display, wherein the first display terminal creates specific information for specifying a part of the second document, which is currently displayed on the first display terminal, in accordance with the identifiers added in the second document, and outputs the specific information to an external device, and the second display terminal receives the specific information, specifies the part which is currently displayed on the first display terminal in accordance with the specific information, and displays the second document so as to make a viewer recognize the specified part.

Abstract: Roughly described, a viewer application is provided for viewing a PDF document on a screen of a device such as a mobile phone or tablet. The viewer application may operate in page mode or in text mode. In page mode the original layout is maintained, and navigation assistance is provided by use of a navigation pane indicating the contents of the screen with a superimposed frame. Display of the navigation pane is controllable by the user. In page mode a selected text column is scrolled and zoomed to optimize reading. In text mode, text is extracted from the document and reformatted in text view to be continuous and complete in correct reading order, and images and advertising may be excluded. The user may toggle between page mode and text mode. The viewer application is implemented in software to by executed by a processor on the device.

Abstract: A mobile multimedia content aggregation and dissemination platform is provided that aims to automate the creation, collection, aggregation, and dissemination of RSS and non-RSS information for and to interested parties. This platform may be used for the construction of a personalized blogging agent as well as for a personalized news aggregator.

Abstract: A server prevents duplicate posts within a question and answer forum. The server may compare the user question vector to each of the plurality of corpus question vectors to determine the closest match between the user question vector and the corpus question vectors to obtain an identified question and answer row, and determine if the identified Q and A row has a last answer that has a corresponding confidence to the question of the identified Q and A row that exceeds a confidence threshold. Responsive to a positive determination, the server may determine if the user question is similar to a question in the identified Q and A row, and if so the server may determine that the last answer is similar to any answer in the identified Q and A row that is not the last answer, and in response, block the submission of the user question.

Abstract: A message processing device (10) includes an estimator (11), an extractor (12), and an indicator (13). The estimator (11) estimates words understandable to a destination user (1). The extractor (12) extracts, from a message (3) created by a transmission originator user (2), a portion that does not match the words estimated by the estimator (11). The indicator (13) indicates, to the transmission originator user (2), the message (3) with the extracted portion by the extractor (12) being in an emphasized manner.

Abstract: Systems and methods are provided to determine that an input to the web browser that displays a web page on a mobile computing device is received, and compare a determined property of the received input with at least one reference value that corresponds to the property. An intent to exit the displayed webpage is detected when the determined property of the received input is the same as or exceeds the at least one reference value. A message is displayed on the display of the mobile computing device based on the determination of intent to exit the displayed web page.

Abstract: A filter system for filtering out content of documents is provided. A filter client receives from a user a selection of content of a first document that the user wants to be obscured when the documents are displayed. The filter client sends to a filter server filter information that includes content information derived from the selected content. The filter client then receives from the filter server a filter generated from filter information sent from the client system and from other client systems of other users. The filter client then obscures content of a second document that matches the filter and then displays the second document.

Abstract: A method includes displaying, on a display interface of a terminal, duration of a to-be-edited audio file; and displaying, on the display interface of the terminal, lyrics that are of the to-be-edited audio file and that correspond to a preset editing duration. The method further includes adjusting the editing duration according to at least one of a start moment or an end moment entered by a user; and displaying, on the display interface of the terminal, lyrics corresponding to the adjusted editing duration, for the user to determine audio file content corresponding to the editing duration. The method additionally includes acquiring an audio file corresponding to editing duration that is between the start moment and the end moment, in response to the user determining a start moment and an end moment for final editing.

Abstract: An out-space actuator is selected to access an out-space user interface for a document editor program. An out-space actuator is associated with an in-space user interface having a displayed document. When the out-space actuator is selected, an out-space user interface is displayed that includes an expanded feature selection surface. The out-space user interface may be used to display one or more status panes for providing status information about a document being edited in the in-space user interface. Application features for affecting changes to a given document's status may be exposed in the out-space interface in proximity to associated status information. An out-space communication user interface (UI) component may be temporarily displayed in the document in-space user interface to communicate document status information that is presently available in the out-space user interface. A message bar may be displayed in the in-space user interface for communicating information from the out-space user interface.

Abstract: A user may make a digital item available to other users of a computer network, such as an instant messaging system, a chat environment, or a subscription-based computer network. Examples of digital items that may be shared with other users include digital representations of graphic images, photographs, audio segments, songs, video segments, movies, and text (such as lists of favorites (e.g., a list of favorite books, a list of favorite movies, and a list of favorite places to visit)). On-line presence information is provided to indicate the on-line presence of users with whom a digital item has been shared, may be shared or is being shared. For instance, an indication of the on-line or offline status of a user with whom an item has been shared or is being shared may be presented.

Abstract: One embodiment provides a method, including: accepting, at an input surface, ink input; determining, using a processor, typeset for the ink input; providing, on a display, a combined display of the ink input and the typeset; where the combined display visually associates the ink input and the typeset. Other aspects are described and claimed.