Patents Issued in August 3, 2017
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Publication number: 20170220427Abstract: A data recovery method includes receiving a first physical address of a data block included in a to-be-recovered file sent by a server, searching in a recovery snapshot according to the first physical address of the data block included in the to-be-recovered file, obtaining a second physical address, in a resource volume, of a modified data block in the to-be-recovered file according to a correspondence between a first physical address of the modified data block and the second physical address, in the resource volume, of the modified data block recorded in the recovery snapshot, where the recovery snapshot is a snapshot volume used to recover the to-be-recovered file, and recovering, in the source volume, the to-be-recovered file according to the second physical address, in the resource volume, of the modified data block in the to-be-recovered file.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Gaoding Fu, Yong Jiang, Zian Mu
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Publication number: 20170220428Abstract: Embodiment provide that each pluggable database (PDB) in a container database is associated with a distinct distributed lock manager (DLM) domain. Thus, in order to access a PDB, a database server instance joins the DLM domain for the PDB. To perform actions on the PDB, the instance secures locks that belong to the DLM domain for the particular PDB. As such, buffers storing data for the PDB may be managed separately from buffers storing data for other PDBs using the PDB-specific DLM domains. An instance forcefully closing a particular PDB marks the DLM domain of the PDB as invalid, which allows detection of the forceful closure by a recovery instance. Detection of an invalid DLM domain by an instance causes the instance to automatically recover the PDB by accessing pertinent ranges of redo logs and replaying changes made to data blocks for the PDB indicated in the logs.Type: ApplicationFiled: February 3, 2016Publication date: August 3, 2017Inventors: Yunrui Li, Chi Cao Minh, Wilson Chan, Tolga Yurek, Ping-Hsiu Hsieh
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Publication number: 20170220429Abstract: Embodiments of a multiple sign controller are generally described herein. Many embodiments include a multiple sign controller system. In some embodiments, the multiple sign controller can comprise a computer, a single instance of an operating system configured to run on the computer, two or more virtual sign controller instances, one or more physical communication ports coupled to the computer, and two or more virtual ports configured to run on the single instance of the operating system. In many embodiments, a first virtual port of the two or more virtual ports can be associated with a first virtual sign controller instance of the two or more virtual sign controller instances. Other embodiments may be described and claimed.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Applicant: Skyline Products, Inc.Inventor: Robert Charles Stadjuhar, JR.
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Publication number: 20170220430Abstract: As disclosed herein a computer-implemented method for managing an HA cluster includes activating, by a cluster manager, a monitoring process that monitors a database on a first node in a high-availability database cluster. The method further includes receiving an indication that the database on the first node is not healthy, initiating a failover operation for deactivating the database on the first node and activating a standby database on a second node in the high-availability database cluster providing an activated standby database, and ensuring that any additional databases on the first node are unaffected by the failover operation. A computer program product corresponding to the above method is also disclosed.Type: ApplicationFiled: January 18, 2017Publication date: August 3, 2017Inventors: Juilee A. Joshi, Gaurav Mehrotra, Nishant Sinha, Jing Jing Xiao
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Publication number: 20170220431Abstract: As disclosed herein a computer-implemented method for managing an HA cluster includes activating, by a cluster manager, a monitoring process that monitors a database on a first node in a high-availability database cluster. The method further includes receiving an indication that the database on the first node is not healthy, initiating a failover operation for deactivating the database on the first node and activating a standby database on a second node in the high-availability database cluster providing an activated standby database, and ensuring that any additional databases on the first node are unaffected by the failover operation. A computer program product corresponding to the above method is also disclosed.Type: ApplicationFiled: February 1, 2016Publication date: August 3, 2017Inventors: Juilee A. Joshi, Gaurav Mehrotra, Nishant Sinha, Jing Jing Xiao
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Publication number: 20170220432Abstract: A first compute node of a plurality of compute nodes of a database cluster may receive a request for a database transaction from a client application. The client application may be located within the first compute node. A first connection may be established, without regard to whether another compute node has a lighter workload than the first compute node, between the client application and a first database of the database cluster. The first connection may be a local connection, wherein the first database is located within the first compute node. The first compute node may detect that a failure associated with the first database has occurred. The first compute node may execute a failover operation to continue servicing the request for the data. The executing of a failover operation may include establishing a second connection between the client application and a second database of the database cluster.Type: ApplicationFiled: February 3, 2016Publication date: August 3, 2017Inventors: Kollol K. Misra, Pallavi Priyadarshini, Parameswara R. Tatini, Maryela E. Weihrauch
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Publication number: 20170220433Abstract: Various embodiments are generally directed to techniques for determining whether one node of a HA group is able to take over for another. An apparatus includes a model derivation component to derive a model correlating node usage level to node data propagation latency through and to node resource utilization from a first model of a first node of a storage cluster system and a second model of a second node of the storage cluster system, the first model based on a first usage level of the first node under a first usage type, and the second model based on a second usage level of the second node under a second usage type; and an analysis component to determine whether the first node is able to take over for the second node based on applying to the derived model a total usage level derived from the first and second usage levels.Type: ApplicationFiled: April 28, 2016Publication date: August 3, 2017Inventors: Alma Dimnaku, Curtis Hrischuk, Kevin Faulkner
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Publication number: 20170220434Abstract: A first compute node of a plurality of compute nodes of a database cluster may receive a request for a database transaction from a client application. The client application may be located within the first compute node. A first connection may be established, without regard to whether another compute node has a lighter workload than the first compute node, between the client application and a first database of the database cluster. The first connection may be a local connection, wherein the first database is located within the first compute node. The first compute node may detect that a failure associated with the first database has occurred. The first compute node may execute a failover operation to continue servicing the request for the data. The executing of a failover operation may include establishing a second connection between the client application and a second database of the database cluster.Type: ApplicationFiled: January 17, 2017Publication date: August 3, 2017Inventors: Kollol K. Misra, Pallavi Priyadarshini, Parameswara R. Tatini, Maryela E. Weihrauch
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Publication number: 20170220435Abstract: A first compute node of a plurality of compute nodes of a database cluster may receive a request for a database transaction from a client application. The client application may be located within the first compute node. A first connection may be established, without regard to whether another compute node has a lighter workload than the first compute node, between the client application and a first database of the database cluster. The first connection may be a local connection, wherein the first database is located within the first compute node. The first compute node may detect that a failure associated with the first database has occurred. The first compute node may execute a failover operation to continue servicing the request for the data. The executing of a failover operation may include establishing a second connection between the client application and a second database of the database cluster.Type: ApplicationFiled: January 17, 2017Publication date: August 3, 2017Inventors: Kollol K. Misra, Pallavi Priyadarshini, Parameswara R. Tatini, Maryela E. Weihrauch
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Publication number: 20170220436Abstract: Methods and apparatus for a primary role reporting service for resource groups are disclosed. A reporting intermediary assigned to a resource group of a network-accessible service receives role information indicating the identity of a primary member of the group from a state manager of the network-accessible service. The intermediary receives a health status query pertaining to the resource group from a health checking subsystem used by a network address discovery service, and provides a health status response based on the role information. The response provided by the reporting intermediary is used by the network address discovery service to provide a network address in response to a lookup query for the resource group.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Applicant: Amazon Technologies, Inc.Inventors: Nicholas Ryman Vogel, Colm McCarthaigh, Grant Alexander MacDonald McAlister, Laurion Darrell Burchall, Jorgen Lawrence Johnson
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Publication number: 20170220437Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Christian Habermann, Gerrit Koch, Martin Recktenwald, Ralf Winkelmann
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Publication number: 20170220438Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.Type: ApplicationFiled: March 9, 2016Publication date: August 3, 2017Inventors: Manoj Dusanapudi, Shakti Kapoor
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Publication number: 20170220439Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.Type: ApplicationFiled: June 29, 2016Publication date: August 3, 2017Inventors: Christian Habermann, Gerrit Koch, Martin Recktenwald, Ralf Winkelmann
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Publication number: 20170220440Abstract: Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.Type: ApplicationFiled: February 9, 2017Publication date: August 3, 2017Inventors: Manoj DUSANAPUDI, Shakti KAPOOR
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Publication number: 20170220441Abstract: A storage aware memory controller for managing a physical storage system. A described controller: a system for mapping physical memory space into a memory region and a storage region; a system for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and a storage file system that includes a mapping table for mapping logical addresses to physical addresses for data stored in the storage region.Type: ApplicationFiled: January 27, 2017Publication date: August 3, 2017Inventors: Tong Zhang, Hao Zhong, Fei Sun, Yang Liu
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Publication number: 20170220442Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.Type: ApplicationFiled: August 23, 2016Publication date: August 3, 2017Inventors: Manoj Dusanapudi, Shakti Kapoor
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Publication number: 20170220443Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.Type: ApplicationFiled: August 31, 2016Publication date: August 3, 2017Inventors: Mickael Broutin, Benoit Lelievre, Nicolas Anquet
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Publication number: 20170220444Abstract: Systems and methods for providing a visual indication of cable connection status. A method may include determining whether an Information Handling System (IHS) has established data communications using one of a plurality of different types of protocols supported by a cable and providing, on the cable, a visual indication of the type of protocol being used and/or an amount of power delivered via the cable. A cable may include a plurality of conductors, a controller coupled to the plurality of conductors, and a plurality of LEDs coupled to the controller. The controller may: determine whether an IHS coupled to the cable has established data communication with another device via the cable using one of a plurality of different types of protocols supported by the cable; and provide a visual indication of the type of protocol being used in the data communication and/or power delivered via the cable.Type: ApplicationFiled: February 28, 2017Publication date: August 3, 2017Applicant: Dell Products, L.P.Inventors: Adolfo S. Montero, Marcin M. Nowak
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Publication number: 20170220445Abstract: Various embodiments of methods and systems for intelligent thermal power management implemented in a portable computing device (“PCD”) are disclosed. To mitigate or alleviate hysteresis associated with drastic changes in processing speeds for thermally aggressive processing components, embodiments of the solution dynamically adjust performance level floors in view of a temperature reading. Advantageously, embodiments work to manage thermal energy generation based on temperature sensor feedback that is relatively slow to detect temperature changes.Type: ApplicationFiled: May 16, 2016Publication date: August 3, 2017Inventors: Adam CUNNINGHAM, Kwangyoon LEE, Melanie OCLIMA
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Publication number: 20170220446Abstract: Computing threads can be sampled such that the samples hit each activity with a probability proportional to a time period of that activity. Therefore, the sampling can advantageously account for all activities, including activities that are smaller than the applicable sampling interval.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Tobias Scheuer, Daniel Booss
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Publication number: 20170220447Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes one or more registers to store software-visible control bits, a first performance counter to increment upon occurrence of a first type of event in the processor from a first starting value to a first limit, and a second performance counter to increment upon occurrence of a second type of event in the processor from a second starting value to a second limit. The processor also includes control logic to receive an indication of the first performance counter reaching the first limit, access a reload enable bit, and send a control signal in view of the reload enable bit. The processor also includes reload logic to reset the second performance counter to a second reload value in response to receiving the control signal from the control logic.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventor: Jason W. Brandt
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Publication number: 20170220448Abstract: Techniques are provided for mocking downstream services while regression testing a service. In one technique a version of a service processes a request, during which one or more computers intercept downstream service calls made by the version of the service. For each downstream service call of the downstream calls, a computer provides, to the version of the service, a response of the downstream service call, which was previously recorded while processing the request in a production environment. Processing, by the version of the service, the request involves processing the request based on the response of at least one of the downstream service calls.Type: ApplicationFiled: February 1, 2016Publication date: August 3, 2017Inventors: SAJID TOPIWALA, ANANT RAO, PRITESH SHAH, WALTER SCOTT JOHNSON, ARUNPRASAD VENKATRAMAN
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Publication number: 20170220449Abstract: In one implementation, a system can comprise a probe monitor engine to monitor a probe passed to a function of a set of instructions, a propagation engine to identify an infrastructure connection based on an attribute of the probe during a runtime session, and a rule engine to generate an infrastructure rule based on the infrastructure connection and the attribute of the probe.Type: ApplicationFiled: September 24, 2014Publication date: August 3, 2017Inventors: Alvaro MUNOZ SANCHEZ, Yekaterina O'NEIL
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Publication number: 20170220450Abstract: An analysis program recorded in a recording medium causes a computer to hold, when executing an intermediate code that is a compiled code in which an element in a source code is replaced with a metafunction that changes the element to a mutant, a set of mutation descriptors indicating a change in the mutant with respect to a mutation operation corresponding to the metafunction. The analysis program further causes the computer to evaluate a command of each of the mutation descriptors, select at least one mutation descriptor having a same command evaluation result from the set of the mutation descriptors, and calculate a direct product of the selected mutation descriptor and one of the mutation operation and a first state that is the set of the mutation descriptors before evaluation of the commands, thereby generating a second state.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Applicant: FUJITSU LIMITEDInventors: Susumu TOKUMOTO, Hiroaki Yoshida
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Publication number: 20170220451Abstract: A multi-device data processing machine system includes a plurality of network-connected cliental servers including first and second production servers coupled to a dynamic load balancer. The machine system also includes an SaaS development server that is configured to pass under-development process requests to the load balancer in combination with a mix command such that the load balancer routes a mix of routine production traffic and the under-development process requests to at least one of the production servers that is instrumented for enabling remote debugging of code executing therein so that the under-development process requests can be debugged under the full or partial stresses of a live production environment.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Applicant: CA, INC.Inventor: Serguei Mankovskii
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Publication number: 20170220452Abstract: Performing a mirror test for localization testing includes executing a mirror test, the mirror test includes an execution of actions on target controls on a master device and mimicking the actions on the target controls on a number of slave devices for localization testing, identifying the target controls on the number of slave devices to mimic the execution of the actions on the target controls of the master device, capturing at least one screenshot of the mirror test, and displaying the at least one screenshot to a user.Type: ApplicationFiled: April 30, 2014Publication date: August 3, 2017Inventors: Yi-Qun Ren, Hai-Ying Liu, Zhi-Yuan Jing
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Publication number: 20170220453Abstract: A high level interface between a remote computer and local computer operator permits the remote computer to be controlled via a sequence of interactions. The remote computer may be monitored for display information which is expected, and also controlled in the event the expected information either is or is not obtained. Command language extensions are provided which extend and complement a basic scripting language. Scripts with embedded command language extensions may be executed through a remote interface, permitting remote testing, operation and evaluation. The development of the scripts, including embedded command language extensions, may be prepared through execution of commands at the local computer on a depiction of the GUI received from the remote computer, and subsequently saved as a script.Type: ApplicationFiled: April 13, 2017Publication date: August 3, 2017Applicant: TESTPLANT, INC.Inventors: Douglas P. SIMONS, Jonathan D. GILLASPIE
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Publication number: 20170220454Abstract: A test device includes a memory and a processor coupled to the memory. The processor is configured to execute a test on a first virtual machine among a plurality of virtual machines included in a network in operation. The processor is configured to generate a first snapshot of the first virtual machine before the test is executed. The processor is configured to generate a first substitute machine from the first snapshot. The first substitute machine is a substitute for the first virtual machine. The processor is configured to determine whether the test results in success. The processor is configured to replace the first virtual machine with the first substitute machine depending on a result of the determination.Type: ApplicationFiled: December 28, 2016Publication date: August 3, 2017Applicant: FUJITSU LIMITEDInventor: Shinya KANO
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Publication number: 20170220455Abstract: The application discloses a computing system to analyze a program to generate a control flow graph representing paths capable of being traversed through the program during execution. The computing system can translate the control flow graph into a constraint graph representation of the program. The computing system can utilize a constraint solver on the constraint graph to identify a set of test values associated with a coverage definition. The set of test values can prompt the program, during execution, to be exercised based on the coverage definition provided to the test program generation tool 300. The computing system can generate a test program configured to provide the set of input variable values to the program.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Ahmed Badran, Sudhir Kadkade
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Publication number: 20170220456Abstract: A method for automated test case augmentation includes receiving, at an automated test augmentation system, a design model and model coverage gap information from a model-based development tool, translating the model coverage gap information into machine-readable mathematical test objective expressions, developing a set of test objective operators by translating the machine-readable mathematical test objective expressions, localizing target operators for the identified coverage gaps within the design model, attaching the test objective operators to target operators of the design model to create a test model, augmenting the test model by propagating test objectives at the target operators to a test node operator of the design model, and executing, by a test generator, the augmented test model to obtain the test cases to cover the coverage gaps and the causes for the model coverage gaps. A system for implementing the model-based design and a non-transitory computer readable medium are also disclosed.Type: ApplicationFiled: February 2, 2016Publication date: August 3, 2017Inventors: Meng LI, Michael Richard DURLING, Jian DAI, Scott Alan STACEY
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Publication number: 20170220457Abstract: A test-centric model of an application is constructed. Each resource specified by each test governing an application is added to the test-centric model. The test or tests specifying an resource are linked to the resource within the test-centric model. A composition of the application is defined using the one or more tests, as the resources specified by the one or more tests, within the test-centric model of the application.Type: ApplicationFiled: April 12, 2017Publication date: August 3, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Oren GURFINKEL, Oleg VERHOVSKY, Eliraz BUSI, Maya Yohay RAFALOVICH, Malcolm ISAACS
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Publication number: 20170220458Abstract: A device may receive information associated with an application to be tested. The device may identify test data associated with the application to be tested based on the received information. The device may associate the test data with a plurality of test cases. The device may associate the plurality of test cases with a test set. The device may associate the test set with a release. The device may provide the plurality of test cases and the test data, associated with the release, to the application to be tested. The device may receive a plurality of first results, and may compare the plurality of first results and a plurality of second results. The device may provide information for display based on comparing the plurality of first results and the plurality of second results.Type: ApplicationFiled: July 18, 2016Publication date: August 3, 2017Inventors: Melissa FINGER, Chinwendu A. OSUOHA, James IRLBECK, Daniel P. SCHMIDT, Rhegina S. GATUZ, Gerald L. HAWKINS, Dattatray JOSHI, Jonathan Herrera FRANCISCO
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Publication number: 20170220459Abstract: A system for centralized testing of web-based agent desktops has been devised. The invention uses a test control portal. The test control portal acts as the interface between the client interaction software systems testing system and analyst controlled test device, executes an extensive set of robust test directive commands with underlying routines to be used to specify test conditions without the use of programming ability on the part of the analyst, uses a robust set of report item and format choice designators to allow easy selection of a range of report content and styles.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Alok Kulkarni, Geoff Willshire
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Publication number: 20170220460Abstract: The present disclosure involves systems, software, and computer implemented methods for testing applications on multiple system landscapes. In one example, a method may include identifying instructions to test a plurality of system landscapes, executing a test of a first system landscape from the plurality of system landscapes, validating a response received from the first system landscape by a user associated with the testing, executing tests of at least a subset of the remaining plurality of system landscapes which includes sending requests including the predefined input to the entry point of each of the subset of the remaining plurality of system landscapes, receiving responses from the subset of the remaining plurality of system landscapes, and comparing each received response to the validated response from the first system landscape, and in response to the comparison, generating a result set of the comparison of each received response to the validated response.Type: ApplicationFiled: April 11, 2017Publication date: August 3, 2017Inventor: Vitaly Vainer
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Publication number: 20170220461Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Vijay KARAMCHETI, Kumar GANAPATHY, Kenneth Alan OKIN, Rajesh PAREKH
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Publication number: 20170220462Abstract: A data storage method and a system thereof are disclosed. The data storage method includes allocating a first logical block and a second logical block, which are mapped to a physical block; the first logical block includes consecutive first logical pages, used to store logical addresses, and the second logical block includes consecutive second logical pages; on executing garbage collection, sequentially and consecutively storing valid logical addresses in second logical pages in the order of the second logical pages according to valid bits; and establishing a one-to-one second mapping relationship between the second logical pages and valid data pages according to the first mapping relationship.Type: ApplicationFiled: February 25, 2016Publication date: August 3, 2017Inventors: SHIH-CHIANG TSAO, TING-FANG CHIEN, AN-NAN CHANG
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Publication number: 20170220463Abstract: A Data Storage Device (DSD) includes a Non-Volatile Memory (NVM) for storing data, a network interface for communicating on a network, and a processor. According to one aspect, a command is received via the network interface for storing data in the NVM. A data writing methodology is dynamically selected for how the data will be physically stored in the NVM from among a plurality of data writing methodologies based at least in part on whether the command is to be performed using a first interface or a second interface for accessing data in the NVM. According to another aspect, respective storage capacities of the NVM and/or respective rates of consumption of different types of storage media in the NVM are assigned to the first interface and to the second interface.Type: ApplicationFiled: April 11, 2017Publication date: August 3, 2017Inventors: James N. MALINA, Allen SAMUELS
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Publication number: 20170220464Abstract: Efficiently managing encrypted data on a remote backup server, including: receiving an encrypted extent of data; storing the encrypted extent; determining, without decrypting the encrypted extent, whether the encrypted extent is no longer valid; and responsive to determining that the encrypted extent is no longer valid, garbage collecting the encrypted extent.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Inventors: JOHN GALLAGHER, ETHAN MILLER, RYAN WALEK
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Publication number: 20170220465Abstract: A memory system supporting an interleaving operation including: a plurality of memory devices; and a controller suitable for detecting whether, among a plurality of logical address groups inputted to perform a read or write operation in the plurality of memory devices, first logical address groups having values related to each other are inputted, and for adjusting, when physical storage locations of data corresponding to logical addresses of the first logical address groups are inaccessible using interleaving, the physical storage locations of the data to locations that are accessible using interleaving and store the data in adjusted locations.Type: ApplicationFiled: July 7, 2016Publication date: August 3, 2017Inventor: Hae-Gi CHOI
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Publication number: 20170220466Abstract: Embodiments of an invention for sharing a guest physical address space between virtualized contexts are disclosed. In an embodiment, a processor includes a cache memory and a memory management unit. The cache memory includes a plurality of entry locations, each entry location having a guest physical address field and a host physical address field. The memory management unit includes page-walk hardware and cache memory access hardware. The page-walk hardware is to translate a guest physical address to a host physical address using a plurality of page table entries. The cache memory access hardware is to store the guest physical address and the host physical address in the cache memory only if a shareability indicator in at least one of the page table entries is set.Type: ApplicationFiled: January 30, 2016Publication date: August 3, 2017Inventors: Deepak K. Gupta, Baiju V. Patel, Andrew V. Anderson, Gilbert Neiger, Ravi L. Sahita
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Publication number: 20170220467Abstract: A cache system stores a number of different datasets. The cache system includes a number of cache units, each in a state associated with one of the datasets. In response to determining that a hit ratio of a cache unit drops below a threshold, the state of the cache unit is changed and the dataset is replaced with that associated with the new state.Type: ApplicationFiled: April 20, 2017Publication date: August 3, 2017Inventors: Filip Eliás, Filip Nguyen
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Publication number: 20170220468Abstract: Embodiments relate to cache coherency verification using ordered lists. An aspect includes maintaining a plurality of ordered lists, each ordered list corresponding to a respective thread that is executed by a processor, wherein each ordered list comprises a plurality of atoms, each atom corresponding to a respective operation performed in a cache by the respective thread that corresponds to the ordered list in which the atom is located, wherein the plurality of atoms in an ordered list are ordered based on program order. Another aspect includes determining a state of an atom in an ordered list of the plurality of ordered lists. Another aspect includes comparing the state of the atom in an ordered list to a state of an operation corresponding to the atom in the cache. Yet another aspect includes, based on the comparing, determining that there is a coherency violation in the cache.Type: ApplicationFiled: April 12, 2017Publication date: August 3, 2017Inventors: DEAN G. BAIR, JONATHAN T. HSIEH, MATTHEW G. PARDINI, EUGENE S. ROTTER
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Publication number: 20170220469Abstract: In one implementation, relationship based cache resource naming and evaluation includes a generate engine to generate a name for a resource being added to a cache, including a plurality of resources, based on a plurality of parameters of a query including an input resource from which the resource is derived, a workflow of the operations to perform to the input resource to generate the resource, and a context associated with the query. In addition, the system includes an evaluate engine to evaluate, in response to an event, each of the plurality of resources and the named resource related to the event.Type: ApplicationFiled: September 3, 2014Publication date: August 3, 2017Inventors: Eric Deliot, Rycharde J. HAWKES, Luis Miguel VAQUERO GONZALEZ, Lawrence WILCOCK
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Publication number: 20170220470Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.Type: ApplicationFiled: September 27, 2016Publication date: August 3, 2017Inventors: Fadi Y. BUSABA, Harold W. CAIN, III, Michael K. GSCHWIND, Valentina SALAPURA, Eric M. SCHWARZ, Timothy J. SLEGEL
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Publication number: 20170220471Abstract: Methods and systems for improved control of traffic generated by a processor are described. In an embodiment, when a device generates a pre-fetch request for a piece of data or an instruction from a memory hierarchy, the device includes a pre-fetch identifier in the request. This identifier flags the request as a pre-fetch request rather than a non-pre-fetch request, such as a time-critical request. Based on this identifier, the memory hierarchy can then issue an abort response at times of high traffic which suppresses the pre-fetch traffic, as the pre-fetch traffic is not fulfilled by the memory hierarchy. On receipt of an abort response, the device deletes at least a part of any record of the pre-fetch request and if the data/instruction is later required, a new request is issued at a higher priority than the original pre-fetch request.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventor: Jason Meredith
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Publication number: 20170220472Abstract: A memory system may include a plurality of first and second memory devices each comprising M-bit multi-level cells (MLCs), M-bit multi-buffers, and transmission buffers, a cache memory suitable for caching data inputted to or outputted from the plurality of first and second memory devices, and a controller suitable for programming program data cached by the cache memory to a memory device selected among the first and second memory devices by transferring the program data to M-bit multi-buffers of the selected memory device whenever the program data are cached by M bits into the cache memory, and controlling the selected memory device to perform a necessary preparation operation, except for a secondary preparation operation, of a program preparation operation, until an input of the program data is ended or the M-bit multi-buffers of the selected memory device are full.Type: ApplicationFiled: July 7, 2016Publication date: August 3, 2017Inventors: Byoung-Sung YOU, Jin-Woong KIM, Jong-Min LEE
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Publication number: 20170220473Abstract: Zones of a magnetic recording medium are allocated as a respective plurality of distributed media caches arranged in in a predetermined order. For each of a plurality of caching events, cache data is written to one or more of the distributed media caches. A next of the media caches in the predetermined order is selected for the next caching event if the selected caches are not a last in the predetermined order. Otherwise a first media cache is selected in the predetermined order.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Inventors: Jason M. Feist, Mark Allen Gaertner, Dipeshkumar J. Purani, Anil Kashyap, Wei Zhao
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Publication number: 20170220474Abstract: NUMA-aware reader-writer locks may leverage lock cohorting techniques that introduce a synthetic level into the lock hierarchy (e.g., one whose nodes do not correspond to the system topology). The synthetic level may include a global reader lock and a global writer lock. A writer thread may acquire a node-level writer lock, then the global writer lock, and then the top-level lock, after which it may access a critical section protected by the lock. The writer may release the lock (if an upper bound on consecutive writers has been met), or may pass the lock to another writer (on the same node or a different node, according to a fairness policy). A reader may acquire the global reader lock (whether or not node-level reader locks are present), and then the top-level lock. However, readers may only hold these locks long enough to increment reader counts associated with them.Type: ApplicationFiled: February 1, 2016Publication date: August 3, 2017Inventors: David Dice, Virendra J. Marathe
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Publication number: 20170220475Abstract: A computer-implemented method for identification of cache memory transiency may include identifying, with a processor, a virtual memory address section having a virtual memory address, determining, via the processor, a classification of cache memory transiency of the virtual memory address section, and determining, with the processor, based on the classification of cache memory transiency, a cache exemption status.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Jonathan D. Bradbury, Dan F. Greiner, Michael Karl Gschwind, Christian Jacobi, Younes Manton, Anthony Saporito, Chung-Lung Kevin Shum
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Publication number: 20170220476Abstract: A method includes: communicating read requests from a host device to either a storage array controller or a data cache associated with the host device; classifying portions of data, in response to the read requests, according to frequency of access of the respective portions of data; and causing the storage array controller to either promote a first portion of data to a data cache associated with the storage array controller or demote the first portion of data from the data cache associated with the storage array controller in response to a change in cache status of the first portion of data at the data cache associated with the host device and in response to frequency of access of the first portion of data.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Yanling Qi, Junjie Qian, Somasundaram Krishnasamy