Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.

Abstract: An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.

Abstract: A computer -implemented method for managing a cache memory includes fetching, via a processor, a data portion, identifying, via the processor, a transiency classification of a data portion in a memory address range, saving, via the processor, the data portion to a first level (L1) cache memory, evaluating, via the processor, whether the data portion should be copied to at least one other cache memory of a plurality of cache memories based on the transiency classification of the data portion, and selectively saving, via the processor, the data portion to a potential one or more of the plurality of cache memories based on the transiency classification of the data portion.

Abstract: A tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.

Abstract: A system and method for improving storage system operation is disclosed. A storage system includes a first tier with high-performance redundancy and a second tier with capacity efficient redundancy. The first tier and the second tier are built from the same storage devices in a storage pool so each storage device includes both the first and second tiers. The storage system stores write data initially to the first tier. When demand for the data falls below a threshold, the storage system migrates the write data to the second tier. This is done by changing the mapping of underlying physical locations on the storage devices where the write data is stored so that the underlying physical locations are logically associated with the second tier instead of the first tier. After remapping, the storage system also computes parity information for the migrated write data and stores it in the second tier.

Abstract: Systems and methods for managing contiguous addressing via virtual paging registers in a page table used in a high-performance computing platform. One embodiment commences upon initializing a first paging register with a first virtual address of a first virtual address length to form a first virtual address space, then receiving a request from a process to allocate physical memory corresponding to a second virtual address request. A memory allocator allocates the requested physical memory from a physical memory location determined by the memory allocator. An operating system or other sufficiently privileged access identifies a second paging register that is contiguously adjacent to the first paging register. If the second paging register is already in use, then the method identifies an unused (third) paging register into which the contents of the second paging register can be relocated. The method stores the second virtual address into the now freed-up second paging register.

Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.

Abstract: A computer-implemented method for protecting a translation lookaside buffer (TLB) from TLB pollution includes receiving, via a processor, a virtual address for a data portion, determining, via the processor, whether the virtual address has a classification of memory cache transiency, creating, via the processor, a TLB entry in a first TLB, wherein the TLB entry omits a most recently used (MRU) classification, and installing the TLB entry in a next available LRU position.

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

Abstract: A device includes a processor that calculates, based on a position of a first region of a storage and a current position of a head in the storage, a first time for reading the first region associated with a first block that is among blocks, which are associated with regions obtained by dividing the storage region of the storage and to be accessed by the head and temporarily store data stored in the regions, and that is determined as a candidate to be deleted based on a method, calculates, based on a position of a second region and the current position of the head, a second time for reading the second region associated with a second block that is not determined as the candidate to be deleted based on the method, and deletes the second block when the processor determines that the second time is shorter than the first time.

Abstract: A system-on-chip includes a magnetic random access memory and a security interface. The magnetic random access memory includes a plurality of memory areas, each of the plurality of memory areas having a different security level. The security interface circuitry configured to: identify a memory area from among the plurality of memory areas based on a received memory address associated with a received memory command; determine a security level associated with the identified memory area; and perform a memory operation on received data based on the received memory command and the determined security level.

Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.

Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.

Abstract: A tablet information handling system keyboard stand stores pairing information in non-transitory memory accessed by an embedded controller upon detection of a physical connection with a tablet information handling system and communicated to an embedded controller in the tablet information handling system through the physical interface. Embedded controller cooperation coordinates configuration of a wireless personal area network interface without wireless communication or power applied to the wireless networking resources.

Abstract: A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.

Abstract: A storage system includes a controller part, a data storage part, and a transfer path of a signal that couples these parts. A driver included in the controller part transmits the signal including write data on the basis of a configured parameter, a receiver included in the data storage part receives the signal, and the write data included in the signal is written into a first storage area. The controller part reads the write data from the first storage area, determines whether or not a bit error exists in the write data, changes the parameter when the bit error exists to repeat similar determination and find an appropriate parameter at which the bit error no longer exists.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: Aspects disclosed in the detailed description include inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe). In this regard, in one aspect, an ICE is provided in a PCIe root complex (RC) in a host system. The PCIe RC is configured to receive at least one transport layer packet (TLP), which includes a TLP prefix, from a storage device. In a non-limiting example, the TLP prefix includes transaction-specific information that may be used by the ICE to provide data encryption and decryption. By providing the ICE in the PCIe RC and receiving the transaction-specific information in the TLP prefix, it is possible to encrypt and decrypt data in the PCIe RC in compliance with established standards, thus ensuring adequate protection during data exchange between the PCIe RC and the storage device.

Abstract: A semiconductor device includes a first intellectual property block (IP block) which includes a function unit and an interface unit; a first clock control circuit which controls a first clock source; a second clock control circuit which transmits a first clock request to the first clock control circuit, and controls a second clock source which receives a clock signal from the first clock source; and a channel management circuit configured to transmit a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block; wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from a second IP block electrically connected to the first IP block and provides the first signal to the function unit.

Abstract: Aspects of the present disclosure describe automatically changing an output mode of an output device from a first output mode to a latency reduction mode. An initiation signal and the output data may be received from a client device platform or a signal distributor. Upon receiving the initiation signal, the output device may change the output mode from the first output mode to the latency reduction mode. Thereafter, the output device may receive an end latency reduction mode signal. The output device may then revert back to the first output mode. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

Abstract: System and method to transferably store a system state of an electronic component, the system including a processor and a circuit module. The processor is configured to decompose the system state into a plurality of data vectors, and to map each of the plurality of data vectors to a respective bit marker. The circuit module is removably coupled to the electronic component, the circuit module including a memory and a transceiver. The transceiver is coupled to the memory and to a communication link between the memory and the processor, the transceiver operable to send and to receive data at a rate faster than 640 MBps. Data sent and received by the transceiver comprises bit markers mapped by the processor.

Abstract: An embodiment of a massively parallel computing system comprising a plurality of processors, which may be subarranged into clusters of processors, and interconnected by means of a configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The system further comprises diverse high bandwidth external I/O devices and interfaces, which may include without limitation Ethernet interfaces, and dynamic RAM (DRAM) memories. The system is designed for implementation in programmable logic in FPGAs, but may also be implemented in other integrated circuit technologies, such as non-programmable circuitry, and in integrated circuits such as application-specific integrated circuits (ASICs). The system enables the practical implementation of diverse FPGA computing accelerators to speed up computation for example in data centers or telecom networking infrastructure. The system uses the NOC to interconnect processors, clusters, accelerators, and/or external interfaces.

Abstract: A method, a controller, and a system for service flow control in an object-based storage system are disclosed. The method is: receiving, by a controller, a first object IO request; acquiring a processing quantity threshold and a to-be-processed quantity; if the to-be-processed quantity is less than the processing quantity threshold, sending the first object IO request to a storage device client, and updating the to-be-processed quantity; receiving a first response message replied by the storage device client for the first object IO request, where the first response message carries a processing result of the first object IO request; and adjusting the processing quantity threshold according to a received processing result of an object IO request when a preset condition is met. The storage device is not overloaded with object IO requests and can use all resources to effectively, thereby improving performance and a success rate of the object-based storage system.

Abstract: An electronic device coupling system includes a plurality of electronic devices and an external power supply. The plurality of electronic devices includes a master device and a plurality of slave devices coupleable to the master device one by one. Each electronic device has a sequence number according to an insertion sequence, the sequence number is corresponds to all the information of local electronic device, the sequence numbers of the plurality of electronic devices are sorted according to the insertion sequence, the sequence number of the master device is a first number of the sequence, and the master device is coupleable to at least one slave device by the sequence number and all the information corresponding to the sequence number. The at least one slave device is a customized group of the master device.

Abstract: Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.

Abstract: The present disclosure relates to embodiments of bus interface systems capable of dealing with the tougher half clock cycle of SREAD commands in the new mobile industry processor interface (MIPI) radio frequency front end (RFFE) version 2.0 standard. With regard to the slave bus controllers of the bus interface systems disclosed herein, the slave bus controller is configured to operate the slave bus driver such that the data bus line is driven towards a minimum voltage level in response to a final clock edge of the clock signal during the bus park subframe. To ensure compliance with the MIPI RFFE version 2.0 standard, the slave bus controller is configured to detect when the data bus line has been driven within a first voltage range after the final clock edge and continue driving the data bus line 16 even after the bus park half clock period is finished.

Abstract: An Ethernet/Fibre Channel conversion system includes a chassis having a first end and a second end that is located opposite the chassis from the first end. An Ethernet interface is located on the first end and is configured to directly mate with an Ethernet port on an Ethernet device. A Fibre Channel interface is located on the second end. An Ethernet/Fibre Channel conversion engine is housed in the chassis and configured to receive Ethernet protocol signals through the Ethernet interface, convert the Ethernet protocol signals to Fibre Channel protocol signals, and send the Fibre Channel protocol signals through the Fibre Channel interface. The Ethernet/Fibre Channel conversion engine is also configured to receive Fibre channel protocol signals from the Fibre Channel IHS through the Fibre Channel interface, convert the Fibre channel protocol signals to Ethernet protocol signals, and send the Ethernet protocol signals through the Ethernet interface.

Abstract: Enhanced data storage devices in various form factors are discussed herein. In one example, a storage drive includes a plurality of storage devices configured to store and retrieve data responsive to operations received over Peripheral Component Interconnect Express (PCIe) interfaces, a PCIe switch circuit communicatively coupled to the PCIe interfaces of the storage devices and configured to receive over a host connector the operations issued by a host system and transfer the storage operations for ones of the storage devices over associated ones of the PCIe interfaces. The storage drive includes holdup circuitry configured to provide holdup power the storage devices. The storage drive includes a first circuit board assembly comprising three storage device connectors that couple to corresponding storage devices, and a second circuit board assembly comprising a further storage device connector that couples to a further storage device.

Abstract: A modular software-defined storage system and method for providing modular software-defined storage, and components thereof, are disclosed herein. In at least one example embodiment, the storage system includes a backplane, a plurality of storage pods, and a management module storing at least one computer program for causing the storage pods to be configured for operation and for facilitating, when the storage pods are configured for operation, storage of information on the storage pods in accordance with a software-defined storage application. The system also includes first and second interfaces by which an additional computer device can at least indirectly engage in communications with the storage system and by which the storage system can at least indirectly engage in additional communications with an additional system having at least one additional storage pod such that the storage system is expanded to allow for additional storage.

Abstract: Various embodiments herein each include at least one of devices, methods, and software for coupled device deployment location classification in an automated manner. One embodiment, in the form of a method, includes searching a device tree of a computing device to identify any devices of interest. This method, for each identified device of interest, may then identify a path within the computing device of the device of interest and classify, based on the identified path, a relative location of the device of interest. This method may then store the classification of the device of interest in a memory device of the computing device.

Abstract: An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit coupled to the wire tracks.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

Abstract: Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.

Abstract: An apparatus includes multiple computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple coprocessors associated with each computing core, where each coprocessor is configured to receive the input data from at least one of the computing cores, process the input data, and generate output data. The apparatus further includes multiple reducer circuits, where each reducer circuit is configured to receive the output data from each of the coprocessors of an associated computing core, apply one or more functions to the output data, and provide one or more results to the associated computing core. In addition, the apparatus includes multiple communication links communicatively coupling the computing cores and the coprocessors associated with the computing cores.

Abstract: An electronic device coupling system includes a plurality of electronic devices inserted together; a public device coupled to one of the plurality of electronic devices and including a display module, an audio module, and a control module; a master device including the public device and the one of the plurality of electronic device; and at least one slave devices including other electronic devices. The master device further includes a function module and is coupleable to any one of the at least one slave devices. When one of the at least one slave devices is coupled to the master device, the control module controls the one of the at least one slave devices via the function module.

Abstract: An electronic device coupling system includes a plurality of electronic devices inserted together. The plurality of electronic devices includes a master device and a plurality of slave devices inserted with the master device one by one in at least a train. Each electronic device includes a control module, a control bus, and a storage unit. The storage unit stores local matching information. Each slave device includes a coupling key coupled to a local control module. When each slave device is inserted to the master device directly or indirectly, each slave device is matched with the master device by identifying the matching information through the control bus; and each slave device is coupleable to the master device through the control module by pressing the coupling key.

Abstract: An electronic device coupling system includes a plurality of electronic devices. The plurality of electronic devices includes a master device and a plurality of slave devices coupleable to the master device one by one. Each electronic device includes a plurality of bus-bars, each bus-bar has a plurality of types coupling ports, the coupling ports are arranged on at least three different directions. Each coupling port of any bus-bar in any electronic device is capable of inserting into a corresponding coupling port in another electronic device.

Abstract: An electronic device coupling system includes a plurality of electronic devices. The plurality of electronic devices includes a master device and a plurality of slave devices coupleable to the master device one by one. Each electronic device includes a plurality of bus-bars and a plurality of switch modules. Each switch module includes a plurality of switch paths each corresponding to one of the plurality of bus-bars. Two of the electronic devices are inserted together by two of the plurality of bus-bars located in the two of the electronic devices respectively. When the two of the electronic devices are inserted together, the switch paths of each switch module corresponding to the two of the plurality of bus-bars are switched on.

Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

Abstract: Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. Other described devices may be configured as a bus master or as a slave. In one method, a transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a red Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: Systems and methods for operating a processing device are provided. A method may comprise transmitting data on the processing device, monitoring state information for a plurality of buffers on the processing device for the transmitted data, aggregating the monitored state information, starting a timer in response to determining that all buffers of the plurality of buffers are empty and asserting a drain state for the plurality of buffers in response to all buffers of the plurality of buffers remained empty for the duration of the timer.

Abstract: A method and a device for estimating a state of a power system are provided. The method includes: dividing the power system into a plurality of sub-systems; establishing a first linear model of the power system for a first stage; solving the first linear model by an alternating direction multiplier method to obtain the intermediate state variables of each sub-system; performing a nonlinear transformation at a second stage on the intermediate state variables to obtain intermediate measured values; establishing a second linear model of the power system for a third stage according to the intermediate measured values; and solving the third linear model by the alternating direction multiplier method to obtain the final state variables of each sub-system.

Abstract: A method for generating a Fast Fourier Transform (FFT) is disclosed. The method includes providing an input signal to two or more fixed-point FFT algorithms that apply different scaling to reduce growth of their output, resulting in each of the FFT algorithms yielding an array of FFT output values characterized by a different gain. The method further includes determining, on a per-FFT output value basis, whether an output value of an FFT algorithm with a relatively high gain was clipped due to saturation. If not, then the output value of that FFT algorithm is included in the final FFT. Otherwise, an output value of an FFT algorithm with a lower gain is included in the final FFT. Reconstructing the final FFT by such combination of values from different FFTs allows benefiting from the advantages of both higher- and lower-gain FFTs while avoiding or minimizing their disadvantages.

Abstract: Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2?2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected from the R2, R3, and R2?2 stages based on an FFT point size to form an FFT engine. The FFT engine receives input samples at a first stage of the sequence and generate an FFT output result that is output from a last stage of the sequence. The sequence includes no more than one R3 stage.

Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.

Abstract: The present invention generally relates to accessing data selected by a user based on correlation analysis. It is proposed in the present invention to introduce attribute value normalization and a hierarchical data analysis based on mutual correlations between attributes. Normalization of scale values of attributes to nominal values provides a basis for the hypothesis of correlations between attributes, thus scientifically justifying further observation and comparison. Multiple layer hierarchical investigation enables not only analysis on the level of attributes but also of related data, which provides a more detailed observation.

Abstract: In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multiplication engines to perform a multiply operation by receiving a memory element output from a corresponding resistive memory element, receiving an input signal, and generating a multiplication output based on a received memory element output and a received input signal. The array also includes an accumulation engine to sum multiplication outputs from the number of multiplication engines.