Abstract: Systems and methods for failure recovery in shared storage operations. An example method comprises: acquiring a lock with respect to a storage domain comprising a specified disk image; creating a transaction marker associated with the disk image; creating a component of a new volume associated with the disk image; destroying the transaction marker; and releasing the lock with respect to the storage domain.

Abstract: Live partition mobility in a computing environment that includes a source system and a target system may be carried out by: pausing a logical partition on the source system, wherein the logical partition is mapped to an I/O adapter of the source system; copying, to the target system, configuration information describing the mapping of the logical partition to the I/O adapter; copying, to the target system, the logical partition of the source system; placing an I/O adapter of the target system into an error state; mapping, in dependence upon the configuration information, the logical partition of the target system to the I/O adapter of the target system; placing the I/O adapter of the target system into an error recovery state; and resuming the logical partition on the target system.

Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.

Abstract: Systems, methods, and computer-readable storage media for hardware recovery are disclosed. In some examples, a system can detect a hardware error and identify a system component associated with the hardware error. The system can then generate a request configured to trigger an operating system of the system to place the system in a particular operating state. The particular operating state can be determined based on a component type of the system component. The particular operating state can be a first sleep state when the component type is a peripheral component or a second sleep state when the component type is a processor, a memory, or a power supply. The second sleep state can result in a lower power resource consumption than the first sleep state. The system can generate an indication that the system component can be replaced without restarting the operating system.

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

Abstract: A monitoring device is mounted in each of a plurality of operational systems constituting a fault-tolerant system. The plurality of operational systems have an identical configuration including a processor system. The monitoring device includes a processor. The processor executes instruction to read data from a predetermined storage area in a memory of an accessory device to be monitored, connected to the processor system. The processor further executes instruction to compare the read data with reference data held in advance. The processor further executes instruction to separate the processor system connected to the accessory device to be monitored from the fault-tolerant system when the read data is different from the reference data.

Abstract: A processing device to receive, from a second node in the data grid system, a first filter. The processing device may detect a failure of a third node of the data grid system. The processing device may determine that the backup data stored at the first node matches the first filter. The processing device may send, to the second node, a duplicate data notification indicating that the backup data comprises, at least in part, first data duplicative to second data communicated to the second node from the third node.

Abstract: A method for processing a fault of a lock server in a distributed system is disclosed, where the distributed system includes m lock servers, which locally store same lock server takeover relationship information. Lock servers in the distributed system that are not faulty receive a notification message, which carries information about a fault of a first lock server; after receiving the notification message, a second lock server determines that it is a takeover lock server of the first lock server according to the lock server takeover relationship information, and the takeover lock server enters a silent state; after receiving the notification message, a third lock server in the distributed system determines that it is not the takeover lock server of the first lock server according to the lock server takeover relationship information. After receiving a locking request, the third lock server allocates lock permission information according to the locking request.

Abstract: Failover of a virtual function exposed by an SR-IOV adapter of a computing system, including: instantiating, by a hypervisor, a standby virtual function in the computing system; detecting a loss of communication between a logical partition and an active virtual function mapped to the logical partition; placing the active virtual function and the standby virtual function in an error state; remapping the logical partition to the standby virtual function; and placing the standby virtual function in an error recovery state.

Abstract: A system and method for responding to a virtual machine (VM) network failure for a host in a network partition in a high availability (HA) cluster. The method includes providing a plurality of network partition response options; and receiving a selection of a first network partition response option from the plurality of network partition response options, the selected first network partition response option causing a processor to transfer execution of a VM on the host to a second host that has VM network connectivity upon detecting a VM network failure for the host.

Abstract: Methods, systems, and computer readable media for managing suspect subscriber bindings. In some examples, a method is performed by a Diameter signaling router (DSR) for a telecommunications network. The method includes binding a subscriber to a first policy and charging rules function (PCRF) server selected from a plurality of PCRF servers for the telecommunications network. The method includes determining that one or more messages destined to the first PCRF server have failed according to one or more user-configurable rules defining failure. The method includes tearing down the binding between the subscriber and the first PCRF server.

Abstract: An apparatus includes nodes each configured to relay data between the nodes. When a failure occurs in a first-node, a management-node determines, based on power consumption and/or memory usage of the nodes, a collection-node that transmits an instruction in first direction approaching the first-node and a second direction approaching a storage-node, respectively. A second-node that is neither an adjacent-node adjacent to the first-node nor the storage-node, upon receiving data including the instruction, transmit data obtained by adding an evaluation value for the second-node to the received data, in the first or second direction.

Abstract: A distributed storage and replication system includes a MDC module, multiple IO routing modules, and multiple OSD nodes. The MDC module is adapted to configure at least two partition, the IO routing module is adapted to route an IO request to an OSD node, and the OSD node is adapted to execute storage of data corresponding to the IO request. The MDC is configured to determine a faulty OSD node, update a partition view of a partition group that includes a partition on the faulty OSD node, and send an updating notification to a primary OSD node in the updated partition view. The primary OSD node is adapted to process replication of the data corresponding to the IO request. According to embodiments of the present disclosure, processing performance, fault tolerance, and availability of consistency replication are improved.

Abstract: There are provided an electronic device, and more particularly, to a controller of a semiconductor memory device with an increased operation speed and a method of operating the same. The method of operating the controller configured to control the semiconductor memory device includes obtaining a recovery address in which recovered data stored in a page buffer of the semiconductor memory device in which the program fail is generated is to be stored, transmitting a recovery command requesting the semiconductor memory device to transmit the recovered data to the semiconductor memory device, and storing the recovered data in the recovery address. The obtaining of the recovery address, the transmitting of the recovery command, and the storing of the recovered data in the recovery address are simultaneously performed while a post-processing operation is performed on the program fail.

Abstract: According to an example, a failed component in a fault-tolerant memory fabric may be determined by transmitting request packets along a plurality of routes between the redundancy controller and a media controller in periodic cycles. The redundancy controller may determine whether route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles. In response to determining that route failures for all of the plurality of routes have occurred within a number of consecutive periodic cycles, the media controller is established as failed. In response to determining that route failures for less than all of the plurality of routes have occurred within the number of consecutive periodic cycles, a fabric device is established as failed.

Abstract: To ensure that there is an elected manager among storage nodes of an erasure coding group (“ECG”), an ECG manager (“ECGM”) election process is periodically performed among available storage nodes that are configured with the software to perform the services of an ECGM. When a storage node is activated, an ECGM process of the storage node begins executing and is assigned a process identifier (“PID”). A storage node can utilize a service query framework to identify other available storage nodes and retrieve their ECGM PIDs. The storage node then selects a PID according to a criterion and elects the storage node corresponding to the selected PID to be the acting ECGM. This process is performed periodically, so even if the acting ECGM storage node fails, a new ECGM is eventually selected from the available storage nodes.

Abstract: A storage controller failover system includes servers, storage controllers coupled to storage subsystems, and a switching system coupling the servers to the storage controllers. A storage controller configurations and storage controller caches for each of the storage controllers are stored in one or more database. A failure is detected of a first storage controller that has provided first storage communications along a first path between a first server and a first storage subsystem and, in response, a second storage controller that is configured to take over the first storage communications from the first storage controller is determined based on its second storage controller configuration. A first storage controller cache for the first storage controller is provided to the second storage controller, and the second storage controller is caused to provide the first storage communications along a second path between the first server and the first storage subsystem.

Abstract: In one embodiment, a method of false sharing detection includes performing, by a device, a plurality of optimization passes on source code, to produce optimized source code and receiving, by the device, selection criteria, The method also includes adding instrumentation to the optimized source code, by the device, after performing the plurality of optimization passes, to produce an instrumented code, where the instrumentation is configured to track memory access addresses and access types of global variables and heap variables in accordance with the selection criteria.

Abstract: By monitoring requests to and from components of an application, an application analysis engine generates an inter-component graph for an application that identifies how the various components in the application are connected. When a performance issue is detected in association with the application, a traversal module traverses the inter-component graph to determine the possible execution paths that may have been the cause of the detected issue. The traversal module transmits requests to the correlation module to compare the metrics time series of the different components in the execution path with the detected issue. The correlation module compares metrics time series with the issue metric to identify correlations between execution patterns. The results of the correlation may be presented in a report that visually identify the root cause of the detected issues.

Abstract: Some examples described herein relate to testing of a cloud service. In an example, a cloud service to be tested may be deployed in a cloud system. A test load may be applied to the cloud service. Upon application of the test load to the cloud service, a determination may be made whether a performance metric related to the cloud service meets a pre-configured criterion. If the performance metric related to the cloud service meets a pre-configured criterion, the cloud service may be scaled. Operations of applying, determining, and scaling may iterated until an end condition is met, wherein the test load applied to the cloud service may vary after each iteration operation.

Abstract: The present invention concerns a method for verifying traceability of first code instructions in a procedural programming language generated from second code instructions in a modelling language, characterised in that it comprises the implementation, by a piece of equipment (1), of steps of: (a) Syntactic analysis: o of the first instructions so as to generate an AST, and o of the second instructions so as to generate an MDT; (b) Semantic analysis: o Of the AST so as to identify patterns representative of basic functional blocks of the first instructions; o Of the MDT so as to identify characteristic properties of basic functional blocks of the second instructions; (c) Matching, pairwise, the identified basic functional blocks, and confirming the traceability of first code instructions only if: o for each block of the first instructions, there is a functionally equivalent block in the second instructions, and o for each block of the second instructions, there is a functionally equivalent block in the first in

Abstract: Described is a computer-implemented method of reordering condition checks. Two or more condition checks in computer code that may be reordered within the code are identified. It is determined that the execution frequency of a later one of the condition checks is satisfied at a greater frequency than a preceding one of the condition checks. It is determined that there is an absence of side effects in the two or more condition checks. The values of the condition checks are propagated and abstract interpretation is performed on the values that are propagated. It is determined that the condition checks are exclusive of each other, and the condition checks are reordered within the computer code.

Abstract: A system for verifying historical artifacts in disparate source control systems. The system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method for obtaining historical artifacts from a target repository; obtaining historical artifacts from a source repository; and verifying the historical artifacts in the target repository match the historical artifacts in the source repository. Verification further comprises comparing commit data in the historical artifacts in the target repository with commit data in the historical artifacts in the source repository; and evaluating whether each commit data event in the historical artifacts in the target repository is equivalent to the corresponding commit data event in the historical artifacts in the source repository.

Abstract: Synchronization points are inserted into a program code to be monitored, and are associated with different branches resulting from execution of an indirect branch instruction. The synchronization points can be accessed by the monitored program code for the purpose of identifying which branch to use during execution of the indirect branch instruction of the monitored program code.

Abstract: A system and method for managing the migration of software components among test servers that form a distributed software test environment to ensure that the software components in each of the test servers represent a production environment except for software components being tested. The system further ensures that component changes rolled out into production are not overridden when multiple update requests are made for the same component.

Abstract: A graphical tool generates test scenarios to be simulated on an integrated circuit. The tool provides for the assembly of a graphical flow chart that represents source code associated with test scenarios, which helps alleviate the need for manual coding and de-bugging.

Abstract: A method includes receiving, via a processor, a model, a test case, and one or more suspect elements. The method includes calculating, via the processor, a relevance score for each model element of the model based on the one or more suspect elements. The method includes setting, via the processor, a threshold reduction score. The method includes generating, via the processor, a reduced model by reducing the model based on the relevance scores and the threshold reduction score. The method includes evaluating, via the processor, the reduced model based on the test case. The method includes detecting, via the processor, the reduced model reproduces an expected behavior. The method includes outputting, via the processor, a result model in response to detecting the reduced model reproduces the expected behavior. The method includes modifying, via the processor, an application associated with the model based on the reduced model.

Abstract: According to an aspect of an embodiment, a method may include identifying a fault at a fault location in a software program using a test suite. The method may also include determining multiple textual similarity scores by determining a textual similarity score with respect to each of multiple repair candidates for the fault. In addition, the method may include sorting the repair candidates based on the textual similarity scores. The method may also include selecting a particular repair candidate from the repair candidates based on the sorting. Moreover, the method may include implementing the particular repair candidate at the fault location based on the selection of the particular repair candidate.

Abstract: A system and method are provided for data collection and analysis of information related to applications. Specifically, the developer of the application may install analytic software, which may be embodied as a software development kit (SDK), on an integrated development environment (“IDE”) associated with the developer, wherein the analytic software may be installed with a wizard-like interface having a series of easy to follow instructions. Once installed, the application, with the analytic software incorporated therein, may be provided and installed on a plurality of end user devices. Thereafter, the analytic software may work in conjunction with analytic processing logic to assist the developer in obtaining pertinent information related to bugs associated with the application that is being executed on an end user device.

Abstract: Systems and methods are provided for resiliency testing microservice-based applications. For example, a method for resiliency testing an application includes receiving a test script that specifies a failure scenario in a distributed microservice-based application comprising a plurality of microservices, and an asserted behavioral expectation of at least one microservice of the distributed microservice-based application in response to the specified failure scenario. The specified failure scenario is translated into fault injection rules. The fault injection rules are utilized to execute fault injection operations on messages that are exchanged between at least a first microservice and a second microservice of the distributed microservice-based application, to stage the specified failure scenario during the failure recovery testing of the distributed microservice-based application.

Abstract: A method of managing a storage system having one or more storage devices includes a host-based garbage collection operation that includes identifying a logical stripe in accordance with data storage information stored at the host system, and enabling a process of coalescing valid data in a target logical stripe, the coalescing process including moving the valid data in the logical stripe and repacking valid logical addresses to the beginning of the target logical stripe, comprising the identified logical stripe or another logical stripe. Further, the use of an internal copy operation allows the host-based garbage collection operation to occur without transferring data back to the host, thus minimizing the number of I/O operations between the host and storage devices. Additionally, use of the host-based garbage collection operation allows device-level garbage collection to be minimized, and more sophisticated garbage collection algorithms (e.g., matching the current workload) to be used.

Abstract: A memory system includes a memory device including a plurality of memory blocks and a controller suitable for selecting first memory blocks, the number of valid pages of which is equal to or less than a first threshold value, among the plurality of memory blocks, and performing a garbage collection operation on the first memory blocks based on error bit information of the first memory blocks.

Abstract: A method for scheduling read commands, performed by a processing unit, contains the following steps: Logical read commands are received from a master device via a first access interface, where each logical read command requests to read data of a logical address. First physical storage locations of mapping segments associated with the logical addresses are obtained from a high-level mapping table, and a second access interface is directed to read the mapping segments from the first physical storage locations of a storage unit. Second physical storage locations associated with the logical addresses are obtained from the mapping segments, and the second access interface is directed to read data from the second physical storage locations of the storage unit. The first access interface is directed to clock the data of the logical addresses out to the master device.

Abstract: A technique for garbage collection in a storage system includes generating regrouping metadata for one or more pages of at least two logical erase blocks (LEB). The regrouping metadata indicates an associated stream for each of the pages. Multiple of the LEBs that include valid pages associated with a first stream are selected, based on the regrouping metadata, for regrouping. The valid pages associated with the first stream from the selected LEBs are regrouped into a new LEB.

Abstract: A technique for garbage collection in a data storage system includes determining a dirty physical byte count for each of a plurality of candidate garbage collection units. The dirty physical byte count provides a total amount of dirty bytes. At least one of a dirty physical codeword container count and a dirty physical page count is determined for each of the candidate garbage collection units. The dirty physical codeword container count provides an amount of physical codeword containers that are completely dirty and the dirty physical page count provides an amount of physical pages that are completely dirty. A garbage collection unit, included in the candidate garbage collection units, is selected for garbage collection based on the dirty physical byte count and at least one of the dirty physical codeword container count and the dirty physical page count.

Abstract: Systems, methods and/or devices are used for efficient implementation of optimized host-based garbage collection strategies using xcopy and arrays of flash devices. In one aspect, a method of managing a storage system having one or more storage devices includes a host-based garbage collection operation that includes identifying two or more logical stripes in accordance with data storage information stored at the host system, and enabling a process of coalescing valid data in the two or more logical stripes. Further, the use of an internal copy operation (e.g., xcopy), allows the host-based garbage collection operation to occur without transferring data back to the host, thus minimizing the number of I/O operations between the host and storage devices. Additionally, use of the host-based garbage collection operation allows more sophisticated garbage collection algorithms (e.g., matching the current workload) to be used, and ensures that multiple logical stripes are available to write data.

Abstract: In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host.

Abstract: A storage device includes a disk including a plurality of tracks, each track including a plurality of addressable blocks of data, a buffer memory, and a controller that stores in the buffer memory, in response to a command to read a first value of a first key, the first value, and also a second value of a second key upon determining that the second value is entirely readable after the first value is read, from the same track as the first value.

Abstract: Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches is provided. In one aspect, a DRAM cache management circuit is provided to manage access to a DRAM cache in high-bandwidth memory. The DRAM cache management circuit comprises a DRAM cache indicator cache, which stores master table entries that are read from a master table in a system memory DRAM and that contain DRAM cache indicators. The DRAM cache indicators enable the DRAM cache management circuit to determine whether a memory line in the system memory DRAM is cached in the DRAM cache of high-bandwidth memory, and, if so, in which way of the DRAM cache the memory line is stored.

Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

Abstract: A computer system includes transactional memory to implement a nested transaction. The computer system generates a plurality of speculative identification numbers (IDs), identifies at least one of a software thread executed by a hardware processor and a memory operation performed in accordance with an application code. The computer system assigns at least one speculative cache version to a requested transaction based on a corresponding software thread. The speculative ID of the corresponding software thread identifies the speculative cache version. The computer system also identifies a nested transaction in the memory unit, assigns a cache version to the nested transaction, detects a conflict with the nested transaction, determines a conflicted nesting level of the nested transaction, and determines a cache version corresponding to the conflicted nesting level. The computer system also invalidates the cache version corresponding to the conflicted nesting level.

Abstract: A computer system includes transactional memory to implement a nested transaction. The computer system generates a plurality of speculative identification numbers (IDs), identifies at least one of a software thread executed by a hardware processor and a memory operation performed in accordance with an application code. The computer system assigns at least one speculative cache version to a requested transaction based on a corresponding software thread. The speculative ID of the corresponding software thread identifies the speculative cache version. The computer system also identifies a nested transaction in the memory unit, assigns a cache version to the nested transaction, detects a conflict with the nested transaction, determines a conflicted nesting level of the nested transaction, and determines a cache version corresponding to the conflicted nesting level. The computer system also invalidates the cache version corresponding to the conflicted nesting level.

Abstract: A processor includes a first core including a first cache including a cache line, a second core including a second cache, and a cache controller to set a flag stored in a flag section of the cache line of the first cache to one of a processor share (PS) state in response to data stored in the cache line being shared by the second cache, or to a global share (GS) state in response to the data stored in the first cache line being shared by a third cache of a second processor.

Abstract: In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

Abstract: Systems, methods and/or devices are used to perform memory-efficient mapping of block/object addresses. In one aspect, a method of managing a storage system having one or more storage devices includes a tiered data structure in which each node has a logical ID and entries in the nodes reference other nodes in the tiered data structure using the logical IDs. As a result, when a child node is updated and stored to a new location, but retains its logical ID, its parent node does not need to be updated, because the logical ID in the entry referencing the child node remains unchanged. Further, the storage system uses a secondary mapping table to translate the logical IDs to the corresponding physical locations of the corresponding nodes. Additionally, the secondary mapping table is cached in volatile memory, and as a result, the physical location of a required node is determined without accessing non-volatile memory.

Abstract: A disclosed hash generation method includes: calculating a hash matrix for identifying original data, which corresponds to a product multiplied by a partial hash matrix of a last block of plural blocks divided from the original data, from a product for each of blocks other than the last block, which is calculated by multiplying from a partial hash matrix of a first block of the plural blocks up to a partial hash matrix of the block; and calculating a hash matrix for identifying changed data, by multiplying a product of a product multiplied lastly by a partial hash matrix of a block immediately before a changed block and a partial hash matrix of the changed block by an inverse matrix of a product multiplied lastly by a partial hash matrix of an unchanged original block and a product multiplied lastly by a partial hash matrix of the last block.

Abstract: A system includes a processor configured to erase external working memory and program a target image of an authenticated update file into the erased working memory. The processor is also configured to erase a first internal memory location, containing data to be replaced by an update, and program portions of the target image to the first internal memory location for finite time periods following a plurality of key-offs, until a full target image is programmed in internal memory.

Abstract: The present disclosure provides a method and apparatus of setting an encrypted storage area, and a terminal. The method of setting an encrypted storage area is applicable to a terminal having multiple operating systems, and comprises: in any operating system, encrypting, by using a preset key stored in the any operating system, a storage area set for the any operating system in a storage card; setting the encryption state of the storage area to be encrypted, and storing the encryption state into the storage area; and storing data that is required to be encrypted, of the any operating system, into the storage area. By means of the technical scheme of the present disclosure, the security of data stored in an encrypted storage area of a storage card can be ensured, and multiple operating systems of a terminal can share the remaining space of the storage card, and the requirements of the operating systems on high storage speed are satisfied.

Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.

Abstract: A system and method for providing a multi-modal active cable. In certain embodiments, the multi-modal active cable enables transmission of alternative display information from a source system. More specifically, in certain embodiments, the multi-modal active cable comprises a switching component to allow host system integrated I/O signals to be provided as either I/O adapter integrated I/O signals or dedicated display signals via a single multi-modal active cable. In certain embodiments, the integrated I/O signals comprise Thunderbolt I/O signals. In certain embodiments, the dedicated display signals comprise DisplayPort signals. In certain embodiments the switching component comprises at least one radio frequency (RF) microwave high performance analog switches to switch the high speed digital signals (e.g., signal speeds up to 40 Gbps on each of a plurality of lane). By using such switches, the load capacitance on the signal paths is minimized as the impedance is carefully controlled.