Abstract: Events generation systems and methods are provided. The system obtains, in real time, input stream data from one or more sources, filters, the input stream data by identifying one or more authentic sources to obtain filtered input stream data, parses, the filtered input stream data to obtain validated data in a specific data format, performs apply, in real time, an analysis on the validated data and on the corresponding one or more authentic sources by applying, at least one of one or more metadata driven logics and one or more predefined rules and further generates generate, in real time, one or more real time events based on the analysis.

Abstract: A control device for controlling equipment or a machine includes: one or more processors, a general-purpose OS and a real-time OS executed in parallel on the one or more processors, and an input interface that receives a cutoff event from outside, wherein the real-time OS provides an execution environment of a user program for realizing control over the equipment or machine. The real-time OS has a function of executing a shutdown preparation process required for shutdown of the real-time OS in response to the cutoff event; a function of instructing the general-purpose OS to shut down after executing the shutdown preparation process; and a function of completing the shutdown of the real-time OS and cutting off power supply of the control device when a predetermined condition is satisfied, wherein the predetermined condition includes receipt of a notification of shutdown completion from the general-purpose OS.

Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.

Abstract: A device may identify a tool operating on a first device for integration into a lifecycle management platform operating on a second device. The tool may be associated with providing a functionality not included in the lifecycle management platform. The first device may be external to the second device. The device may determine a set of tool attributes for data events associated with the tool. The data events may include a data input, a data output, a new message, an updated message, a deleted message, or the like. The device may select a message format based on the set of tool attributes. The device may configure adaptation for a tool application programming interface (API) of the tool and a platform API of the lifecycle management platform based on the message format. The device may provide information associated with configuring adaptation for the tool API and the platform API.

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Abstract: An aspect includes identifying a repaired memory array element in a memory array, and identifying memory array elements in the memory array that are adjacent to the repaired memory array element. A group that includes the repaired and adjacent memory array elements is formed and monitored for error conditions. It is determined whether a number of the error conditions exceeds a threshold. A repair action is performed to the memory array based on determining that the number of error conditions exceeds the threshold.

Abstract: A computer implemented method comprises accessing a plurality of calendars, each calendar defining a schedule of calendar days, receiving a plurality of inputs from one or more applications, each input defining a data event for a specific source, for each calendar of the plurality of calendars, maintaining, for each data event source, a count for each calendar day and a count for each non-calendar day, for each calendar of the plurality of calendars, determining, for each data event source, if a comparison of the count for each calendar day and the count for each non-calendar day is statistically significant, and generating an output for a data event source, if the comparison of the count for each calendar day and the count for each non-calendar day is statistically significant.

Abstract: A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. The predetermined temporal relationship may require the first state machine to progress to the first state machine state before the progress to the second state. The current state of the temporal relationship state machine may be one of a first temporal relationship state and a second temporal relationship state. The second state may be a second state machine state of the first state machine. The second state may be a second state machine state of a second state machine.

Abstract: In one example, a method includes generating a set of predicted load values for at least one physical component, each predicted load value corresponding uniquely to one of an ordered sequence of index values. The method further includes determining a set of predicted wear indicator values corresponding to the at least one physical component. Each predicted wear indicator value corresponds uniquely to one of the ordered sequence of index values and is determined based on one of the predicted load values that corresponds to a sequentially previous index value and one of the predicted wear indicator values that corresponds to the sequentially previous index value. The method further includes determining a predicted amount of remaining useful life of the at least one physical component based on the set of predicted wear indicator values, and outputting an indication of the predicted amount of remaining useful life.

Abstract: Various techniques are provided to efficiently implement deterministic read back and error detection for programmable logic devices (PLDs). In one example, a PLD includes an array of memory cells arranged in rows and columns, where at least one row includes an enable bit. The PLD further includes an address logic circuit configured to selectively assert the columns of the array by respective address lines. The PLD further includes a register configured to store a value of the enable bit in response to an assertion of an address line corresponding to the enable bit. The PLD further includes a read back circuit configured to selectively provide, for each memory cell, a data bit value stored by the memory cell or a predetermined data bit value based at least on the stored value of the register. Additional systems and related methods are provided.

Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

Abstract: An information handling system includes a network interface device coupled to a network, a memory including first code to instantiate an operating system including an exception handler and second code to instantiate an exception handler interface and a UNDI module, and a processor to execute the first code and the second code. The network interface device is responsive to a Universal Network Device Interface (UNDI) command. The operating system detects an exception and invokes the exception handler to write a stack frame associated with the exception to the memory in response to detecting the exception. The exception handler interface determines that the stack frame has been written in the memory and directs the UNDI module to provide the UNDI command to the network interface device to communicate the stack frame to the network.

Abstract: A computer-implemented method includes calculating a first efficiency of a first device connected to a host system when a second device is not connected to the host system. Connection of the second device to the host system is detected. The method further includes calculating a second efficiency of the first device when the second device is connected to the host system. An interference quotient of the first device is calculated, by a computer processor, based on the first efficiency and the second efficiency. A user is warned of interference between the first device and the second device, responsive to the interference quotient being in an unacceptable range.

Abstract: Systems (100) and methods are provided for obtaining process model which comprises of process maps, wherein process maps comprises of process levels and sub levels, which are configured with key metrics and corresponding time stamp to monitor health of process model. During execution of process model and therein the process levels, configured key metrics are monitored and compared with the pre-defined threshold value. Any increase in the key metrics beyond threshold limit, one or more events are determined, which are analyzed and based on the time stamp of the events, process levels and sub levels are identified and rectified. In one of the embodiment, system (100) enables replay process to replay process model for problem determination purpose. In the replay process, system (100) enables viewing of obtained process model wherein process definition and data with time stamp is in XML format for every step which is recorded in the past.

Abstract: Systems, methods, circuits and computer-readable mediums for multi-channel RAM system with error-correcting code (ECC) protection for partial writes are provided. In one aspect, a method includes accessing a plurality of bursts of partial data units from a plurality of respective bus ports, forming a plurality of memory addresses for a plurality of memory channels by interleaving addresses from the plurality of bus ports, and performing read-modify-write (RMW) error-correcting code (ECC) processes to write partial data units from the plurality of bursts into memory portions corresponding to the formed memory addresses in the plurality of memory channels.

Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory cells; and a controller suitable for reading target data from a target page corresponding to the plurality of memory cells, estimating error bits of the target data based on reference data read from at least one reference page corresponding to the plurality of memory cells of the target data, and performing an error correction operation to the target data based on a result of the estimation.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Once Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.

Abstract: A method for execution, when a generic computing device is paired with a specific computing device (SCD) token, begins with the SCD token sending distributed storage network (DSN) access request to DSN memory via the generic computing device, wherein the DSN access request identifies SCD operation information that is stored as one or more of sets of encoded data slices in the DSN memory and wherein the SCD operation information was encoded using a dispersed storage error encoding function to produce the plurality of sets of encoded data slices. Then, the SCD token receives the one or more of sets of encoded data slices from the DSN memory via the generic computing device and decodes the one or more of sets of encoded data slices to retrieve the SCD operation information and enables the generic computing device to function as an SCD in accordance with the SCD operation information.

Abstract: Cataloging file system-level changes to a source storage between image backups of the source storage. In one example embodiment, a method for cataloging file system-level changes to a source storage between image backups of the source storage may include obtaining first file system metadata (FSM) associated with a first image backup of the source storage that represents a first point in time, obtaining second FSM associated with a second image backup of the source storage that represents a second point in time, identifying a set of blocks that changed in the source storage between the first point in time and the second point in time, analyzing the set of blocks, the first FSM, and the second FSM, and cataloging files and/or directories that changed in the source storage between the first point in time and the second point in time based on the analyzing.

Abstract: Providing snapshot isolation to a database managed by a database management system includes providing a program module to analyze a plurality of database queries directed at a table of the database and generates a view for said table. The table comprises a counter value column and the view is configured to selectively read, upon being called, data records having assigned particular counter values. The program module modifies the view of said table such that the particular counter values comprise counter values generated at moments when the program module received respective write queries which have already committed at the moment of modifying the view, are free of counter values of data records having become outdated by an update statement committed at the moment of modifying the view, and are free of counter values generated by the counter after the moment of modifying the view.

Abstract: In one example, backing up disk array volumes creates a snapshot of a volume of a disk array. Unshared blocks between a previous snapshot and the snapshot are identified to generate an allocation map. Source-side de-duplication is performed for a stream comprising the snapshot. The unshared blocks are folded into an endpoint store that includes a full backup of the volume, to generate a synthetic full of the volume.

Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.

Abstract: Embodiments of the present invention provide a data management technology. An OSD receives a strip write request sent by a client server, where the strip write request carries a to-be-written strip, a version number of the to-be-written strip, an offset of the to-be-written strip, and an object ID of the to-be-written strip; and the OSD writes the to-be-written strip into a storage location determined by using the object ID, the version number of the to-be-written strip, and the offset of the to-be-written strip. By applying the present invention, a quantity of object IDs can be reduced.

Abstract: A method for distributing data among storage devices. The method comprising one or more processors receiving a first graph workload that executes within a networked computing environment. The method further includes identifying data from the first graph workload that is utilized during the execution of the first graph workload that includes a plurality of data packets. The method further includes creating a first graph workload model representative of the graph structure of the first graph workload and determining two or more partitions that are representative of a distribution of the identified data utilized by the first graph workload based, at least in part, on the first graph workload model. The method further includes allocating a plurality of network accessible storage devices among the two or more partitions and copying a first set of data packets of the plurality of data packets to a network accessible storage device.

Abstract: A hash-optimized backup system and method takes data blocks and generates a probabilistically unique digital fingerprint of the content of each data block using a substantially collision-free algorithm. The process compares the generated fingerprint to a database of stored fingerprints if the generated fingerprint matches a stored fingerprint, the data block is determined to already have been backed up, and therefore does not need to be hacked up again. Only if the generated fingerprint does not match a stored fingerprint is the data block backed up, at which point the generated fingerprint is added to the database of stored fingerprints. Because the algorithm is substantially collision-free, there is no need to compare actual data content if there is a hash-value match. The process can also be used to audit software license compliance, inventory software, and detect computer-file tampering such as viruses and malware.

Abstract: Provided is a database journaling method and apparatus for storing a log file in a storing apparatus by performing a lesser number of record commands to decrease a volume of data to be input and output by the storing apparatus, and the database journaling method may include determining whether a database is changed based on an operation performed on data in the database, generating a log file including log entries for the database when the database is changed, and performing journaling on the database by storing the generated log file in a storing apparatus, wherein each of the log entries includes a log record in which the data associated with a change of the database is stored, and metadata for the log record is recorded in a predetermined area embedded in the log record.

Abstract: A Management system 10 includes: resource pools 111-114 which act as the hardware components on which multiple virtual machines are running; an inter-connecting network 12 which connects various resource pools; and a HA manager 13 which snoops all traffic of the inter-connecting network 12 to detect failure of a target VM and triggers corresponded actions when failure is detected.

Abstract: Concepts and technologies are disclosed herein for using diversity to provide redundancy of virtual machines. A server computer that executes an orchestrator application can receive a virtual machine instantiation request. The server computer can analyze the request to determine needs associated with a virtual machine (including a redundancy requirement). The server computer can obtain resource availability data that indicates availability of resources and includes diversity data used to provide diversity-based redundancy of the virtual machine. The server computer can identify a pool of resources and identify, among the pool, two or more resources. The two or more resources can include a most diverse group of resources of the pool of resources and can be identified based upon the diversity data. The server computer can trigger instantiation of the virtual machine and a copy of the virtual machine on the resources.

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Abstract: The disclosure is directed to a failover mechanism for failing over an application service, e.g., a messaging service, from servers in a first region to servers in a second region. Data is stored as shards in which each shard contains data associated with a subset of the users. Data access requests are served by a primary region of the shard. A global shard manager manages failing over the application service from a current primary region to a secondary region of the shard. A leader service in the application service replicates data associated with the application service from the primary to the secondary region, and ensures that the state of various other services of the application service in the secondary region is consistent. The leader service confirms that there is no replication lag between the primary and secondary regions and fails over the application service to the secondary region.

Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.

Abstract: Methods for system failure prediction include clustering log files according to structural log patterns. Feature representations of the log files are determined based on the log clusters. A likelihood of a system failure is determined based on the feature representations using a neural network. An automatic system control action is performed if the likelihood of system failure exceeds a threshold.

Abstract: Mobile phones and methods for mobile phone failure prediction include receiving respective log files from one or more mobile phone components, including at least one user application. The log files have heterogeneous formats. A likelihood of failure of one or more mobile phone components is determined based on the received log files by clustering the plurality of log files according to structural log patterns and determining feature representations of the log files based on the log clusters. A user is alerted to a potential failure if the likelihood of component failure exceeds a first threshold. An automatic system control action is performed if the likelihood of component failure exceeds a second threshold.

Abstract: A device maintenance apparatus includes a setting operator configured to allow for setting a test pattern, the test pattern being set to define a change of output signals output from a device over time, and an execution operator configured to make the device output the output signals based on the set test pattern.

Abstract: Utilities (e.g., methods, systems, apparatuses, etc.) for use in automatically identifying improper physical connections in storage networks and recommending particular actions (e.g., changes to existing physical connections) that seek to ensure symmetric and redundant connections from a data host through all associated storage enclosures and reduce the likelihood that single failures prevent access to storage system data.

Abstract: Code monitoring and optimization may include code being monitored for potential security violations during an active code creation session. The procedure may include at least one of monitoring code for potential security violations during an active code creation session occurring on a client device, comparing the monitored code with an aggregate rule set stored in a repository, identifying at least one of a security violation or an error based on the comparing and identifying a correction to the at least one of the security violation or the error during the active code creation session.

Abstract: A compiler, IDE or other code analyzer may determine whether an instance variable declaration assignment is redundant. The code analyzer may also take action based on that determination. A code analyzer may be able to determine with certainty that a particular instance variable initialization or assignment is definitely redundant. The code analyzer may cause a compiler to automatically elide the redundant assignment from compiled source code. The code analyzer may be able to determine with certainty that a particular assignment is definitely not redundant. Additionally, a code analyzer may not be able to determine with certainty whether an instance variable assignment is definitely redundant or definitely not redundant. Additionally, the code analyzer may report a warning or other informative message indicating the redundancy property of the assignment, thus alerting the programming to a (possibly) redundant assignment.

Abstract: In one example of the disclosure, a graphic user interface is provided and a plurality of factors to be considered by a user in evaluating a test application are caused to be displayed via the interface. The test application to test a software program. User-assigned ratings for test application evaluation factors are received via the interface. The test application evaluation factors include a documentation test quality factor, a product-general test quality factor; a product-specific test quality factor, and a defect seventy factor. An overall test effectiveness rating for the test application is determined based upon the ratings.

Abstract: A computer-implemented system for generating test cases and/or test procedures to verify software having a nonlinear arithmetic constraint over a Real number range. The system includes a translator that receives, as input, software specification models for the software to be verified. The translator is configured to generate, as output, a plurality of SMT formulas that are semantically equivalent to the software specification models. The system includes an analytical engine pool that receives, as input, the plurality of SMT formulas from the translator and analyzes the plurality of SMT formulas, and generates, as output, test case data for each of the plurality of SMT formulas determined to be satisfiable. The system includes a post-processor that receives, as input, the test case data from the analytical engine pool and generates, as output, the test cases and/or test procedures for the software to be verified based on the test case data.

Abstract: Disclosed are an apparatus and method for generating a scenario for testing interoperability of robot software. The apparatus for generating a scenario for testing interoperability of robot software includes a user interface unit for receiving a request to test a component under test from a user, a semantic model-mapping unit for mapping a test case semantic model to the component under test, a test scenario template selection unit for selecting a test scenario template corresponding to a type of the component under test, a test case component selection unit for selecting a test case component based on whether the mapped test case semantic model corresponds to a source or a target, and an interoperability test scenario generation unit for generating an interoperability test scenario based on information about a connection between the component under test and the test case component in the selected test scenario template.

Abstract: Example implementations relate to separating verifications from test executions. Some implementations may include a data capture engine that captures data points during test executions of the application under test. The data points may include, for example, application data, test data, and environment data. Additionally, some implementations may include a data correlation engine that correlates each of the data points with a particular test execution state of the application under test based on a sequence of events that occurred during the particular test execution state. Furthermore, some implementations may also include a test verification engine that, based on the correlation of the data points, verifies an actual behavior of the application under test separately from the particular test execution state.

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.

Abstract: An example method includes receiving, by a software module that is executed by at least one processor of a computing device, memory write information indicating that the at least one processor has not written any data to a storage area of a memory of the computing device since a prior point in time, the memory write information being associated with the storage area and being based on information generated by a management unit of the computing device, the management unit comprising a hardware component of the at least one processor to manage data retrieved from and data written to the memory, and the storage area including a first object stored in the memory. The example method further includes determining, by the software module and based on the memory write information, to refrain from performing garbage collection on a second object stored in the memory and referenced by the first object.

Abstract: Systems and methods for determining a cumulative control state for mapping logical block addresses (LBAs) to physical block addresses (PBAs) are disclosed. One such system includes a bitonic network including first switches and configured to receive a first randomly ordered list and random switch settings, determine a permutation of the first randomly ordered list using the random switch settings at the first switches, where the permutation includes a second randomly ordered list, and output the second randomly ordered list; a bitonic sorter including second switches and configured to receive the second randomly ordered list, sort the second randomly ordered list, and output settings of the second switches used to achieve the sort, where the second switch settings define a cumulative control state; and an access network configured to determine a PBA of a non-volatile memory (NVM) to enable a data access of a corresponding LBA using the cumulative control state.

Abstract: A system and method provide for a better way of managing a shared memory system. A multiprocessor system includes a first and second CPU, with each CPU having a private L1 cache. The system further includes a level 2 (L2) cache shared between the first CPU and the second CPU, and includes a memory coherency manager (CM) and an I/O device. The second CPU is configured to request ownership of a cache line in the L1 cache of the first CPU that is in a Modified state. Later, upon receiving a read discard command from the I/O device, the second CPU is configured to request the CM update the cache line from a Modified state to a Shared state.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies. A first cache memory in a first vertical cache hierarchy issues on the system interconnect a request for a target cache line. Responsive to the request and prior to receiving a systemwide coherence response for the request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the request. In response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiates processing to install the target cache line in the first cache memory.