Abstract: A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: A data reading circuit including a phase difference determining module, a time delay detection module, and a reading control module, and the phase difference determining module is connected to the echo clock signal and a clock signal of the second clock domain. The phase difference determining module is configured to determine a phase difference between the echo clock signal and the clock signal of the second clock domain; the time delay detection module is configured to detect a time delay value in transmission of data from a buffer to a flip-flop; and the reading control module is configured to determine, according to the phase difference and the time delay value, a triggering edge, at which the flip-flop can read data output by the buffer, of the clock signal of the second clock domain.

Abstract: In an embodiment, a memory system comprises a memory array having memory cells. A decoder is coupled to the memory array and configured to decode input address signals to generate memory cell selection signals. An encoder is configured to generate encoded selection signals based on the memory cell selection signals. In another embodiment, a method comprises: receiving by the decoder of the memory system input address signals, generating, by the decoder, selection signals for selecting a memory cell in the memory array, and generating, by an encoder, encoded selection signals based on the selection signals.

Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.

Abstract: Disclosed is a memory system. The memory system includes a volatile memory device configured to exchange data with a host through a first channel, a nonvolatile memory device, and a memory controller connected with the volatile memory device through a second channel. The memory controller detects a request of the host or a power state and controls the volatile memory device and the nonvolatile memory device based on the detection result such that data stored in the volatile memory device is backed up in the nonvolatile memory device through the second channel. The volatile memory device includes a first interface for communicating with the host through the first channel and a second interface for communicating with the memory controller through the second channel.

Abstract: An apparatus includes a perpendicular magnetic tunnel junction (MTJ) including a free layer. The apparatus includes a spin orbit torque metal layer coupled to the perpendicular MTJ and configured to change a magnetization state of the free layer responsive to flow of a current along the spin orbit torque metal layer. The apparatus includes a random number generator configured to generate a random number at least partially based on a state of the perpendicular MTJ.

Abstract: According to one embodiment, a memory device includes a memory cell array; a generation circuit generating a reference current; a sense amplifier comparing a cell current flowing through a memory cell with the reference current; a first clamp transistor connected between the sense amplifier and the memory cell; a second clamp transistor connected between the sense amplifier and the generation circuit; a first interconnect layer connected to a gate of the first clamp transistor; a second interconnect layer connected to a gate of the second clamp transistor and arranged adjacent to the first interconnect layer; and a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer, a fixed voltage being applied to the first shield line.

Abstract: A memory circuit (100), comprises a first set of memory cells (102a; 202a) configured to operate in a direct access mode or in a refresh mode and a second set of memory cells (102b; 202b) configured to operate in the direct access mode and in the refresh mode. The memory circuit (100) further comprises a controller (104) configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory area, a first selection circuit for selecting a bit line of the first memory area, a second memory area, a second selection circuit for selecting a bit line of the second memory area, and a third selection circuit arranged between the first selection circuit and the second selection circuit and configured to select either the first selection circuit or the second selection circuit.

Abstract: A magnetic storage apparatus is disclosed, and is configured to access data. The magnetic storage apparatus includes a magnetic storage track, a first write apparatus, a second write apparatus, and a drive apparatus. The first write apparatus and the second write apparatus are located at different positions on the magnetic storage track. The first write apparatus is configured to write first data “0” or second data “1”. The second write apparatus is configured to write third data “2” and fourth data “3”.

Abstract: Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

Abstract: Provided is a refresh control device including: an arbitration operating unit configured to arbitrate (i) a memory access request for accessing a volatile memory that requires a refresh operation for holding data and (ii) a refresh trigger for requesting execution of the refresh operation; and a trigger generating unit configured to generate refresh triggers in a non-constant cycle to satisfy refresh-rate requirements defining the number of refresh operations necessary to be executed per predetermined period for the volatile memory to hold the data.

Abstract: Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

Abstract: A differential interface circuit includes a differential amplifier circuit, a common-mode feedback circuit and a feedback initialization circuit. The differential amplifier circuit is configured to receive and amplify a differential input signal so as to produce an amplified differential output signal. The common-mode feedback circuit is configured to estimate a common-mode level of the differential output signal, to produce a feedback value in response to the estimated common-mode level, and to adjust the differential amplifier circuit using the feedback value. The feedback initialization circuit is configured, in response to detecting that the differential input signal is in a range predefined as abnormal, to temporarily override the common-mode feedback circuit, and instead set the feedback value applied to the differential amplifier circuit to a predefined initialization value.

Abstract: A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.

Abstract: A memory device may include: a plurality of cell mats arranged in a plurality of rows and columns; a plurality of first drivers, each first driver being disposed on a left side of a corresponding cell mat of the plurality of cell mats and configured to drive a first sub-word line of the corresponding cell mat; and a plurality of second drivers, each second driver being disposed on a right side of the corresponding cell mat of the plurality of cell mats and configured to drive a second sub-word line of the corresponding cell mat, wherein, during an active operation, among the plurality of cell mats, sub-word lines of cell mats disposed in odd-numbered columns or sub-word lines of cell mats disposed in even-numbered columns are selectively activated.

Abstract: The present disclosure provides a static random access memory (SRAM) cell comprising first, second, and third fins defined in various well regions. The fins are spaced from each other along a first direction and extend lengthwise generally along a second direction perpendicular to the first direction. The fins include source, drain, and channel regions for various pull-up, pull-down, and pass-gate fin field-effect transistors (FinFETs). The SRAM cell further includes various gate features over the fins and extending lengthwise generally along the first direction. The gate features include gate regions for the various FinFETs.

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-up (PU1) transistor and a second pull-up (PU2) transistor. The at least one CBP facilitates biasing of at least one the PU1 and PU2 transistors during at least one of a read, write or standby operation of the structures.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.

Abstract: Technologies are generally described herein for technologies to sense the threshold voltage for memory cells in one sensing operation. The memory cells may be storage circuits for a flash memory device, such as a multilevel flash memory device. Data may be stored and retrieved in the memory cells of the flash memory without involving the use of hardwired or predetermined thresholds. According to some configurations, the sense time distribution from a set of flash cells (e.g., one row), may be processed to decode the digital state of each memory cell. In some examples, computer-executable instructions may be used to process and decode the digital state of the memory cells.

Abstract: A semiconductor memory includes a cell array including a plurality of resistive memory cells in which a plurality of columns and a plurality of rows are arranged, a read voltage application circuit configured to apply a read voltage to a selected memory cell of the plurality of resistive memory cells, a sensing circuit configured to detect an amount of a current flowing through the selected memory cell and sense data, and an overcurrent prevention circuit configured to reduce voltage levels at both ends of the selected memory cell when an overcurrent flows through the selected memory cell.

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract: A computing device includes a computation circuit and a data storage circuit. The computation circuit is coupled to the data storage circuit and is arranged for reading and writing data from/to the data storage circuit. The computing device includes a memory array of non-volatile memory elements and controlling circuitry connected to the memory array for reading and writing data from/to selected memory elements in the array. The computation circuit and the data storage circuit are located in the memory array, and the non-volatile memory elements of the memory array are memristor-type elements.

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Abstract: Access is obtained to a truth table having a plurality of rows, each including a plurality of input bits and a plurality of output bits. At least some rows include don't-care inputs. At least some of the rows are clustered into a plurality of multi-row clusters. At least some of the multi-row clusters are assigned to ternary content-addressable memory modules of a prefabricated programmable memory array. Instructions for interconnecting the ternary content-addressable memory modules with a plurality of input pins of the prefabricated programmable memory array and a plurality of output pins of the prefabricated programmable memory array are specified in a data structure, in order to implement the truth table.

Abstract: The consumption current of a TCAM device is reduced. A semiconductor device includes multiple sub-arrays each including a TCAM cell array. Each sub-array searches the corresponding part of the input search data. Each sub-array outputs the search result indicative of a match for every entry without searching, when the corresponding first control signal is activated.

Abstract: A semiconductor memory device includes a plurality of memory blocks. The semiconductor memory device also includes a block decoder configured to output a block select signal for selecting at least one memory block of the plurality of memory blocks to at least one block word line of a plurality of word lines, and a connecting circuit including a plurality of pass transistors configured to electrically connect global lines to local lines of a plurality of memory cells included in the plurality of memory blocks in response to the block select signal. The semiconductor device may also include a control logic configured to apply a voltage pulse to global word lines and a ground voltage to global select lines of the global lines, and the voltage pulse to at least the one block word line while the semiconductor memory device is in a ready state.

Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected memory cell for programming, and a second voltage is applied to a non-selected memory cell. Before the second voltage rises to a predetermined voltage level, which is less than a program voltage level, the first voltage is greater than the second voltage or the second voltage is maintained at greater than a ground voltage level. Related non-volatile memory devices and memory systems are also discussed.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to initiate writing of first data to a first portion of a group of storage elements of the non-volatile memory. The controller is further configured to initiate writing of shaped dummy data to a second portion of the group of storage elements.

Abstract: A programming method of a nonvolatile memory device including; programming data in memory cells connected to a word line by performing a coarse program operation; and programming the data in the memory cells by performing a fine program operation, wherein the number of program states in the coarse program operation is changed according to a program/erase (P/E) cycle number.

Abstract: A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.

Abstract: A memory system includes: a memory device comprising a plurality of memory dies, each memory die including a plurality of planes, each plane including a plurality of memory blocks, each memory block including a plurality of pages, each page including a plurality of memory cells in which data is stored; and a controller suitable for, after a first time when the memory system in a power-on state performs a program operation corresponding to a write command received from a host, on first pages of the memory blocks, and records program information on the program operation in a list, in the case where power off occurs at a second time while the memory system performs a program operation on second pages of the memory blocks, checking the program information recorded in the list after the memory system is changed from a power-off state to the power-on state at a third time, and performing a recovery operation for the memory blocks for which a program operation was not completed due do the power off.

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N?1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.

Abstract: A method of erasing a non-volatile memory device which includes a plurality of NAND strings is provided as follows. A first voltage is applied to each of word lines for a corresponding effective erasing execution time. An erase operation is performed on memory cells connected to each of the word lines for the corresponding effective erasing execution time. A second voltage is applied to each of at least some word lines among the word lines for a corresponding erasing-prohibited time after the corresponding effective erasing execution time elapses. A sum of the corresponding effective erasing execution time and the corresponding erasing-prohibited time for each of the at least some word lines is substantially equal to an erasure interval during which an erase operation is performed using the first voltage and the second voltage higher than the first voltage. The word lines are stacked on a substrate.

Abstract: The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.

Abstract: A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.

Abstract: An integrated One-Time Programmable (OTP) memory to emulate an Multiple-Time Programmable (MTP) memory with a built-in program count tracking and block address mapping is disclosed. The integrated OTP memory has at least one non-volatile block register and count register to respectively store block sizes and program counts for different block/count configurations. The count register can be programmed before each round of programming occurs to indicate a new block for access. The integrated OTP memory also can generate a block address based on values from the count and block registers. By combining the block address with the lower bits of an input address, a final address can be generated and used to access different blocks (associated with different program counts) in the OTP memory to mimic an MTP memory.

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

Abstract: Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.

Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.

Abstract: The voltage applied to an integrated circuit is scaled so as to account for variations in the manufacturing processes, temperature, and the like, and to allow for power/performance optimization of the integrated circuit. The integrated circuit may characterized during a manufacturing test or anytime thereafter. The characterization data, which reflects the performance and power consumption of the integrated circuit, is used to determine an associated processing/speed bin, which in turn, defines the voltage that will be applied to the integrated circuit during normal operation. Optionally, a number of different supply voltages are applied to different circuit blocks disposed in the same integrated circuit. Each such circuit block may have a different characterization data associated with a different supply voltage.

Abstract: A system for programming integrated circuit (IC) dies formed on a wafer includes a magnetic field transmitter that outputs a digital test program as a magnetic signal. At least one digital magnetic sensor (e.g., Hall effect sensor) is formed with the IC dies on the wafer. The digital magnetic sensor detects and receives the magnetic signal. A processor formed on the wafer converts the magnetic signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The magnetic field transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the magnetic signal so that all of the IC dies are concurrently programmed with the digital test program.

Abstract: An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a first memory address of the array, a most stringent value of a sensing reference level at which correct data are read is identified. The remainder of the addresses of the array are evaluated in sequence, beginning at the value determined for the first address, and incrementally adjusting the sensing reference level for each, if necessary, until correct data are read at that address. The sensing reference level may be a reference current applied to a sense amplifier, against which read current from the addressed memory cell is compared, or may be control gate voltage applied to the control gate of a floating-gate transistor in the addressed memory cell.

Abstract: A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.

Abstract: A storage system is provided which includes: a storage device including a first memory, which may be nonvolatile memory, and a second memory, which may be a device memory, and configured to request a test on at least one of the first and second memories; and a host configured to test the at least one memory in response to the request for the memory test from the storage device and store the test result in the first memory or a third memory.

Abstract: A nonvolatile memory system includes a nonvolatile memory device including a distribution table suitable for storing recovery read level intervals that are set by being changed through multiple stages according to a distribution value of threshold voltage levels of a plurality of memory cells, measured at a reference read level, is changed through the multiple stages; and a memory controller suitable for reading measurement data from the memory cells by additionally using a measurement read level, searching for a difference value between the normal data and the measurement data from the multiple stages of distribution values stored in the distribution table, and recovering the normal data based on a recovery read level interval corresponding to a searched distribution value, when an error occurs in normal data read from the memory cells by using the reference read level.