Abstract: Techniques to back up data are disclosed. In various embodiments, a shadow copy of a source volume is created. An excluded file is deleted from the shadow copy. One or more blocks modified in the shadow copy in connection with deleting the excluded file from the shadow copy are tracked. An incremental backup is performed, the incremental backup includes determining one or more blocks to be backed up in connection with the incremental backup based at least in part on at least one of the tracked one or more blocks modified in the shadow copy and a merged bitmap corresponding to a merger of a first bitmap associated with the shadow copy and a second bitmap associated with the source volume.

Abstract: Determining a summary feature set is disclosed. A plurality of subsegments of a first segment are selected. For each subsegment, a plurality of values by applying a set of functions to each subsegment are computed. From all the values computed for all the subsegments, a first subset of values is selected.

Abstract: Techniques to back up data are disclosed. In various embodiments, a copy of a free block map as of a first time associated with a first backup is stored in persistent data storage. Writes made subsequent to the first backup to blocks not listed as free in the copy of the free block map as of the first time are tracked in a persistently-stored change block tracking log. A free block map as of a second time and the previously-stored copy of the free block map as of the first time are used to determine which blocks listed as free in the free block map as of the first time have been written to since the first time. At least a subset of blocks determined to have been written to since the first time are including in an incremental backup.

Abstract: According to certain aspects, a system includes a client device that includes a virtual machine (VM) executed by a hypervisor, a driver located within the hypervisor, and a data agent. The VM may include a virtual hard disk file and a change block bitmap file. The driver may intercept a first write operation generated by the VM to store data in a first sector, determine an identity of the first sector based on the intercepted write operation, determine an entry in the change block bitmap file that corresponds with the first sector, and modify the entry in the change block bitmap file to indicate that data in the first sector has changed. The data agent may generate an incremental backup of the VM based on the change block bitmap file in response to an instruction from a storage manager, where the incremental backup includes the data in the first sector.

Abstract: Systems and methods are disclosed for cross-system user-level management of data objects stored in one or more information management systems, and for user-level management of data storage quotas in information management systems, including data objects in secondary storage. An illustrative quota manager is associated with one or more information management systems. The quota manager comprises a quota value representing the maximum amount of data storage allowed for a given end-user's primary and secondary data in the one or more information management systems. The quota manager determines whether data associated with the end-user has exceeded the storage quota, and if so, prompts the end-user to select data for deletion, the deletion to be implemented globally, across the primary and secondary storage subsystems of the respective one or more information management systems. Meanwhile, so long as the quota is exceeded, the quota manager instructs storage managers to block backups of end-user's data.

Abstract: A resource allocation system begins with an ordered plan for matching requests to resources that is sorted by priority. The resource allocation system optimizes the plan by determining those requests in the plan that will fail if performed. The resource allocation system removes or defers the determined requests. In addition, when a request that is performed fails, the resource allocation system may remove requests that require similar resources from the plan. Moreover, when resources are released by a request, the resource allocation system may place the resources in a temporary holding area until the resource allocation returns to the top of the ordered plan so that lower priority requests that are lower in the plan do not take resources that are needed by waiting higher priority requests higher in the plan.

Abstract: A method of prioritizing data for recovery in a distributed storage system includes, for each stripe of a file having chunks, determining whether the stripe comprises high-availability chunks or low-availability chunks and determining an effective redundancy value for each stripe. The effective redundancy value is based on the chunks and any system domains associated with the corresponding stripe. The distributed storage system has a system hierarchy including system domains. Chunks of a stripe associated with a system domain in an active state are accessible, whereas chunks of a stripe associated with a system domain in an inactive state are inaccessible. The method also includes reconstructing substantially immediately inaccessible, high-availability chunks having an effective redundancy value less than a threshold effective redundancy value and reconstructing the inaccessible low-availability and other inaccessible high-availability chunks, after a threshold period of time.

Abstract: Techniques for backup and restore of optimized data streams are described. A chunk store includes each optimized data stream as a plurality of chunks including at least one data chunk and corresponding optimized stream metadata. The chunk store includes data chunks in a deduplicated manner. Optimized data streams stored in the chunk store are identified for backup. At least a portion of the chunk store is stored in backup storage according to an optimized backup technique, an un-optimized backup technique, an item level backup technique, or a data chunk identifier backup technique. Optimized data streams stored in the backup storage may be restored. A file reconstructor includes a callback module that generates calls to a restore application to request optimized stream metadata and any referenced data chunks from the backup storage. The file reconstructor reconstructs the data streams from the referenced data chunks.

Abstract: Transactional log data for a distributed database may be archived by a number of computing nodes scalable to a specified concurrency parameter. A log record may be mapped to a computing node for performance of an archiving operation. The log record may be stored with information indicative of a position, in a hierarchy of shards, of the shard from which the log record originated. The log record may be replayed in an order, relative to other records, that is based on the shard's position in the shard hierarchy. The log record may be replayed on a shard identified based on a time-invariant and idempotent hash function.

Abstract: An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for remapping of memory in memory control architectures. A processing device includes a processing core and a platform controller hub (PCH) coupled to the processing core. The PCH is to receive an indication of a failure associated with a first memory region of a plurality of memory regions residing in a memory. The PCH is also to interrupt an operating system to prompt for a reboot. Upon the reboot, the PCH is to remap a memory address range associated with the first memory region to a second memory region of the plurality of regions.

Abstract: A computing system having a plurality of computers connected via a computer network to form a computing entity. Each of the computers operates substantially independent of others. Each of the computers is configured to interrogate network infrastructure of the computer network to determine the identity of the computing entity when the computer is connected to the computer network and thus join the computing entity by announcing its presence in the computing entity. Each of the computers is configured to determine an identifier of the computer in the computing entity based on the connectivity configuration in the network infrastructure and assume a role to perform a portion of operations of a computing request directed to the computing entity over the computer network, based on the presence data of the computers in the entity.

Abstract: According to an example, a resiliency group for a memory node in a memory network can provide error correction for a memory access in the memory node. The memory access may be received from a main memory controller of a processor connected to the memory network. The memory access may be executed by a memory controller of the memory node.

Abstract: Implementations disclosed herein provide a method comprising iteratively reading data from a failing media sector prior to a an error minimization operation, analyzing read data at each iteration using an error minimization operation to determine sections of read data as good data, storing the good data in a buffer during each iteration, and using the good data as input for the read data during a subsequent error retry operation. In another implementation, the method further comprises comparing new read data with stored good data in the buffer, and replacing the stored good data with the new read data if the new read data has a higher quality than the stored good data.

Abstract: A new test control structure improves on constructing complex test sequences in a scripting language. The new test control structure iterates over two or more arbitrary values of a test attribute, such as a networking protocol parameter applied at OSI layers 2-7.

Abstract: An apparatus and method of connecting an external device are provided. The method includes connecting the apparatus to the external device when a distance between the external device and the apparatus is less than a reference range; after the external device is connected to the apparatus, continuously maintaining the connection when a distance between the external device and the apparatus is greater than the reference range; and disconnecting the external device from the apparatus when a distance between the external device and the apparatus is greater than a detectable range.

Abstract: Embodiments of the claimed subject matter are directed to methods and systems that allow tracking and accounting of wear and other aging effects in integrated circuits and products which include integrated circuits over time, and the dynamic adjustment of operating conditions to increase or decrease wear in response to the accumulated wear relative to the expected wear during the lifetime of the circuit and/or product.

Abstract: Embodiments of the present invention provide a method, system and computer program product for concurrent workload simulation for application performance testing. In an embodiment of the invention, a method for concurrent workload simulation for application performance testing is provided. The method includes loading a list of recorded workloads for different tasks of a computing application under test in a workload simulator executing in memory by at least one processor of a host computer. The method also includes grouping the recorded workloads by common task in a corresponding block. Finally, the method includes generating loads for simulating performance of the computing application under test from the grouped workloads so as to require serial execution of workloads in a common block in order of appearance in the common block, but to allow concurrent execution of workloads in different blocks.

Abstract: Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed.

Abstract: One or more problems may be detected in an executing application by retrieving runtime execution information from the application executing on one or more computers. The runtime information is transformed into a temporal sequence of events. A knowledgebase is searched for a dialog that has nodes in an order that match the temporal sequence of events according to a threshold degree. Responsive to finding the dialog in the knowledgebase, the dialog is launched on a user interface to interact with a user and guide the user through a problem identification and solution. Responsive to not finding the dialog, additional instrumenter is enabled in the application.

Abstract: Dynamically identifying performance anti-patterns in a software system is based on a set of documented symptoms that are evaluated in real-time. The evaluation is based on the observed system behavior and its comparison against the documented symptoms of different types of performance issues.

Abstract: The present disclosure describes methods, systems, and computer program products for debugging structured query language (SQL) statements.

Abstract: In some aspects, a debugging application can obtain log data from a target device. The log data can be generated from the execution of object code by the target device. The object code can be generated from assembly code for the target device. For each of multiple program counter entries in the log data, the debugging application can identify a correspondence between the program counter entry and a respective portion of the assembly code and simulate a respective operation performed by the execution of the object code. The simulated operation corresponds to the program counter entry. Simulating the execution can include configuring a display device to display a visual indicator for the portion of the assembly code that caused a given operation. The visual indicator is displayed based on the identified correspondence between a portion of the assembly code and a program counter entry from the log data.

Abstract: The present disclosure describes testing resiliency plans for applications on alternate hosts within production environments instead of simulated environments. Embodiments herein disclose determining resiliency components for an application being tested and determining related resiliency components from related applications. Embodiments herein further disclose determining one or more dependencies between a first resiliency component and both the resiliency components from the application being tested and related applications. Furthermore, mapping resiliency component dependencies between the resiliency components of the application and with the related resiliency components is disclosed. Finally, the first resiliency component and the related resiliency components are moved from a home host location to an alternate host location for a period of time in a real production environment.

Abstract: A method (and system) for trace recovery includes retrieving a code listing from a memory and performing a static analysis on the retrieved code listing. Based on the static analysis, profiling instructions are inserted in the code.

Abstract: In one embodiment, a system for program lifecycle testing includes receiving a request to test a program update at an interface. Using a processor, the system may then execute a validation test associated with the program update, wherein the validation test is conducted in a testing environment comprising a plurality of testing environment systems. The system may then use the processor to capture a current state of the testing environment at a start of the validation test, and confirm that the plurality of testing environment systems are operating according to the validation test. The system may then use the interface to receive testing results from the validation test and compare the testing results to previous test results from a prior program update. The system may then store the validation test results, the current state of the testing environment, and a name of the program update, in a performance database.

Abstract: An apparatus includes a non-volatile storage medium and a processing circuit. The non-volatile storage medium stores code implementing an application program. The processing circuit may be configured to load and execute the code implementing the application program. At least a portion of the code implementing the application program is modified by the processing circuit to inject random errors in responses to requests from at least one calling program while an original definition of a functionality of the modified portion of the code implementing the application program remains unaltered. A particular random error injected is determined in response to configuration information received from a user.

Abstract: This disclosure relates generally to software performance testing, and more particularly to a system and method for steady state performance testing of a multiple output software system. According to one exemplary embodiment, a processor-implemented performance test for steady-state determination method is described. The method may include executing, via one or more hardware processors, a performance test of a web-based application, calculating, via the one or more hardware processors, a plurality of output metrics based on the performance test, determining, via the one or more hardware processors, whether each of the output metrics has achieved steady state within micro, macro, and global initial time windows, and providing an overall steadiness indication based on the determination of whether each of the output metrics has achieved steady state within the micro, macro, and global time windows.

Abstract: In response to a test case error generated by execution of a test case against a code build, a source code segment that caused the test case error is identified by a defect monitor. The identified source code segment is linked to the test case that generated the test case error. The linked source code segment is monitored for code changes. A determination is made as to whether a test case re-execution criterion associated with the test case has been satisfied based upon a detected code change of the linked source code segment. An indication to re-execute the test case is generated in response to determining that the test case re-execution criterion associated with the test case has been satisfied.

Abstract: Methods and apparatus for dynamically resizing circular buffers are described wherein circular buffers are dynamically allocated arrays from a pool of arrays. The method comprises receiving either a request to add data to a circular buffer or to remove data from a circular buffer. If the request is an addition request and the circular buffer is full, an array from the pool is allocated to the circular buffer. If, however, the request is a removal request and removal of the data creates an empty array, an array is de-allocated from the circular buffer and returned to the pool. Any arrays that are not allocated to a circular buffer may be disabled to conserve power.

Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.

Abstract: A leak detection system may be configured to receive a plurality of memory use reports periodically from a user device. The memory use reports may include an indication of memory that may be used and/or allocated by/to a particular process, such as a process that may currently be running on the user device. The memory use report may further provide a relatively granular view of the allocation of memory associated with the process, such as by type of memory and/or category of memory associated with the process. The leak detection system may use the plurality of memory use reports to generate a memory profile associated with the process and particular memory types and/or categories of memory allocation. By analyzing the memory profiles, the leak detection system may be configured to identify a memory leak associated with the process on the user device.

Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.

Abstract: Systems, methods and/or devices are used to enable enhancing data integrity to protect against returning old versions of data. In one aspect, the method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses in a logical address space of the host, (2) mapping the set of logical block addresses to a set of physical addresses corresponding to physical pages of the storage device, and (3) performing one or more operations for each logical block specified by the set of logical block addresses, including: (a) generating metadata for the logical block, the metadata including a version number for the logical block, (b) storing the metadata, including the version number, in a header of a physical page in which the logical block is stored, and (c) storing the version number in a version data structure.

Abstract: This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Abstract: Systems and methods for coherency maintenance are presented. The systems and methods include utilization of multiple information state tracking approaches or protocols at different memory or storage levels. In one embodiment, a first coherency maintenance approach (e.g., similar to a MESI protocol, etc.) can be implemented at one storage level while a second coherency maintenance approach (e.g., similar to a MOESI protocol, etc.) can be implemented at another storage level. Information at a particular storage level or tier can be tracked by a set of local state indications and a set of essence state indications. The essence state indication can be tracked “externally” from a storage layer or tier directory (e.g., in a directory of another cache level, in a hub between cache levels, etc.). One storage level can control operations based upon the local state indications and another storage level can control operations based in least in part upon an essence state indication.

Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Abstract: A method and an apparatus for processing data and a computer system are provided. The method includes copying a shared virtual memory page to which a first process requests access into off-chip memory of a computing node, and using the shared virtual memory page copied into the off-chip memory as a working page of the first process; and before the first process performs a write operation on the working page, creating, in on-chip memory of the computing node, a backup page of the working page, so as to back up original data of the working page. Before a write operation is performed on a working page, page data is backed up in the on-chip memory, so as to ensure data consistency when multiple processes perform an operation on a shared virtual memory page while accessing off-chip memory as less as possible and improving a speed of a program.

Abstract: Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors is disclosed. In one aspect, a block-based computer processor provides a merging logic circuit communicatively coupled to an unordered store queue and cache memory. The merging logic circuit is configured to select a first store queue entry in the unordered store queue, and read its memory address, an age indicator, and a data value. The age indicator and the data value are stored in merged data bytes within a merged data buffer. The merging logic circuit then locates a remaining store queue entry having a memory address identical to the first selected store queue entry, and reads its age indicator and data value. Based on the age indicator and one or more age indicators of the merged data bytes within the merged data buffer, the data value is merged into the merged data buffer.

Abstract: Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

Abstract: In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting, in the instruction sequence, a barrier instruction that precedes the store instruction in program order and that includes a field set to indicate the store operation should be accorded high priority and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract: A device includes, a memory, and, a processor coupled to the memory, including a cache memory, and configured, to hold a memory access instruction for executing an access to the memory and a prefetch instruction for executing a prefetch to the memory, to determine whether or not data which is a subject data of the memory access instruction is held in the cache memory, and when the data is held in the cache memory and when a corresponding prefetch instruction that is a prefetch instruction corresponding to the memory access instruction is held in the processor, not to execute an execution of the corresponding prefetch instruction.

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

Abstract: A de-duplication is configured to cache data for access by a plurality of different storage clients, such as virtual machines. A virtual machine may comprise a virtual machine de-duplication module configured to identify data for admission into the de-duplication cache. Data admitted into the de-duplication cache may be accessible by two or more storage clients. Metadata pertaining to the contents of the de-duplication cache may be persisted and/or transferred with respective storage clients such that the storage clients may access the contents of the de-duplication cache after rebooting, being power cycled, and/or being transferred between hosts.

Abstract: Various embodiments are generally directed to instrumenting an interrupt service routine. A non-executable address may be provisioned and added to an execution stack to cause a page fault on a known address after execution of an interrupt service routine. The page fault on the known address can be used to trigger instrumentation operations and also to return to the interrupted process.

Abstract: Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and processing the instruction packet. The instruction packet may include one or more instructions for obtaining a block of virtual memory for use in an emulated operating environment from a slab of virtual memory in a host environment, maintaining a mapping between the block of virtual memory and physical memory when the block is returned to the host environment, and for filling the block of virtual memory with zeros and a pattern based, at least in part, on a detected fill type.

Abstract: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.

Abstract: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.

Abstract: A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage space includes a plurality of buffer entries; providing a second storage space, wherein the second storage space includes a plurality of translation entries, and the translation entries correspond to a plurality of translation indices; and when receiving a write instruction to write a first virtual-to-physical address translation into a specific buffer entry of the buffer entries, storing the first virtual-to-physical address translation in a write translation entry of the translation entries according to a first part of bits of a first virtual address corresponding to the first virtual-to-physical address translation, and storing the first virtual address and a write translation index corresponding to the write translation entry in the specific buffer entry.