Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.

Abstract: An information processing system comprising a storage device and an information processing device, wherein the information processing device includes a data holding unit which holds first data, a first detection unit which detects a first state of access, and a transmission unit which transmits the first state of access detected by the first detection unit to the storage device, and the storage device includes a storage unit which stores second data, a reception unit which receives the first state of access transmitted from the transmission unit, a second detection unit which detects a second state of access, which is a state of access to the second data, and a control unit which rearranges the second data in the storage unit on the basis of the states of access.

Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.

Abstract: An apparatus and system are disclosed for a storage area network (“SAN”). In one embodiment, a computer system includes an internal storage device and an internal storage controller. In this embodiment, the internal storage controller is configured to implement a SAN that includes at least the internal storage device and a storage device external to the computer system. In this embodiment, the internal storage controller is further configured to service a storage request received from a client that involves data stored by the internal storage device. In this embodiment, the internal storage controller is configured to communicate with the external storage device via a network.

Abstract: A cache apparatus stores part of a plurality of accessible data blocks into a cache area. A calculation part calculates, for each pair of data blocks of the plurality of data blocks, an expected value of the number of accesses made after one of the data blocks is accessed until the other of the data blocks is accessed, on the basis of a probability that when each of the plurality of data blocks is accessed, each data block that is likely to be accessed next is accessed next. When a data block is read from outside the cache area, a determination part determines a data block to be discarded from the cache area, on the basis of the expected value of the number of accesses made after the read data block is accessed until each of the plurality of data blocks is accessed.

Abstract: A memory device includes: a main block that includes a plurality of first pages that are accessible based on a multi-bit address; and a sub-block that includes a plurality of second pages that are accessible based on a portion of bits of the multi-bit address, and stores a replacement data for replacing entire or a portion of the data of an accessed first page among the plurality of the first pages in a second page that stores the same tags as the other bits of the multi-bit address among the accessed second pages.

Abstract: Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.

Abstract: In an aspect of the present disclosure, a method is disclosed including receiving first transaction data from a first trusted party that includes a first pending transaction between the first trusted party and a second trusted party and a second pending transaction between the first trusted party and an un-trusted party. The method further includes receiving second transaction data from the second trusted party that includes a third pending transaction between the second trusted party and the un-trusted party. The method further includes analyzing the first and second transaction data to determine whether more than one trusted party has a pending transaction with the same un-trusted party, determining that the first trusted party and the second trusted party each have a pending transaction with the un-trusted party, and modifying the first pending transaction, the second pending transaction, and the third pending transaction. The modification includes removing the third pending transaction.

Abstract: Systems and methods for guest page table validation by virtual machine (VM) functions. An example method comprises: storing a first VM function invocation instruction in a first memory page executable from a default memory view of a VM, wherein executing the first VM function invocation instruction switches a page table pointer to a trampoline memory view of the VM; configuring a write access permission, from the trampoline memory view, to a page table comprised by a VM page table hierarchy; storing a second VM function invocation instruction in a second memory page executable from the trampoline memory view, wherein executing the second VM function invocation instruction switches the page table pointer to an alternative memory view of the VM; storing, in the second memory page, validation instructions to validate the VM page table hierarchy; and storing protected instructions within a third memory page executable from the alternative memory view.

Abstract: The present application relates to a heap sorting method based on arrangement and apparatus which can improve the heap sorting conducting speed through reducing access (I/O) frequency of the external memory when conducting heap sorting through storing binary data in the basic access unit of the external memory device in reference to the subtree unit.

Abstract: Embodiments include method, systems and computer program products for a parallel ordering queue using an encoded command type. In some embodiments, a command may be receive from a receiver of a first bus, wherein the command is to be sent to a second bus. The command may be decoded. The command may be associated with an encoded command type. The command may be placed in an ordering queue. A first entry of a second queue may be popped based on the encoded command type of the first entry of the ordering queue. The first entry of the ordering queue may be removed from the ordering queue.

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

Abstract: Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write transactions. A common set of control signal lines from the controller communicates the same command and address signals to the modules. For write commands, the controller sends subsets of write data to each module over a respective subset of data lines. For read commands, each module responds with a subset of the requested data over the respective subset of data lines. The memory modules can be width configurable so that a single full-width module can connect to both subsets of data lines to convey full-width data, or two half-width modules can connect one each to the subsets of data lines.

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract: In some embodiments, an apparatus includes a processor that is configured to execute computer usable program code to perform operations. The operations include executing an atomic transaction in a system having a transactional memory. The operations include receiving a signal interrupt during executing of the atomic transaction. The operations include storing a state of the signal interrupt to enable subsequent execution of the signal interrupt. The operations include returning to executing the atomic transaction until the atomic transaction is at least one of completed and aborted. The operations include after executing the atomic transaction is at least one of completed and aborted, determining whether the signal interrupt is received during executing of the atomic transaction. The operations include after determining that the signal interrupt is received during executing of the atomic transaction, retrieving the state of the signal interrupt.

Abstract: In some embodiments, a method includes executing an atomic transaction in a system having a transactional memory. The method includes receiving a signal interrupt during executing of the atomic transaction. The method includes storing a state of the signal interrupt to enable subsequent execution of the signal interrupt. The method includes returning to executing the atomic transaction until the atomic transaction is at least one of completed and aborted. The method includes after executing the atomic transaction is at least one of completed and aborted, determining whether the signal interrupt is received during executing of the atomic transaction. The method includes after determining that the signal interrupt is received during executing of the atomic transaction, retrieving the state of the signal interrupt. The method includes executing an interrupt handler for processing the signal interrupt and returning from executing of the atomic transaction.

Abstract: Systems and methods are provided for expanding the available memory of a storage controller. The systems and methods utilize a PCIe memory controller connected to the backend interface of the storage controller. Memory of the PCIe memory controller is memory mapped to controller memory of the storage controller. The PCIe connection allows the storage controller to access the memory of the PCIe memory controller with latencies similar to that of the controller memory.

Abstract: A method for reading data from a persistent storage module (“PSM”) in a communication fabric is discussed. A read request may be submitted to a PSM via a processor. In response, the requested data may be written to the client. A read complete may follow the same path as the data through the communication fabric.

Abstract: A system includes a host device, an external bus and a storage device. A driver is installed in the host device. The external bus is connected with the host device. The external bus supports a communication protocol. The storage device includes a controlling circuit and a non-volatile memory. After the storage device issues a request to the host device according to the communication protocol, a reserved space is created in a host memory of the host device in response to the request, and a device information from the storage device is stored into the reserved space. While the host device issues a first command to operate the storage device, the first command is converted into a second command by the driver according to the device information, and then the second command is transmitted to the storage device.

Abstract: A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

Abstract: Described examples include USB controllers and methods of interfacing a host processor with one or more USB ports with the host processor implementing an upper protocol layer and a policy engine for negotiating USB power delivery parameters, in which the USB controller includes a logic circuit implementing a lower protocol layer to provide automatic outgoing data transmission retries independent of the upper protocol layer of the host processor. The controller logic circuit further implements automatic incoming data packet validity verification and acknowledgment independent of the upper protocol layer of the host processor.

Abstract: A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation.

Abstract: A WiFi serial bus (WSB) attribute for use in Wi-Fi Alliance defined point-to-point (P2P) discovery mechanism includes a plurality of fields disposed in the frame. The WiFi serial bus attribute is arranged to provide information in the plurality of fields to support connectivity decisions for a USB device in a point-to-point network using a WSB protocol. The WSB attribute includes WSB architectural element information and information associated with a USB device behind a USB protocol adaptation layer (PAL).

Abstract: A method for effectively transmitting data, in which a switch is connected between a plurality host and storage, comprises steps of the following. First, the hosts recognize the storages via the switch, and revise a data transmission path within an original command, meanwhile transforming it into a specific command. Later, the switch receives the specific command, alternatively revises the data transmission path or not, and transforms the specific command into a standard command. The standard command is then transmitted to the storage. After receiving it, the storage is able to search for a corresponding host based on the data transmission path such that data is simply transmitted between the storage and its corresponding host. By employing the proposed method, the present invention is beneficial to reducing system complexity and raising data transmission efficiency.

Abstract: Methods and systems are provided routing access requests produced by a function to a physical sharing machine on a computer interconnect fabric. Access requests are routed through a switch that includes an NTB, the NTB using an address-lookup table to ensure that access requests made by multiple physical sharing machines are appropriately isolated from one another.

Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.

Abstract: A remote access appliance is disclosed which provides electronic display identification data (EDID) information associated with a monitor which is communicating with the appliance, to any one of a plurality of remote computers in communication with the appliance, without requiring rebooting of a selected one of the remote computers. A plurality of multiplexers is controlled by a controller for interfacing a selected one of the computers to a display data channel (DDC) interface associated with the monitor. Memory devices are accessible by each of the computers and by the controller which store the EDID information. The controller controls the multiplexers so that any selected one of the computers can communicate with the monitor, and can access an associated one of the memory devices to obtain the stored EDID information, or such that the EDID information can be loaded into each of the memory devices.

Abstract: The present invention relates to the prevention of bus conflicts in the backplane by providing a bus structure which is configured to control the activation of an attached slave board in the backplane to/from which a plurality of slave boards are attached and detached. The backplane according to the present invention can prevent data bus conflicts and improve the stability of a corresponding system by configuring general purpose I/O (GPIO) pins in a 2 bit request/grant scheme between a master board and the plurality of slave boards. Accordingly, the present invention can improve system reliability, maintainability, and competitiveness in various fields such as the fields of communication devices and server devices, remote monitors and control systems, vessel communications, aircraft communications, and wired and wireless communications in which various protocols are combined and implemented.

Abstract: A standardized hot-pluggable transceiving unit comprising a housing, a connector and a processing unit. The housing has specific standardized dimensions and can be inserted into a chassis of a hosting unit. The connector receives an IP flow. The processing unit processes packets of the IP flow based on a control plane message. The control plane message is received by the connector receiving the IP flow or by another connector of the transceiving unit. The processing unit may further generate a report or an alarm related to the IP flow, for transmission by the transceiving unit. The IP flow may for example transport a video payload. A system comprising a chassis and the transceiving unit is also disclosed. The chassis comprises a processing unit capable of processing packets of IP flows. The transceiving unit is inserted into the chassis and exchanges data with the processing unit of the chassis.

Abstract: A firmware updating method in just a bunch of disks includes the following blocks. A motherboard is coupled to a first primary storage extension chip or to a second primary storage extension chip. The first primary storage extension chip and the second primary storage extension chip are coupled to each other. At least one secondary storage extension chip is coupled to the first primary storage extension chip. At least one secondary storage extension chip is coupled to the second primary storage extension chip. A signal sent to the first primary storage extension chip or to the second primary storage extension chip by the motherboard causes firmware of each storage extension chip to be updated.

Abstract: A control method applied to an Operating-Mode Finite-State-Machine (OPFSM) arranged for deciding a behavior of a first port of an apparatus includes: controlling the OPFSM to enter a second local state from a first local state and controlling the first port to send a signal with a wakeup pattern to a link partner of the first port when the state of the OPFSM is the first local state, and a wakeup request bit is a first local value.

Abstract: The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: The present invention provides integrated circuit and apparatus having USB connector; the integrated circuit includes a signaling circuit and an interface for relaying signal between the USB connector and the signaling circuit, wherein an interconnect scheme of the signaling circuit is different from USB interconnect defined by USB specification; for example, a frequency adopted for signaling can be programmable, be lower than wireless band and/or be different from a frequency of USB SuperSpeed interconnect.

Abstract: A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.

Abstract: In one example, a host device may identify a serial device connected to the host device to determine a host action. The host device may receive a serial device signal with a child serial device identifier from a serial device bridge. The host device may identify a child serial device based on the child serial device identifier. The host device may execute a host action based on the child serial device.

Abstract: The present tool and method relate to device fault detection, diagnosis and prognosis. More particularly, the present tool and method store in a database a plurality of measured indicators representative of at least one dynamic condition of the device. The present tool and method further binarize by a processor the plurality of measured indicators, and analyze the plurality of binarized measured indicators using a machine learning data tool for extracting at least one pattern from the binarized measured indicators by adding at least one different constraint to each iteration. The at least one extracted pattern is indicative of whether the device has a fault or not.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: A system and method which uses pattern recognition in assessing or monitoring a vehicle status and/or an operator's driving behavior. A vehicle, for use by an operator or driver, can be equipped with a data collection and assessment system. The system can comprise one or more data collection devices, e.g., accelerometers, which can be used to capture data and information, or otherwise measure vehicle actions. A pattern recognition module is configured with one or more defined operating patterns, each of which operating patterns reflects either a known change in vehicle status corresponding to, e.g., when a passenger has embarked or disembarked the vehicle, or a known vehicle operating or driving behavior. Information collected as events describing a current vehicle status or a current driving behavior can be compared with the known operating patterns.

Abstract: Systems, methods, apparatus, and techniques are presented for maintaining cupolets in a state of mutual stabilization. A first cupolet and a second cupolet are generated. A first control code is applied to the first cupolet for a first time to produce a first visitation code. The first visitation code is transformed based on an exchange function to produce a second control code. The second control code is applied to the second cupolet to produce a second visitation code. The second visitation code is transformed based on the exchange function to produce the first control code. The first control code is applied to the first cupolet for a second time.

Abstract: In general, techniques are described for implementing a 32-point discrete cosine transform (DCT) that is capable of applying multiple DCTs of different sizes. For example, an apparatus comprising a 32-point discrete cosine transform of type II (DCT-II) unit may implement the techniques of this disclosure. The 32-point DCT-II unit performs these DCTs-II of different sizes to transform data from a spatial to a frequency domain. The 32-point DCT-II unit includes an 16-point DCT-II unit that performs one of the DCTs-II of size 16 and at least one 8-point DCT-II unit that performs one of the DCTs-II of size 8. The 16-point DCT-II unit includes another 8-point DCT-II unit. The 16-point DCT-II unit also comprises at least one 4-point DCTs-II unit. Two or more of these DCTs-II units may concurrently perform DCTs-II of different sizes to various portions of the content data.

Abstract: Systems and methods for forecasting a time series data are disclosed. The methods include receiving a historical time-series data including a series data and a non-stationary series data. The historical time-series data is processed to obtain a unified time series data. On the unified time series data, a data distribution is plotted and the data distribution is validated based upon a rate function associated with a Large Deviation Theory (LDT). The unified time series data is split validated into vectors based on autocorrelation function (ACF). The unified time series data is further validated. A mixture of Gaussian distribution models is applied and weights are assigned to each of the Gaussian distribution model. By controlling the weights based upon various what-if scenarios, a resultant Gaussian time series data is generated. The resultant Gaussian time series data indicates forecasted time series data of the historical time series data.

Abstract: A computer implemented system for genomic data sorting, comprising alignment and position mapping. The system maps each read to a position on the reference genome with which the read is associated, followed by sorting these reads by their mapped positions.

Abstract: A method providing an analytical technique introducing label information into an anomaly detection model. The method includes the steps of: inputting measurement data having an anomalous or normal label and measurement data having no label as samples; determining a similarity matrix indicating the relationship between the samples based on the samples; defining a penalty based on the similarity matrix and calculating parameters in accordance with an updating equation having a term reducing the penalty; and calculating a degree of anomaly based on the calculated parameters. The present invention also provides a program and system for detecting an anomaly based on measurement data.

Abstract: This disclosure describes systems, methods, and computer-readable media related to contextual anchor points in content. In some embodiments, processed content may be received from a server. Contextual anchor parameters may be received from a user. A selection of an anchor target in the processed content may be received from a user. One or more contextual anchor candidates may be identified in the processed content based at least in part on the anchor target and the one or more contextual anchor parameters. The one or more contextual anchor candidates and at least a portion of the processed content may be displayed to the user. A selection of at least one contextual anchor from the one or more contextual anchor candidates may be received from the user. An association may be established between the anchor target and the contextual anchor. The processed content, anchor target, and the association may be transmitted.

Abstract: Architecture that facilitates language conversion and previewing of a message attachment in multiple different languages. The architecture can be employed in a messaging application or a personal information manager program, for example, such that the message attachment can be selected and designated for conversion into a different language, and then previewed in the different language. For example, a first language can be simplified Chinese and a second language can be traditional Chinese, such that the user can toggle the preview to view the attachment in the simplified or traditional Chinese languages. The attachment can be a word processing document, a spreadsheet document, a presentation document for the presentation of information, and/or a web feed document. Additionally, the attachment can be one of multiple attachments to the message that is selected by the user.

Abstract: Adjusting the layout size of a hyperlink includes displaying at least one hyperlink in a user interface; detecting a touch operation for the at least one hyperlink, and extracting position coordinates of a touch point formed by the touch operation on the user interface. Adjusting the layout size further includes determining a target hyperlink from the at least one hyperlink, and determining the precision of the touch operation with respect to the target hyperlink based on the position coordinates of the touch point; and adjusting layout size of the target hyperlink based on the determined precision. The hyperlink layout in a web page can be adapted to the touch precision of user's finger automatically, which facilitates the recognition of hyperlinks by the user's finger.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for content evaluation. In one aspect, a method includes identifying a first document object model for a resource, the first document object model being associated with a performance profile, the performance profile specifying performance factors for content item presentation positions of the resource. A first similarity measure can be computed for first document object model based on the first document object model and a second document object model for the resource, the second document object model for the resource being a previous document object model for the resource. A new performance profile can be computed for the resource if the first similarity measure does not meet a similarity threshold.