Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated.

Abstract: Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The tread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. A set of mailbox registers can be allocated to each thread of a plurality of threads that can be executed in the microprocessor. A mailbox register in the set of mailbox registers comprises an identifier of a next thread of the plurality of threads to which an active thread switches based on a thread switch condition further indicated in the mailbox register. The auxiliary registers in the microprocessor can be used to configure a number of threads for simultaneous execution in the microprocessor, a priority for thread switching, and to store a program counter of each thread and states of registers of each thread.

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

Abstract: Certain embodiments of the present disclosure support a method and apparatus for efficient multithreading on a single core microprocessor. Thread switching in the single core microprocessor presented herein is based on a reserved space in a memory allocated to each thread for storing and restoring of registers in a register file. The thread switching is achieved without full save and restore of the register file, and only those registers referenced in the memory are saved and restored during thread switching.

Abstract: Techniques are disclosed for receiving an instruction for processing data that includes a plurality of sectors. A method includes decoding the instruction to determine which of the plurality of sectors are needed to process the instruction and fetching at least one of the plurality of sectors from memory. The method includes determining whether each sector that is needed to process the instruction has been fetched. If all sectors needed to process the instruction have been fetched, the method includes transmitting a sector valid signal and processing the instruction. If all sectors needed to process the instruction have not been fetched, the method includes blocking a data valid signal from being transmitted, fetching an additional one or more of the plurality of sectors until all sectors needed to process the instruction have been fetched, transmitting a sector valid signal, and reissuing and processing the instruction using the fetched sectors.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and an instruction sequencing unit. Operation of such a multi-slice processor includes: receiving, at the instruction sequencing unit, a load instruction indicating load address data and a load data length; determining a previous store instruction in an issue queue such that store address data for the previous store instruction corresponds to the load address data, wherein the previous store instruction corresponds to a store data length; and generating, in dependence upon the store data length matching the load data length, an indication in the issue queue that indicates a dependency between the load instruction and the previous store instruction.

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Abstract: A method and an apparatus for allocating a hardware acceleration instruction to a memory controller to balance load of memory controllers, where the method includes, after dividing a plurality of hardware acceleration instructions into different instruction sets according to dependency relationships among the plurality of hardware acceleration instructions, a first mapping relationship between the instruction sets and memory controllers in a computer system is obtained according to a rule that different instruction sets whose hardware acceleration instructions do not have a dependency relationship are allocated to different memory controllers.

Abstract: A system for discovering new backup clients is disclosed. The system comprises an input interface and a processor. The input interface is configured to receive a notice from a backup client. The processor is configured to provide an indication of the notice and select a configuration mode from a set of available configuration modes.

Abstract: An apparatus, method, and program product are disclosed for loading a program during boot of a device. A monitor module collects usage data for each of one or more programs executing on a device. The usage data for each program comprising an amount of time that the program was used and a schedule of when the program was used. A priority module assigns a boot priority to each of the one or more programs based on the amount of time that each program was used. A boot module selects one or more programs to load during a boot period for the device based on each program's usage schedule. The one or more selected programs are loaded according to each selected program's boot priority.

Abstract: Exemplary embodiments provide method and apparatus for deploying new systems agilely without preventing stable operation of existing IT systems. In one embodiment, a management computer is coupled to a first system. The management computer includes a memory and a processor. The processor is configured, in receipt of a request to deploy a second system which will issue an access to the first system, to create a constraint which limits the access to the first system issued by the second system, and deploy the second system, to which the created constraint is set, to operate the second system with the created constraint.

Abstract: The application relates to a multi-operating system (multi-OS) device and a notification device. The multi-OS device comprises a processor, a transceiver, and an output device. The processor is configured to host a first operating system (OS1) in a foreground and a second operating system (OS2) in a background, or vice versa. The output device is configured to be controlled by an operating system hosted in the foreground. The transceiver is configured to receive a first signal (S1) from a notification device over a communication system, where the S1 indicates a notification associated to the OS2. The output device is further configured to output the notification associated to the OS2 when the OS1 is hosted in the foreground.

Abstract: Techniques facilitating synchronization of processing engines for parallel deep learning are provided. In one example, a first processing component associated with a processor and processing components can: generate first output data based on input data associated with a machine learning process, wherein the processing components are communicatively coupled with an assignment component via a network; transmit the first output data to a second processing component of the processing components, wherein the first processing component and the second processing component comprise a first group of the processing components and the first group of the processing components is determined by the assignment component based on a first defined criterion; receive communication data generated by the second processing component; and generate second output data based on the communication data, wherein the second output data is an updated version of the first output data stored in the memory of the first processing component.

Abstract: The present disclosure provides an information processing method and an electronic apparatus thereof. The method includes using a first electronic apparatus to receive data displayed via a second electronic apparatus for a corresponding display via the first electronic apparatus; providing a status identifier to control the corresponding display of the data as received from the second electronic apparatus; and displaying the status identifier via the first electronic apparatus.

Abstract: Techniques are described herein for leveraging information about a user to enable a personal assistant module to make various inferences about what actions that may be responsive to a user declaration. In various implementations, upon identifying a user declaration received at a computing device, a plurality of candidate responsive actions that can be initiated by the computing device in response to the user declaration may be identified. A single candidate responsive action may then be non-deterministically (e.g., randomly, stochastically) selected to be exclusively initiated on the computing device in response to the user declaration.

Abstract: When an application is booted, a font that will be used with the application is identified and it is determined whether the identified font it locally available to the device. If not, a request to a remote font service is automatically generated, and the identified font is downloaded based upon the detected application boot. The device then finishes booting the application.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: A method to deploy a multitier application in a virtualized computing environment includes receiving an open virtualization format (OVF) package. The OVF package includes an OVF descriptor, one or more virtual disk image files of virtual machines, and a multitier application blueprint specifying software components on the virtual machines and dependencies of the software components. The method further includes deploying the virtual machines based on the OVF package and executing the multitier application blueprint by deploying the software components on the virtual machines pursuant to the dependencies of the software components.

Abstract: Examples include provision of a hypervisor manager native API call from an API gateway to a hypervisor manager. Some examples include determination, with the API gateway and based on at least one restriction not enforced by the hypervisor manager, whether a requesting entity associated with the hypervisor manager native API call is authorized to cause an action that is requested in the hypervisor manager native API call. Such examples may involve provision of the hypervisor manager native API call from the API gateway to the hypervisor manager in response to a determination that the action is authorized.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for changing virtual machine user interfaces. One of the methods includes receiving a first request from a first client device to initiate a first remote session, detecting, for the first remote session, a first display property of the first client device in response to receiving the first request, configuring, for the first remote session, a virtual display device for the virtual machine to be a display device having the first display property, receiving a second request from a second client device to initiate a second remote session, detecting, for the second remote session, a second display property of the second client device in response to receiving the second request, and configuring, for the second remote session, the virtual display device for the virtual machine to be a display device having the second display property.

Abstract: An adaptive virtual desktop architecture is provided. Application install or assignment is evaluated, such as by using heuristics to identify applications that may present compatibility problems. Upon determining that a newly installed application may have compatibility problems when associated with a non-persistent virtual desktop, a promotion to a persistent virtual desktop occurs.

Abstract: Embodiments of the present invention disclose an application interaction method and apparatus, and a terminal. The application interaction method includes: receiving application invitation information sent by a target application running in a first terminal, where the application invitation information carries application interaction information of the target application; detecting, according to the application interaction information, whether a currently triggered interactive application and the target application are a same application. If the interactive application and the target application are different applications, sending a notification message to an interaction application, corresponding to the application interaction information, in a preset storage area according to the application invitation information, so that the interaction application establishes a session connection to the target application according to the notification message.

Abstract: The described technology provides a system and method for sequential execution of one or more operation segments in an asynchronous event driven architecture. One or more operation segments may be associated and grouped into an activity of operation segments. The operation segments of an activity may be sequentially executed based on a queue structure of references to operation segments stored in a context memory associated with the activity. Any initiated operation segment may be placed on the queue structure upon completion of an associated I/O action.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: A non-repudiable transaction protocol system includes a memory, at least one processor in communication with the memory, an operating system executing on the at least one processor, a resource manager configured to manage a storage system, and a transaction manager. The transaction manager is configured to provide NRO-W evidence of a work request from a client to the resource manager and provide NRR-W evidence to the client that the resource manager has completed initial work for the work request. Additionally, the transaction manager is configured to provide NRO-C evidence to the resource manager that the client requested completion of the initial work and NRR-C evidence to the client that the resource manager promised to execute the completion. Each of the NRO-W evidence, the NRR-W evidence, the NRO-C evidence, and the NRR-C evidence are exchanged to prevent either one of the client and the resource manager from gaining an advantage.

Abstract: Example implementations disclosed herein include techniques for systems, methods, and devices for a heap data structure organized into linked-lists of epoch data pages on a per-core basis in a multi-core multi-node computing system to handle many concurrent transactions.

Abstract: An electronic device is provided. The electronic device includes a display and at least one processor that is configured to display an object corresponding to an application on the display, display an execution screen of the application in an area of the display when a hovering input is detected on the object corresponding to the application, and display the object corresponding to the application on the display when the hovering input is released.

Abstract: A plurality of processing entities are maintained. An indication is made of a primary processing entities group for a task control block (TCB). An indication is made of a secondary processing entities group for the TCB. In response to determining that the secondary processing entities group has processing cycles available for processing additional TCBs, the TCB is moved from the primary processing entities group to the secondary processing entities group for processing.

Abstract: An example device in accordance with an aspect of the present disclosure includes a launch engine and an offload engine. The launch engine is to request a resource predictor based on analysis of collected resource usage information. The offload engine is to compare resource availability at the device to predicted resource usage indicated in the resource predictor, and offload at least a portion of resource usage.

Abstract: A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectively provide a hardware acceleration plane. A common physical network allows the host components to communicate with each other, and which also allows the hardware acceleration components to communicate with each other. Further, the hardware acceleration components in the hardware acceleration plane include functionality that enables them to communicate with each other in a transparent manner without assistance from the software plane.

Abstract: A system of processing a task based on information of frequently used algorithms learned through a memory unit includes a first memory, a second memory, a processor, and a reading unit. The processor processes a first type of task using a first algorithm, and writes to a first memory cell of the second memory. The second memory including first and second memory cells each having a charge storage element. The first and second memory cells correspond to the first and second algorithms, respectively. The reading unit senses a first voltage stored in the first memory cell and a second voltage stored in the second memory cell, and provides information of frequently used algorithms to the processing device based on the sensed first and second voltages.

Abstract: A plurality of ordered lists of dispatch queues corresponding to a plurality of processing entities are maintained, wherein each dispatch queue includes one or more task control blocks or is empty. A determination is made as to whether a primary dispatch queue of a processing entity is empty in an ordered list of dispatch queues for the processing entity. In response to determining that the primary dispatch queue of the processing entity is empty, a task control block is selected for processing by the processing entity from another dispatch queue of the ordered list of dispatch queues for the processing entity, wherein the another dispatch queue from which the task control block is selected meets a threshold criteria for the processing entity.

Abstract: In an example embodiment, a method of operating a task scheduler for one or more processors is provided. A topology of one or more processors is obtained, the topology indicating a plurality of execution units and physical resources associated with each of the plurality of execution units. A task to be performed by the one or more processors is received. Then a plurality of available execution units from the plurality of execution units is identified. An optimal execution unit is then determined, from the plurality of execution units, to which to assign the task, based on the topology. The task is then assigned to the optimal execution unit, after which the task is sent to the optimal execution unit for execution.

Abstract: Techniques are provided for dynamically self-balancing communication and computation. In an embodiment, each partition of application data is stored on a respective computer of a cluster. The application is divided into distributed jobs, each of which corresponds to a partition. Each distributed job is hosted on the computer that hosts the corresponding data partition. Each computer divides its distributed job into computation tasks. Each computer has a pool of threads that execute the computation tasks. During execution, one computer receives a data access request from another computer. The data access request is executed by a thread of the pool. Threads of the pool are bimodal and may be repurposed between communication and computation, depending on workload. Each computer individually detects completion of its computation tasks. Each computer informs a central computer that its distributed job has finished. The central computer detects when all distributed jobs of the application have terminated.

Abstract: An application manager receives or defines a service specification for a first application that defines a set of required computing resources that are necessary to run each application component of the first application. A resource supply manager in communication with the application manager manages a plurality of computing resources in a shared computing environment.

Abstract: The management system according to the present invention, which manages a plurality of computers, manages instances that are implemented using allocated from the plurality of computers, and selects, from among a plurality of different instance implementation methods, an instance implementation method that matches instance configuration information, which is information including settings for configuring an instance and which includes particular settings, each indicating whether the instance needs to monopolize a physical resource, said selection being based the instance configuration information. The plurality of computers provide physical resources to the instance on the basis of the selected instance implementation method.

Abstract: A cloud service method and system based on redistribution of processing power includes registering electronic devices as operation processors and operation consumers through communication with the registered electronic devices over a network; separating, in response to an operation request from an operation consumer for processing power, the requested operation into a plurality of operations; requesting at least a portion of the registered operation processors to process the separated plurality of operations in a distributed manner in which more than one operation processor responds to the operation request; receiving and collecting the distributed processing results of the requested operation from the at least a portion of the registered operation processors; and providing the collected processing results to the operation consumer.

Abstract: A network on a chip architecture uses hardware queues to distribute multiple-instruction tasks to processors dedicated to performing that task. By repeatedly using the same processors to perform the same task, the frequency at which the processors access memory to retrieve instructions is reduced. If a hardware queue runs dry and a processor is remains idle, the processor will determine which queues have tasks and rededicate to performing a new task that has higher demand, without requiring the intervention of centralized load balancing software or specialized programming.

Abstract: A method for live migration of a virtual machine includes receiving a data packet that is sent to a migrated virtual machine on the source physical machine in a stage when the migrated virtual machine is suspended, and caching the received data packet; and sending the cached data packet to the migrated virtual machine on the destination physical machine after it is sensed that the migrated virtual machine is restored at the destination, to speed up restoration of a TCP connection inside the virtual machine. The apparatus of the present disclosure includes a caching unit and a data restoration unit. The method and apparatus of the present disclosure improve a restoration speed of the TCP connection, make live migration of a virtual machine more imperceptible for users, and improve user experience.

Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

Abstract: A framework that creates an abstraction layer to configure/display system resources and process/application resource utilization while accessing the system information from a CLI. The framework is implemented using a scripting language like python and uses pre-existing OS or OEM tools to configure/display system resource information and filter the output to implement the CLI. A user argument defines the choice to use the framework as a standalone utility (running in a Linux shell) or in a library mode. Since the framework makes use of OS or OEM tools and does not access any system resource directly, the framework can be run in the virtual machine and baremetal OS. The framework can access the OS or OEM tools to configure/display system resource information locally and remotely by establishing remote communication through rsh (remote shell) connections. This approach allows reuse of the code, minimizes the implementation complexity, reduces development time and minimizes defects.

Abstract: A computer-implemented method includes receiving, from a first log agent, a first log collection. The computer-implemented method further includes receiving a first policy, wherein the first policy includes a definition of a first pattern and a definition of a procedure. The computer-implemented method further includes scanning the first log collection against the first policy to determine a match between a portion of the first log collection and the first pattern, with the matching portion of the first log collection being identified as a first data artefact. The computer-implemented method further includes, responsive to identifying the first data artefact, executing the procedure defined by the first policy, wherein the procedure includes: filtering the first log collection to yield a first group of filtered log entries, receiving a first data collection, and sending the first group of filtered log entries and the first data collection to a recipient system.

Abstract: Bugs/events that are reported by both users and the product are used to build an estimation model that relates the frequency/amount of received user bug reports to the number of products that are known to have the bug (as reported by the deployed products themselves.) This estimation model is then used to estimate the impact of bugs that are only discovered via user (i.e., free-form, unstructured) bug reports. In addition, the discovery of a bug via only user bug reports can be used to improve the data reported by the deployed products such that more information can be gathered about the nature and/or impact of the bug.

Abstract: An object of the invention is to improve communication quality in a power storage management system. The above-mentioned problem may be solved by the following one solution. When a communication error where transmission, reception, or both transmission and reception of a signal is not allowed occurs between one or a plurality of a plurality of information acquisition devices that acquires states of a plurality of power storage cells and an information collection device that communicates with the plurality of information acquisition devices in a time-division manner, and collects information related to the states of the plurality of power storage cells acquired by the plurality of respective information acquisition devices, a process for resolving a communication error is executed by putting all the plurality of information acquisition devices in a state in which communication with the information collection device is allowed at all times.

Abstract: A method for processing at least one information item in a networked system to yield a result, the at least one information item, which encompasses a value and a validity of the value, being transferred from at least one source of the system to a receiver of the system, an interim data set having at least two variables being used, of which a first variable is allocated to the value of the at least one information item, and a further variable is allocated to the validity of the value, and at least one evaluating step being carried out in the receiver, using the value and the validity, in order to determine a resultant data set having a resultant value and a resultant validity as a result of the processing of the at least one information item.

Abstract: The present invention makes it possible to determine whether there is actually a fault that has occurred in a situation where a specific fault state pertaining to a system to be monitored is continuously detected. An operation management device detects, using the measured value of a performance index pertaining to the system to be monitored and a correlation model representing the relationship between two mutually different performance indices, fault information indicating a fault pertaining to the combination of the two mutually different performance indices. The operation management device holds the detected fault information in chronological order, and determines, on the basis of the fault information, whether the fault information has been detected continuously with respect to a specific combination.

Abstract: A control apparatus connected to a device includes a first control unit configured to execute a program, a second control unit configured to access the device to control the device, and a third control unit configured to control a reset of the control apparatus by transmitting a watchdog reset signal to the first and the second control units. When a condition for triggering a watchdog reset is satisfied, the third control unit transmits a watchdog reset prior notification to the second control unit before transmitting the watchdog reset signal. Upon reception of the watchdog reset signal, the first control unit executes a watchdog reset on the control apparatus. When a watchdog reset is executed, the second control unit controls the device to perform processing for making the device ready to accept a command based on information acquired upon reception of the watchdog reset prior notification.

Abstract: An apparatus includes a plurality of mounting slots each configured to mount an electronic part including a first memory. The apparatus collects, through a first path, from the electronic part mounted on each of the plurality of mounting slots, event information indicating an operating state of the electronic part, and stores the collected event information in a second memory included in the apparatus. When the event information stored in the second memory has a first level of importance, the apparatus causes the event information stored in the second memory to be stored, through a second route, in the first memory of the electronic part from which the event information having the first level of importance has been collected.

Abstract: A method, system, and/or computer program product corrects a data error that has been caused by a break in a conductor link in a memory. A memory controller detects a line malfunction in a data bit transmission line between a first bit node and a second bit node in a memory, and then identifies a constant voltage state at the second bit node that is caused by the line malfunction. In response to determining that the constant voltage state is non-representative of the bit value intended to be transmitted from the first bit node to the second bit node, an inversion logic inverts bit values for all bits in an original bit array to create an inverted bit array, which is stored in the array of memory cells for future retrieval and re-inversion, in order to reconstruct the original bit array.