Abstract: Described is a machine-readable storage medium having instructions stored thereon, that when executed, cause a processor to perform a method which comprises: grouping two or more work groups to form a super-workgroup; and partitioning a portion of a memory space into one or more super-shared local memories (Super-SLMs), wherein the memory space shared within the super-workgroup forms at least one Super-SLM of the one or more Super-SLMs. Described is an apparatus which comprises: a plurality of execution units; a cache memory having a portion characterized as a SLM which is shared with the plurality of execution units at least one of which is to operate on a work group of a sub-slice, wherein the SLM is shared within the work group; and at least one Super-SLM for providing shared memory accessible by different work groups in the sub-slice, wherein the at least one of the execution units is to operate on the different work groups.

Abstract: A data write control method includes detecting a quantity of dirty blocks in a first memory when a write control apparatus is in write-back mode; separately predicting execution progress of a program run by a processor within a danger time period in the two write modes when the quantity of dirty blocks reaches a first preset threshold; when it is predicted that the execution progress of the program run by the processor within the danger time period in write-through mode is faster than the execution progress of the program run by the processor within the danger time period in write-back mode, switching a current data write mode to the write-through mode; and detecting the quantity of dirty blocks when the write control apparatus is in write-through mode and switching the current data write mode to the write-back mode when the quantity of dirty blocks decreases to a second preset threshold.

Abstract: The present disclosure discloses a method for accessing a data visitor directory in a multi-core system, a directory cache device, a multi-core system, and a directory storage unit. The method includes: receiving a first access request sent by a first processor core, where the first access request is used to access an entry, corresponding to a first data block, in a directory; determining, according to the first access request, that a single-pointer entry array has a first single-pointer entry corresponding to the first data block; when determining, according to the first single-pointer entry, that a sharing entry array has a first sharing entry associated with the first single-pointer entry, determining multiple visitors of the first data block according to the first sharing entry. According to embodiments of the present disclosure, storage resources occupied by a directory can be reduced.

Abstract: Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer program product for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a transfer logic used in a power-loss save of the write cache. The one or more operating parameters include an instance-specific process speed of the transfer logic which is retrieved as bin data. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Abstract: The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

Abstract: A system and an operating method thereof include a system on chip (SOC) flash controller having at least one SOC channel; at least one memory device coupled with the at least one SOC channel; a printed circuit board (PCB), wherein the SOC flash controller and the at least one memory device are mounted thereon; a flash address translation (FTL) address translator automatically managing the at least one memory device in accordance with a PCB board configuration file of the PCB board and a drive configuration file of the at least one memory device; and a fuse storing an open data plane (ODP) fuse setting generated in accordance with at least in part with data of the PCB board configuration file and the drive configuration file.

Abstract: A storage device that maps logical addresses to physical addresses includes a memory that stores machine instructions and a processor coupled to the memory that executes the machine instructions to store a compressed mapping table in the memory. The compressed mapping table correlates logical addresses to locations in a storage. The storage device also stores a bundle of uncompressed mapping table entries starting at a first location in a cache and maps a first logical address associated with the uncompressed mapping table entry to the first location.

Abstract: Implementations disclosed herein provide for a storage system including an on-disk read cache and a variety of read cache management techniques. According to one implementation, a storage device controller time-sequentially reads a series of non-contiguous data blocks storing a data sequence in a read cache of a magnetic disk, the data sequence identified by a requested sequence of logical block addresses (LBAs). The controller determines that read requests for the data sequence satisfy at least one predetermined access frequency criterion and, responsive to the determination, the controller re-writes data of the data sequence to a series of contiguous data blocks in the read cache.

Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.

Abstract: A process running method and apparatus is disclosed. The method is: selecting a code page from a candidate process, storing only a code page of the candidate process into a swap partition, and releasing memory space occupied by the code page; updating a physical address that is of the code page and that is stored into a page entry; and when it is determined that the candidate process to which the code page belongs needs to be run, if the code page needs to be executed, directly executing the code page in the swap partition.

Abstract: Provided is a process including: receiving a write command requesting that a document associated with the write command be stored in an immutable data structure that prevents an attacker attempting to modify the document from concealing that the document was modified after storing the document in the data structure; forming a tamper-evident, immutable directed acyclic graph having the document in one or more nodes of the graph; and storing the directed acyclic graph.

Abstract: A system, method, and apparatus for operating system integrated application isolation. A snapshot manager creates a snapshot table including one or more pointers to a file system storage. Then an application is installed on an operating system and mapped to a snapshot table. The snapshot manager receives a request by the application to access a memory block. The snapshot manager determines whether the application has permission to access the memory block. Responsive to a determination that the application has permission to access the memory block, the snapshot manager permits access to the memory block.

Abstract: In a system executing a program, a method comprises detecting one or more input/output calls associated with the program and re-randomizing memory associated with the program in response to the one or more input/output calls. A related system is also described.

Abstract: A loading control method and system for a storage device are disclosed. The method comprises: judging whether a storage controller is valid through a first bus, and judging whether a storage controller is valid through a first bus, and acquiring a key of the storage controller if a positive judgement is made; judging whether the key is valid, commanding the storage controller to turn on a power supply of a storage device if a positive judgement is made; and loading the storage device through a second bus. According to the method, storage devices based on windows and android are allowed to be loaded after the storage device verification is successful, and by means of the method, data security of a user can be effectively protected, which provides reliable and effective protection for future private cloud service data.

Abstract: Provided is a method for reading a block in a database system. Provided is a method for reading data recorded in a persistent storage medium by a first node among a plurality of nodes, including: receiving a reading request for a plurality of blocks among blocks recorded in the persistent storage medium; determining respective master nodes of the plurality of blocks; querying, of the master nodes of the plurality of respective blocks, whether a lock for reading the data recorded in each of the plurality of blocks is required; skipping an operation of obtaining the lock and reading the data, with respect to at least some blocks of which the lock is not required among the plurality of blocks, based on the query result; and reading the data after obtaining the lock with respect to at least some blocks of which the lock is required among the plurality of blocks, based on the query result.

Abstract: A system is described to provide protection key access control in a system whose operating system and processor were not designed to provide a protection key memory access control mechanism. Such a system can be applied to an emulator or to enable a system that executes native applications to be interoperable with a legacy system that employs protection key memory access control.

Abstract: Embodiments of the present disclosure provide a method and device for storage management. The method comprises receiving at a storage management device a configuration request for a storage space managed by the storage management device, the configuration request indicating a capacity of the storage space and a target size of a chunk in the storage space; and based on the capacity and the target size, dividing the storage space into a metadata region storing a chunk status indicator indicating whether the chunk is assigned with data and a data region including the chunk with the target size. Embodiments of the present disclosure also provide a corresponding device.

Abstract: Methods and apparatus for dynamic instruction set selection for producing an output parameter based on one or more available input parameters are presented. In an example method, a device selects, from different candidate instruction sets that are each configured to produce a same output parameter, an instruction set that requires one or more input parameters that are each available at the device. In addition, in the example method, the device obtains the output parameter by executing the selected instruction set using the input parameters required by that instruction set. In some examples where more than one candidate instruction sets could be selected based on the available input parameters, the device may select the highest-ranking instruction set for execution.

Abstract: Disclosed are various embodiments of transmit and receive connectivity devices that include signal processing circuitry, an HDMI port, and a multi-position multi-contact port. The signal processing circuitry can transmit and receive signals over the multi-position multi-contact port. The signals can include a first signal corresponding to a first frequency and a second signal corresponding to a second frequency. A power and ground can be send over a cable attached to the multi-position multi-contact port.

Abstract: A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.

Abstract: A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system.

Abstract: According to an example of managing a universal serial bus (“USB”), a device connected to a USB hub controller is sensed and a USB information scheme from the device is fetched. A power requirement of the device is determined through the USB information scheme, and a total power consumption of a plurality of devices connected to the USB hub controller is calculated. USB information scheme data to display to a user and a data display arrangement are determined, and a monitor scalar is instructed to display the USB information scheme in the determined data display arrangement. Power to the device is distributed based on the total power consumption of all devices connected to the hub controller and a user setting.

Abstract: An automation device has a main module and an interchangeable connection module in which a fieldbus port of the automation device is located. The automation device is characterized in that the interchangeable connection module contains a non-volatile memory which can be read out by the main module of the automation device. A method for operating the automation device includes the steps of connecting a main module of the automation device with a connection module, reading the non-volatile memory of the connection module, detecting any incompatibilities between the main module and the connection module, and placing the automation device in operation if no incompatibilities are detected.

Abstract: A technique for establishing a network interface and an external interface in a connector is disclosed. A personal computer (PC) includes a device controller for controlling data transmission with a peripheral device and a network device, and a receptacle including multiple pins for connecting data channels of the device controller to the peripheral device through the external interface and the network device through the network interface. The PC further includes a crossbar switch for switching the data channels to establish the external interface and the network interface in the receptacle. The external interface complies with the USB standards, and the network interface complies with the Ethernet standards.

Abstract: A wired textile control and power supply system as a connection interface between a smart telephone (1) and an electronic textile (3), the connection interface system is a completely textile Universal Serial Bus (USB) On The Go (OTG) connection interface and is composed of textile circuitry and which comprises: (2a) a harmonized standard textile AB USB micro-connector from the mobile telephony industry and is connected (2b) to a textile cable which produces the USB OTG exchange of power supply and control, (2c) optionally USB textile circuitry for signal conditioning and (2d) a control and power supply connection cable to the electronic textile (3). The proposed invention does not require the additional electronics of a control system dedicated to the electronic textile, which makes it simpler, more comfortable and economic than any other alternative for communication between smart mobile telephone devices and electronic textiles.

Abstract: Implementations of the subject matter described herein provide an input/output (I/O) card for storage device and a storage device. The I/O card and the disk drive for the storage device have the same form factor and comply with the same protocol, to enable the I/O card and the disk drive can be arranged at the same end of the storage device.

Abstract: A method of provisioning cards in a rack mount system, by selecting a desired configuration file from a library of configuration files, and copying the configuration file into a memory device. The memory device is inserted into the rack mount system and powered up. Whereupon the configuration file automatically and without any further user intervention provisions a card of the rack mount system.

Abstract: A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport.

Abstract: A vehicle interface system comprises a vehicle interface processor, a processor data interconnect system, a vehicle communications bus electrical connection system, vehicle interface software, and an application data collection process running on the application processor using spare cycles not used by the application primary process. The application data collection process communicates with the vehicle interface software using the processor data interconnect system.

Abstract: A signal transmitter of the invention is coupled to a plurality of signal receivers by a bus, and is configured to transmit display data through the bus for displaying a line. The signal transmitter includes a first data sequence and a second data sequence. The first data sequence has an electronic characteristic of a first value and is transmitted to a first signal receiver of the signal receivers, and the second data sequence has the electronic characteristic of a second value to a second signal receiver of the signal receivers. Wherein, a first signal transmission path from the signal transmitter to the first signal receiver is shorter than a second signal transmission path from the signal transmitter to the second signal receiver, and the first value is larger than the second value.

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

Abstract: Techniques are disclosed for circuit synchronization. Information is obtained on logical distances between circuits on a semiconductor chip. A plurality of clusters is determined within the chip circuits, where a cluster within the plurality of clusters is synchronized to a tic cycle boundary. A tic cycle count separation is evaluated across the clusters using the information on the logical distances. A plurality of counter initializations is calculated where the counter initializations compensate for the tic cycle count separation across the clusters. A plurality of counters is initialized, with a counter from the plurality of counters being associated with each cluster from the plurality of clusters, where the counters are distributed across the clusters, and where the initializing is based on the counter initializations that were calculated. The plurality of counters is started to coordinate calculation across the plurality of clusters.

Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

Abstract: The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Abstract: Arithmetic circuits calculate d?1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.

Abstract: A similarity measurement method includes: obtaining a directional relationship between nodes in a network, and determining a transition matrix; calculating a constraint matrix according to the transition matrix and an obtained attenuation factor; constructing a system of linear equations, where a coefficient matrix of the system of linear equations is the constraint matrix, and a variable of the system of linear equations is a correction vector; solving the system of linear equations by means of iteration by using a Jacobi method, and determining the correction vector; and calculating similarities between the nodes according to the transition matrix, the attenuation factor, and a diagonal correction matrix that is generated according to the correction vector. In the method, the correction vector is determined by using the Jacobi method, and further the similarities between the nodes may be calculated.

Abstract: A method for processing an audio signal, including: sound is converted to an analog audio input signal and converted into a digital audio signal; a windowed time domain signal is obtained and then a twiddled signal is obtained; the twiddled signal is pre-rotated and then an FFT is performed; an in-place fixed rotate compensation is performed on the FFT signal and then an post-rotated is performed; a quantized signal is obtained and then wrote into a bitstream for transmitting or storing.

Abstract: A lack of available responsive options for existing web sites and/or pages, and the wide spectrum under which they fall presents a challenge for a satisfying mobile user experience (UX) with a hosted collaboration service. Templates used to create a site and/or page may each have capabilities and features which “cross-over” into other templates. Deconstructing and rendering a web page into a native application experience at a mobile client may highlight a template's functionality to enhance the UX. For example, a server side application programming interface (API) may be provided for the mobile UX, a type of a page to be rendered may be determined, the page may be deconstructed into pieces, and the deconstructed pieces may be provided to rebuild the page at the mobile client natively. The page may be rendered on the mobile client with added elements based on the deconstructed pieces to enhance the mobile UX.

Abstract: Techniques are described for managing the generation, style, and/or distribution of digital contact cards. An organization may access a card management platform and upload style information for digital contact card(s). Style information may include an arrangement and/or layout of the card(s), an organization name and/or logo to be included on the card(s), the font, color, size, or other characteristics of the text on the card(s), and so forth. A user may access the platform to request the distribution of a digital contact card to recipient(s). In response to the request, the platform may generate a digital contact card for the user based on the previously specified style information, and distribute card(s) to the specified recipient(s). Techniques are also described for determining positions of various mobile devices (and associated users) in a room or other area, and presenting received contact card information in a user interface according to the determined positions.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.

Abstract: Apparatuses and methods for enhanced text metadata systems are described herein. In a non-limiting embodiment, a camera on an electronic device may be activated in response to receiving a signal indicating a message is being inputted by a user. While receiving the message, a camera may capture an image of the user. This image may be analyzed to determine an emotion the user is feeling when inputting the message. Once an emotion of the user is determined, the message will be altered to reflect the emotion the user is feeling.

Abstract: A method and a file format transformation system (FFTS) for transforming marked-up content in a first file format (FFF) to a second file format (SFF) that enables automated browser based pagination are provided. The FFTS reflows marked-up content of the FFF into a continuous page. The FFTS generates and appends tags to spaces and block elements identified in the reflown marked-up content of the FFF. For each space and block element, the FFTS determines and tags line breaks in the reflown marked-up content. For each line break, the FFTS identifies, tags, and positions anchored floats and footnotes on a current page based on space availability. The FFTS positions page breaks in the continuous page based on a configurable page height and the line breaks. The FFTS groups the marked-up content, inserts pagination elements and renders the grouped marked-up content in the SFF based on a selected level of reversibility.

Abstract: Encoding Chinese in one(linear code)-to-one(character or word) correspondence systematically has been a century old challenge. Based on the official standards for Pinyin and writing order of characters, that all Chinese users are familiar with, this invention comprises: (1) encoding all characters and words of a predetermined set or dictionary into distinct codes in electronic system like computer; (2) retrieving character or word by decoding user's keyboard input, and then entering the corresponding character or word into the system. Denoted inside [ ], the proposed Pinyin+X coding format is [Pinyin+X]=[Pinyin]+[3-Stroke]+[Extra], where [3-Stroke] consists of three consonant letters coding for the first, second, and last stroke of the writing form of character or word, and [Extra] is system-generated consonant letter(s) to ensure the uniqueness of the entire [Pinyin+X] code. Pinyin+X keyboard entry process for Chinese can therefore be designed to be direct that every keystroke counts and none is extra.

Abstract: There is disclosed a computer-implemented method for generating a hierarchical data structure. The computer-implemented method can be executable at a server. The computer implemented method comprises: identifying a plurality of data elements to be searched, the plurality of data elements having a set of descriptors, each descriptor within the set of descriptors being associated with a data type being different from data types of other descriptors within the set of descriptors; defining the hierarchical data structure, having a first level and a second level.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.