Abstract: A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path, wherein a part of the source field plate above the gate electrode has a varying distance from an upper surface of the semiconductor layer. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region and the insulating layer in the nitride semiconductor layer and has a higher electric resistivity than the first region.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).

Abstract: A semiconductor device may include a semiconductor substrate; a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.

Abstract: A switching device has a substrate and a power semiconductor component, comprising a connection device and a pressure device wherein the substrate has tracks electrically insulated from one another. The power semiconductor component is on one of the tracks with a first main surface and is conductively connected thereto. The device is embodied as a film composite having a conductive film and an insulating film that forms a first and a second main surface. The switching device is connected internally in a circuit-conforming manner by the connection device and a contact area of the connection device is connected to a first contact area of one of the tracks in a force-locking and electrically conductive manner. There is a pressure body projecting to the substrate and pressing onto a first section of the second main surface of the film composite.

Abstract: A device includes an n-doped InP layer and an ohmic contact, in contact with the n-doped InP layer. The ohmic contact includes an annealed stack of at least three, or preferably four alternating layers of Si and Ni, such that: (i) the n-doped InP layer and one of the layers of the stack in contact with the n-doped InP layer are at least partly intermixed; and (ii) any two adjacent layers of the stack are at least partly intermixed. Related fabrication methods are also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.

Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.

Abstract: A method for forming a spacer for a semiconductor device includes patterning gate material in a transverse orientation relative to semiconductor fins formed on a substrate and conformally depositing a dummy spacer layer over surfaces of gate structures and the fins. A dielectric fill formed over the gate structures and the fins is planarized to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of the sidewalls of the gate structures. Channels are formed by removing the dummy spacer layer along the sidewalls of the gate structures. The fins are protected by the dielectric fill. A spacer is formed by filling the channels with a spacer material. The dielectric fill and the dummy spacer layer are removed to expose the fins. Source and drain regions are formed between the gate structures on the fins.

Abstract: Various methods and devices that involve body contacted transistors are disclosed. An exemplary method comprises forming a gate on a planar surface of a semiconductor wafer. The gate covers a channel of a first conductivity type that is opposite to a second conductivity type. The method also comprises implanting a body dose of dopants on a source side of the gate using the gate to mask the body dose of dopants. The body dose of dopants spreads underneath the channel to form a deep well. The body dose of dopants has the first conductivity type. The method also comprises implanting, subsequent to implanting the body dose of dopants, a source dose of dopants on the source side of the gate to form a source. The method also comprises forming a source contact that is in contact with the deep well at the planar surface of the semiconductor wafer.

Abstract: Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction.

Abstract: The present disclosure provides a display device, including: a gate line and a data line; a pixel array; a gate driver, configured to provide a gate signal to the gate line; a test circuit, coupled to a first input line and a second input line respectively; and a data driver, including a first power line, a first transistor and a third input line, wherein the first power line is configured to supply an initial voltage to the pixel array, the first power line is coupled to the first input line via the first transistor, a gate of the first transistor is coupled to the third input line, the third input line is configured to transmit a pre-charge control signal, and the pixel array is configured to supply the initial voltage to each pixel in the pixel array based on the pre-charge control signal.

Abstract: During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.

Abstract: Three optimizations are provided for B-TRAN devices which include field plate trenches: 1) the trench dielectric thickness is large enough to withstand the base-to-emitter voltage, but thin enough to provide good electrical coupling between the poly field plate and the adjacent p-type silicon; 2) the base contact width is small enough to provide an acceptably low reverse base contact region pinch-off voltage, but large enough to avoid degradation of both base resistance; and 3) the emitter width is small enough to keep an acceptably high current density at the emitter's center.

Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.

Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer and an insulating layer including an oxide film or an oxynitride film that contacts with the nitride semiconductor layer. The oxide film or the oxynitride film includes at least one impurity selected from the group consisting of boron (B), gallium (Ga), aluminum (Al), and indium (In) and carbon (C). A first peak of a concentration distribution of the at least one impurity in the insulating layer is present in the oxide film or the oxynitride film. A second peak of a concentration distribution of carbon in the insulating layer is present in the oxide film or the oxynitride film. A distance between the first peak and the nitride semiconductor layer is equal to or less than 5 nm, and a distance between the second peak and the nitride semiconductor layer is equal to or less than 5 nm.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and a source external connecting element. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The source pad is electrically connected to the source electrode and includes a body portion, a plurality of branch portions, and a current diffusion portion. The body portion is at least partially disposed on the active region of the active layer. The current diffusion portion interconnects the body portion and the branch portions. A width of the current diffusion portion is greater than a width of the branch portion and less than a half of a width of the body portion. The source external connecting element is disposed on the body portion and spaced from the current diffusion portion.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Abstract: A semiconductor device has an active region in which a plurality of unit cells are regularly arranged, each of the unit cells including: a channel region having a first conductivity type and formed over a front surface of a semiconductor substrate; a source region having a second conductivity type different from the first conductivity type and formed over the front surface of the semiconductor substrate in such a manner as to be in contact with the channel region; and a JFET region having the second conductivity type and is formed over the front surface of the semiconductor substrate on the opposite side of the channel region from the source region in such a manner as to be in contact with the channel region. The channel region is comprised of a first channel region and a second channel region higher than the first channel region in impurity concentration, over the front surface of the semiconductor substrate.

Abstract: A semiconductor structure is provided in which gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.

Abstract: Edge termination structures for power semiconductor devices (or power devices) are disclosed. The purpose of this invention is to reduce the difficulty of deep trench etching and dielectric filling by adopting an inverted trapezoidal trench. In order to save the area of edge termination and get a high blocking voltage on condition that the angle between the sidewall of the trench and horizontal is large, fixed charges are introduced at a particular location in the trench. Due to the Coulomb interaction between the ionized impurity in the drift region and the fixed charges, the depletion region of the terminal PN junction can extend fully, which relieves the concentration of electric field there. Therefore, the edge termination can exhibit a high breakdown voltage near to that of the parallel plane junction with a smaller area and the reduced technical difficulty of deep trench etching and dielectric filling.

Abstract: A method of manufacturing a semiconductor device includes: forming a trench extending into a semiconductor substrate and a polysilicon gate electrode in the trench; forming a body region of a first conductivity type in the substrate adjacent the trench and a source region of a second conductivity type adjacent the body region and the trench; forming a dielectric layer on the substrate; forming a gate metallization on the dielectric layer which covers part of the substrate and a source metallization on the dielectric layer which is electrically connected to the source region, spaced apart from the gate metallization and covering a different part of the substrate than the gate metallization; and forming a metal-filled groove in the polysilicon gate electrode which is electrically connected to the gate metallization. The metal-filled groove extends along a length of the trench underneath at least part of the source metallization.

Abstract: To suppress current leakage in a semiconductor device having a gate insulating film and a gate electrode. A gate electrode is continuously formed in a film via a gate insulating film on the bottom surface of a trench, the side surfaces of a trench, and the top surfaces of a second n-type layer in the vicinity of the side surfaces of the trench. The ends of the bottom surface of the gate electrode are aligned with the ends of the top surface of the gate insulating film, and the ends of the bottom surface of the gate insulating film are formed in contact with the surfaces of the second n-type layer facing the ends of the bottom surface of the gate electrode. The passivation film covers the entire top surface of the device except the contact holes of the gate electrode and the source electrode.

Abstract: A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.

Abstract: A semiconductor device in a semiconductor substrate having a first main surface includes a transistor array and a termination region. The transistor array includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel in the body region. The body region and the drift zone are disposed along a first horizontal direction between the source region and the drain region. The transistor array further includes first field plate trenches in the drift zone. A longitudinal axis of the first field plate trenches extends in the first horizontal direction. The semiconductor device further includes a second field plate trench, a longitudinal axis of the second field plate trench extending in a second horizontal direction perpendicular to the first direction.

Abstract: In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.

Abstract: A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is improved. The vertical Schottky contact transistor includes a bottom Schottky contact source/drain structure and a top Schottky contact source/drain structure located at opposing ends of a semiconductor channel region. The bottom Schottky contact source/drain structure includes a base portion and a vertically extending portion.

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.

Abstract: The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

Abstract: A thin-film transistor including an insulative substrate, a gate electrode formed on the insulative substrate, a gate insulating layer formed on the substrate and the gate electrode, a source electrode and a drain electrode forming on the gate insulating layer and spaced from each other, a semiconductor layer formed on the gate insulating layer and connected to the source electrode and the drain electrode, a semiconductor protective layer formed on the semiconductor layer, an interlayer insulating film formed on the source electrode, the drain electrode and the semiconductor protective layer, the interlayer insulating film including a fluorine compound, and an upper electrode formed on the interlayer insulating film.

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

Abstract: The present invention relates to the field of semiconductor technology, particularly to a super-junction schottky diode. According to the present invention, the effective area of schottky junction is increased by forming the schottky junction in the trench located in the body of the device. Therefore, the current capacity of this novel schottky diode can be greatly improved. In addition, a super-junction structure is used to improve the device's reverse breakdown voltage and reduce the reverse leakage current. The super-junction schottky diode provided in the present invention can achieve a larger forward current, a lower on-resistance and a better reverse breakdown characteristic.

Abstract: The invention provides a power semiconductor device including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 105 cm?2 and the Full Width Half Maximum (FWHM) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and a power semiconductor structure comprising at least one doped AlxGa1-xN layer overlying the aluminum nitride single crystalline substrate.

Abstract: A semiconductor substrate includes a first region in which a plurality of pixels are disposed and a second region located inside the first region to be surrounded by the first region when viewed from a direction in which a principal surface and a principal surface oppose each other. A through-hole penetrating through the semiconductor substrate is formed in the second region of the semiconductor substrate. An electrode disposed on a side of the principal surface of the semiconductor substrate and electrically connected to the plurality of pixels and an electrode disposed on a side of a principal surface of a mount substrate are connected to each other via a bonding wire inserted through the through-hole.

Abstract: A plasmonic scattering nanomaterial comprising a substrate layer, a metal oxide layer in continuous contact with the substrate layer and silver nanoparticles with a diameter of 25-300 nm deposited on the metal oxide layer is disclosed. The silver nanoparticles have a broad size distribution and interparticle distances such that the silver nanoparticles plasmonically scatter light throughout the metal oxide layer with a near electric field strength of 1-30 V/m when excited by a light source having a wavelength in the range of 300-500 nm and/or 1000-1200 nm. In addition, a method for producing the nanomaterial by sputter deposition is disclosed as well as an appropriate thin film plasmonic solar cell comprising the nanomaterial with a solar efficiency of at least 10%.

Abstract: A photon detection device includes a single photon avalanche diode (SPAD) including a multiplication junction defined at an interface between n doped and p doped layers of the SPAD in a first region of a semiconductor layer. A vertical gate structure surrounds the SPAD in the semiconductor layer to isolate the SPAD in the first region from a second region of the semiconductor layer on an opposite side of the vertical gate structure. The SPAD laterally extends within the first region of semiconductor layer to the vertical gate structure. An inversion layer is generated in the SPAD around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure. The inversion layer isolates the SPAD from the second region of the semiconductor layer on the opposite side of the vertical gate structure.

Abstract: A solar cell has a backside resonant waveguide structure. The backside structure includes a plurality of resonant waveguides formed in or on a semiconductor-based light absorbing material and arranged in a pattern to cause laterally scattered light to be at least partially confined in the semiconductor-based light absorbing material.

Abstract: A solar antenna array may comprise an array of carbon nanotube antennas that may capture and convert sunlight into electrical power. A method for constructing the solar antenna array from a glass top down to aluminum over a plastic bottom such that light passing through the glass top and/or reflected off the aluminum both may be captured by the antennas sandwiched between. Techniques for patterning the glass to further direct the light toward the antennas and techniques for continuous flow fabrication and testing are also described.

Abstract: A wavelength conversion member (20) includes a fluoride phosphor (25) activated by Ce3+ or Eu2+. Then, with regard to the fluoride phosphor, internal quantum efficiency measured at 80° C. is 85% or more when internal quantum efficiency measured at 30° C. is taken as 100%. Moreover, a photovoltaic device includes the above-mentioned wavelength conversion member. The wavelength conversion member uses a fluoride phosphor, in which a decrease of the internal quantum efficiency is suppressed, and excellent temperature characteristics are imparted. Therefore, the wavelength conversion member can effectively utilize ultraviolet light even at high temperature, and it becomes possible to enhance an output of the photovoltaic device.

Abstract: A method for texturing a photovoltaic module ribbon on a photovoltaic cell including a plurality of first electrodes on a first side and a plurality of second electrodes on a second side, and coupling a first photovoltaic module ribbon to the plurality of first electrodes. The method also includes positioning the photovoltaic cell on a textured base having a texture embodied thereon, where the first photovoltaic module ribbon is substantially contacting the texture. The method further includes coupling a second photovoltaic module ribbon to the plurality of second electrodes, and transferring the texture of the textured base to the first ribbon using heat energy released when the second photovoltaic module ribbon is coupled to the plurality of second electrodes.

Abstract: A display may include a color filter layer, a liquid crystal layer, and a thin-film transistor layer. A camera window may be formed in the display to accommodate a camera. The camera window may be formed by creating a notch in the thin-film transistor layer that extends inwardly from the edge of the thin-film transistor layer. The notch may be formed by scribing the thin-film transistor layer around the notch location and breaking away a portion of the thin-film transistor layer. A camera window may also be formed by grinding a hole in the display. The hole may penetrate partway into the thin-film transistor layer, may penetrate through the transistor layer but not into the color filter layer, or may pass through the thin-film transistor layer and partly into the color filter layer.

Abstract: A-light-emitting device which realizes a high aperture ratio and in which the quality of image is little affected by the variation in the characteristics of TFTs. The channel length of the driving TFTs is selected to be very larger than the channel width of the driving TFTs to improve current characteristics in the saturated region, and a high VGS is applied to the driving TFTs to obtain a desired drain current. Therefore, the drain currents of the driving TFTs are little affected by the variation in the threshold voltage. In laying out the pixels, further, wiring is arranged under the partitioning wall and the driving This are arranged under the wiring in order to avoid a decrease in the aperture ratio despite of an increase in the size of the driving TFT.

Abstract: An LED element includes a substrate, a semiconductor lamination part that includes a light-emitting layer formed on a front surface of the substrate, a reflecting portion formed on a back surface of the substrate, and an electrode formed on the semiconductor lamination part. The electrode includes a diffusion electrode layer formed on the semiconductor lamination part and a moth-eye layer which is formed on the diffusion electrode layer and of which the front surface forms the transmissive moth-eye surface having depression parts or projection parts formed with a period smaller than twice the optical wavelength of the light emitted from the light-emitting layer.