Abstract: A semiconductor device having favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a metal oxide. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, the metal oxide over the first insulating film, a pair of electrodes over the metal oxide, and a second insulating film in contact with the metal oxide. The metal oxide includes a first metal oxide and a second metal oxide in contact with a top surface of the first metal oxide. The first metal oxide and the second metal oxide each contain In, an element M (M is gallium, aluminum, silicon, or the like), and Zn. The first metal oxide includes a region having lower crystallinity than the second metal oxide. The second insulating film includes a region whose thickness is smaller than that of the second metal oxide.

Abstract: A silicon chalcogenate precursor comprising the chemical formula of Si(XR1)nR24-n, where X is sulfur, selenium, or tellurium, R1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each R2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed.

Abstract: Methods for seam-less gapfill comprising forming a flowable film by exposing a substrate surface to a silicon-containing precursor and a co-reactant are described. The silicon-containing precursor has at least one akenyl or alkynyl group. The flowable film can be cured by any suitable curing process to form a seam-less gapfill.

Abstract: A method of forming a thin film is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of an organic precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to mix the adsorbed carbon-containing film with the material of the underlying substrate and form a mixed film.

Abstract: An apparatus for fabricating a thin film is provided. The apparatus includes a tube including one end and another end, a first heater supplying heat to a first region, adjacent to the one end, of the tube, a second heater supplying heat to a second region, adjacent to the another end, of the tube and disposed in parallel to the first heater along the tube, a gas inlet through which a source gas is supplied to the one end of the tube, and a gas outlet through which the source gas is exhausted from the another end of the tube.

Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.

Abstract: A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

Abstract: A p-type impurity diffusion composition is provided which makes it possible to improve storage stability of a coating liquid, and to achieve uniform diffusion of the coating liquid on a semiconductor substrate. The p-type impurity diffusion composition includes (A) a group-13 element compound, (B) a hydroxyl-group-containing polymer, and (C) an organic solvent, (Cl) a cyclic ester solvent being contained in the organic solvent.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A source electrode and a drain electrode of a channel-etched transistor are each made to have a stacked-layer structure including a first conductive layer and a second conductive layer. A silicide that contains a metal element contained in the second conductive layer and nitrogen is formed to be in contact with a top surface and a side surface of the second conductive layer. Before etching of the first conductive layer, the silicide is formed by exposing the second conductive layer to an atmosphere containing silane, and plasma treatment is performed in a nitrogen atmosphere without exposure to the air.

Abstract: Methods for etching a bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) to form high aspect ratio features using an etch process are provided. The methods described herein advantageously facilitate profile and dimension control of features with high aspect ratios through a proper sidewall and bottom management scheme during the bottom anti-reflective coating (BARC) and/or an anti-reflective coating (ARC) and/or a dielectric anti-reflective coating (DARC) open process.

Abstract: A dry etching method includes performing at least two etching steps, and further includes injecting protective gas into an etch chamber for processing between any two successive etching steps, wherein the protective gas generates plasma to neutralize electrons accumulated on a side wall of an etching trench. According to the present disclosure, hydrogen plasma is added in an etching process to remove the electrons accumulated on the side wall of the etching trench so as to reduce the microetching effect in multiple etching. In this way, process stability and reliability of a display substrate are improved.

Abstract: A method of etching is described. The method includes treating at least a portion of a surface exposed on a substrate with an adsorption-promoting agent to alter a functionality of the exposed surface and cause subsequent adsorption of a carbon-containing precursor, and thereafter, adsorbing the organic precursor to the functionalized surface to form a carbon-containing film. Then, at least a portion of the surface of the carbon-containing film is exposed to an ion flux to remove the adsorbed carbon-containing film and at least a portion of the material of the underlying substrate.

Abstract: There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a polymer having a urea bond by supplying polymerizing raw materials to a surface of the substrate on which an etching target film formed; forming an etching pattern on the masking film; subsequently, etching the etching target film with a processing gas using the etching pattern; and subsequently, removing the masking film by heating the substrate to depolymerize the polymer.

Abstract: A transistor with high productivity and a method for manufacturing the transistor are provided. In the formation of a bottom-gate transistor using a metal oxide layer as a semiconductor layer where a channel is formed, a gate insulating layer including silicon nitride is formed, and then plasma treatment is successively performed in the same treatment chamber under an atmosphere containing oxygen. After that, the metal oxide layer is formed.

Abstract: A silicon carbide composite that is lightweight and has high thermal conductivity as well as a low thermal expansion coefficient close to that of a ceramic substrate, particularly a silicon carbide composite material suitable for heat dissipating components that are required to be particularly free of warping, such as heat sinks. A method for manufacturing a silicon carbide composite obtained by impregnating a porous silicon carbide molded body with a metal having aluminum as a main component, wherein the method for manufacturing a silicon carbide composite material is characterized in that the porous silicon carbide molded article is formed by a wet molding method, and preferably the wet molding method is a wet press method or is a wet casting method.

Abstract: A substrate processing apparatus includes: a plurality of modules configured to process a substrate; a transfer chamber adjoining the modules; a transfer part configured to transfer the substrate to one of the modules; a reception part configured to receive process information of the substrate; a detection part configured to detect quality information of the respective modules; a table in which the process information corresponds to the quality information; a memory part configured to store the table; and a controller configured to compare the process information received by the reception part with the quality information detected by the detection part using the table, configured to select one of the modules corresponding to the process information, and configured to instruct the transfer part to transfer the substrate to the selected module.

Abstract: Disclosed is a substrate treating apparatus that treats a substrate with processing liquids. The apparatus includes a substrate holder, an exterior cup, and an interior cup. The interior cup includes an interior cup body, and an interior cup outlet. The exterior cup includes an exterior cup body, an exterior bottom cup, a first drain outlet, a first exhaust port, a second drain outlet, a second exhaust port, and a separation partition. The apparatus further includes an annular member movable upwardly/downwardly, and a drive unit that causes the annular member to move to shift the interior cup body between a collecting position and a retracting position.

Abstract: A substrate processing apparatus includes a guard that catches liquid scattered outward from a spin chuck, a cup defining a liquid receiving groove to catch liquid that is guided downward by the guard, a guard elevating/lowering unit that moves the guard in an up/down direction, a cleaning liquid supplying unit that supplies cleaning liquid, discharged from a cleaning liquid nozzle, to the liquid receiving groove via the spin chuck and the guard, a cleaning liquid draining unit that drains the cleaning liquid in the liquid receiving groove, and a controller that controls the cleaning liquid supplying unit and the cleaning liquid draining unit to accumulate cleaning liquid in the liquid receiving groove and controls the guard elevating/lowering unit to cause a lower end portion of the cylindrical portion to be immersed in the cleaning liquid in the liquid receiving groove.

Abstract: A plasma processing apparatus includes: a processing container which defines a processing space; a microwave generator; a dielectric having an opposing surface which faces the processing space; a slot plate formed with a plurality of slots; and a heating member provided within the slot plate. The slot plate is provided on a surface of the dielectric at an opposite side to the opposing surface to radiate microwaves for plasma excitation to the processing space through the dielectric based on the microwaves generated by the microwave generator.

Abstract: Methods and apparatus for changing the temperature of a substrate are provided. In some embodiments, a method includes: placing a substrate onto a support surface of a substrate support disposed within an inner volume of a cooling chamber; moving at least one of the substrate support or a plate disposed in the cooling chamber opposite the substrate support from a first position, in which the substrate is placed onto the support surface, to a second position, in which a second volume is created between the support surface and the plate, the second volume being smaller than and substantially sealed off from a remaining portion of the inner volume; flowing a gas into the second volume to increase a pressure within the second volume; and flowing a coolant through a plurality of channels disposed in at least one of the substrate support or the plate to cool the substrate.

Abstract: A wafer holder and temperature controlling arrangement has a metal circular wafer carrier plate, which covers a heater compartment. In the heater compartment a multitude of heater lamp tubes is arranged, which directly acts upon the circular wafer carrier plate. Latter is drivingly rotatable about the central axis. A wafer is held on the circular wafer carrier plate by means of a weight-ring residing upon the periphery of a wafer deposited on the wafer carrier plate.

Abstract: A substrate processing apparatus includes an outer tube including an open bottom portion and a closed top portion, and an inner tube disposed in the outer tube and spaced apart from the outer tube. The inner tube includes a first opening at a top portion of the inner tube, a second opening at a bottom portion of the inner tube, and an inner sidewall including a plurality of exhaust holes on one side of the inner sidewall, the inner sidewall defining the first and second openings.

Abstract: The substrate liquid processing apparatus includes a processing bath that accommodates substrates, and a plurality of gas supply pipes provided in a processing bath. Ejection holes of one gas supply pipe and ejection holes of another adjacent gas supply pipe do not overlap each other in a direction parallel to the circuit-formed surfaces of the substrates.

Abstract: Disclosed herein is a hold checking method for checking whether or not a wafer is held by an electrostatic chuck in loading the wafer to the electrostatic chuck by operating a transfer unit holding the wafer. The hold checking method includes a connecting step of bringing the wafer held by a transfer pad into contact with the electrostatic chuck to thereby connect the transfer pad through the wafer to the electrostatic chuck, and a hold determining step of supplying electric power from a DC power source through first wiring to the electrostatic chuck after performing the connecting step, and next determining that the wafer is held by the electrostatic chuck when the voltage across a resistor inserted in the first wiring has reached a predetermined voltage value.

Abstract: Semiconductor device fabrication systems and methods are provided. In an example, a semiconductor device fabrication system includes a semiconductor fabrication tool. Further, the semiconductor device fabrication system includes wireless sensors associated with the semiconductor fabrication tool. The wireless sensors measure process parameters of the fabrication tool and transmit wireless signals. The semiconductor device fabrication system also includes a sensor controller configured to identify the wireless sensors associated with the semiconductor fabrication tool and to receive the wireless signals from the wireless sensors. The semiconductor device fabrication system further includes a tool controller including a receiver for receiving data from the sensor controller. The tool controller is configured to sequentially assign system variable identifiers (SVID) to the data from the sensor controller, and to contextualize the data in data packets.

Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

Abstract: A processed wafer is described that may be used as a workpiece carrier in semiconductor and mechanical processing. In some examples, the workpiece carrier includes a substrate, an electrode formed on the substrate to carry an electric charge to grip a workpiece, a through hole through the substrate and connected to the electrode, and a dielectric layer over the substrate to isolate the electrode from the workpiece.

Abstract: A laminated top plate of a workpiece carrier is described that is particularly suitable for mechanical and semiconductor processing. In one example, A method of fabricating a workpiece carrier top plate includes dispensing conductive paste onto at least one of a plurality of ceramic sheets, embedding the paste between the plurality of ceramic sheets, compacting ceramic sheets together with the paste, and sintering the paste.

Abstract: An electrostatic chuck part of an electrostatic chuck device has an electrostatic chuck part inner peripheral surface surrounding an opening of a chuck part through-hole, and an electrostatic chuck part outer peripheral surface surrounding the electrostatic chuck part inner peripheral surface. An insulator has an insulator main body in which an insulator through-hole having an opening on the electrostatic chuck part side is formed, an insulator inner end face, and an insulator outer end face which faces the electrostatic chuck part outer peripheral surface. The insulator inner end face and the electrostatic chuck part inner peripheral surface are in contact with each other, or an adhesion layer or a plasma-resistant adhesive layer extends in a gap between the insulator inner end face and the electrostatic chuck part inner peripheral surface. The plasma-resistant adhesive layer is formed between the electrostatic chuck part outer peripheral surface and the insulator outer end face.

Abstract: A semiconductor integrated circuit device may include a first electrostatic discharge (ESD) protecting circuit and a second ESD protecting circuit. The first ESD protecting circuit may include at least one resistance changeable device connected between a power voltage line and a data pad to discharge an electrostatic. The second ESD protecting circuit may include at least one resistance changeable device connected between the first ESD protecting circuit and a ground voltage line.

Abstract: A semiconductor structure includes a first well, a semiconductor element, a second well and a first isolation layer. The semiconductor element is formed on or contacts the first well. The first well is formed on the second well. The first isolation layer is used to reduce a parasitic effect between the first well and the second well. The bottom of the first isolation layer is at least as deep as the bottom of the first well. The first isolation layer substantially forms a first ring structure around the first well. The doping type of the second well is different from the doping type of the first well.

Abstract: Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.

Abstract: A method of manufacturing a semiconductor device may include forming an insulating layers on a substrate, forming a plurality of holes in an upper portion of the insulating layer, forming a mask layer having openings exposing at least a first set of the plurality of holes, etching a lower portion of the insulating layer exposed by one of the plurality of holes which is exposed by the mask layer to form a through hole in the insulating layer in combination with the one of the plurality of holes, and forming a conductive structure in the through hole.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Abstract: A method for selectively depositing a metal film onto a substrate is disclosed. In particular, the method comprising flowing a metal precursor onto the substrate and flowing a non-metal precursor onto the substrate, while contacting the non-metal precursor with a hot wire. Specifically, a reaction between a tungsten precursor and a hydrogen precursor selectively forms a tungsten film, where the hydrogen precursor is excited by a tungsten hot wire.

Abstract: Provided is a method for removing barrier layer for minimizing sidewall recess. The method comprises the following steps: introduce noble-gas-halogen compound gas and carrier gas into an etching chamber within which a thermal gas phase etching process is being performed for etching a barrier layer (206) on non-recessed areas of an interconnection structure (501); detect an end point of the thermal gas phase etching process (502), if the thermal gas phase etching process reaches the end point end point, then execute the next step; if the thermal gas phase etching process doesn't reach the end point, then return to the previous step; stop introducing the noble-gas-halogen compound gas and the carrier gas to the etching chamber (503).

Abstract: Interconnect structures and processes generally include creating point defects in exposed surfaces of the dielectric layer to create a point defect region at a relatively shallow depth, wherein the point defect region is a fraction of the dielectric layer and is created with exposure to silicon, carbon, nitrogen, oxygen, or mixtures thereof such that the point defect region contains Si, C, N O, or mixtures containing at least one of the foregoing. A seed layer can be deposited and includes at least one alloying element that is effective to form an in situ self-aligned liner layer with the Si, C, N O, or mixtures containing at least one of the foregoing within the point defect region, which is formed at a depth of less than 10 nanometers. The in situ liner layer within the dielectric layer maximizes the volume fraction of the conductor of the interconnect structure.

Abstract: A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.

Abstract: A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel material, and removing portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first and second sacrificial mandrel. Spacers are formed adjacent to the sacrificial mandrels. A filler material is deposited on the second hardmask, and a first mask is formed on the filler material. An exposed portion of the second sacrificial mandrel is removed to form a first cavity. The depth of the first cavity is increased. The first mask, portions of the first and second sacrificial mandrels, the filler material, portions of the second hardmask, the spacers, portions of the planarization layer and the first hardmask are removed. A second cavity is formed and the first and second cavities are filled with a conductive material.

Abstract: A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

Abstract: A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of first patterns that extend in a first direction, are parallel to one another, and are separated from one another with a space therebetween. At least one support structure that contacts an upper surface of the pattern structure and extends on the pattern structure in a second direction that crosses the first direction is formed. A buried layer that fills the spaces between the plurality of first patterns while the at least one support structure contacts the upper surface of the pattern structure is formed. The at least one support structure is separated from the pattern structure.

Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.

Abstract: A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of reference chips with respect to the substrate in the images, obtaining relative offsets of subordinate chips with respect to the reference chips in the images, and calculating misalignments of the chips based on the absolute offsets and the relative offsets.

Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

Abstract: Efficiency of prediction of a physical quantity increases in repeated simulation of an etching process with a change of parameters. An information processing device includes a base shape storage unit and a physical quantity prediction unit. The base shape storage unit of the information processing device stores a shape of a sample etched within a chamber as a base shape. On the other hand, the physical quantity prediction unit of the information processing device predicts a physical quantity within the chamber on the basis of a processing condition determined for the sample and associated with the physical quantity and the base shape.

Abstract: Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.

Abstract: A method for inspecting the influence of an installation environment upon a processing apparatus includes setting a mark for specifying a relative positional relation between a chuck table and a processing unit, imaging the mark plural times by using an imaging unit when a moving unit is at rest, and detecting the position of the mark from an image and then determining whether or not the influence of the installation environment upon the processing apparatus is present based on whether the change in position of the mark is less than or more than a threshold.

Abstract: A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.