Abstract: A system for package management includes an interface and a processor. The interface is to receive an indication to install a package. The processor is to determine a configured package using a set local configuration properties and using the package and to launch, using a metascheduler, a set of subschedulers to install a plurality of applications of the configured package.

Abstract: A mechanism for automatic installing and scaling of application resources in a multi-tenant Platform-as-a-Service (PaaS) environment in a cloud computing system is disclosed. A method includes creating, by a processing device of an Infrastructure-as-a-Service (IaaS) platform, an image package corresponding to a node host on a multi-tenant Platform-as-a-Service (PaaS) system. The image package comprises an image file including a script file having a plurality of software updates and run time configuration files. The image package is stored in a storage memory of the IaaS platform and is accessible by a virtual machine (VM) instance. The method also includes retrieving, from the storage memory, the script file from the image package and causing a boot process of the VM instance to download the script file into the PaaS system.

Abstract: An independent product upgrade function is associated with each of multiple software products installed in a set of multiple computing devices. Responsive to a triggering event, each upgrade function determines whether the corresponding product can be updated based on rules for the corresponding product. Upgrade may be dependent on other products, but the upgrade function need not know the conditions for upgrading other products. If a product can be updated, update is performed and all other products are notified. Each of the other product upgrade functions then determines whether its corresponding product can be upgraded as a result of the recent upgrade to the first product, and if so, another set of notifications is sent. This cycle continues until all dependent products have been updated. Upgrade functions preferably operate in a peer-to-peer relationship, and upgrade can be initiated in any node.

Abstract: Techniques for managing an upgrade operation comprising multiple upgrade process executing on multiple host machines (or hosts) for upgrading software applications on the multiple hosts. Techniques are disclosed for managing notifications that are generated by the multiple upgrade processes during execution, and more particular, techniques for reducing the number of notifications that are sent to a user. The techniques include: only sending a subset of the generated notifications to a user, the subset being selected at the host machines based upon notifications level criteria specified by the user for the host machines; consolidating multiple generated notifications into a fewer number of consolidated notifications and only sending consolidated notifications to the user; combination of criteria-based selection and notifications consolidation.

Abstract: A method in a first network device of performing a software update of a line card of a second network device without disruption to data traffic. The method includes causing a redundant control plane component of the second network device to be updated according to the software update. The method continues with causing the second network device to instantiate, based on the software update, a line card virtual machine (LC VM) as a redundant data plane component for the line card. The method further includes causing a third network device to forward data traffic to both the line card and the LC VM of the second network device, and causing the second network device to update the line card according to the software update while processing the received data traffic using the LC VM.

Abstract: An electronic device (such as a cellular telephone) automatically installs and personalizes updates to an applet on a secure element in the electronic device. In particular, when a digitally signed update package containing the update is received from an updating device (such as a server), the secure element identifies any previous versions of the applet installed on the secure element. If there are any previously installed versions, the secure element verifies the digital signature of the update package using an encryption key associated with a vendor of the secure element. Then, the secure element uninstalls the previous versions of the applet and exports the associated user data. Next, the secure element installs the update to the applet, and personalizes the new version of the applet using the user data.

Abstract: A field firmware upgrading method is adapted in a field firmware upgrading system having a computing device and a storage device. First, the computing device is boot up to a real-time operating system (RTOS), wherein the RTOS and a firmware of the storage device are communicated with each other via a driver. The RTOS sends reading commands to the firmware, such that the firmware performs a reading operation meeting a prefix proceeding, wherein the prefix proceeding defines an order which specific logic block addresses (LBAs) are read. After the firmware performs the reading operation meeting the prefix proceeding, the RTOS sends writing commands to the firmware, such that the firmware performs a writing operation meeting a specific writing proceeding to write an firmware image file into the storage device beginning at a target LBA defined by the specific writing proceeding.

Abstract: Automated systems and methods for assessing the urgency of installing a patch for a component of a software application are described. The systems and methods involve identifying a set of defective programming constructs of the component that are altered by the patch, collecting execution traces of programming constructs of the software application and programming constructs of the component in a context of application use, and evaluating the execution traces to determine whether one or more defective programming constructs of the component are invoked in the context of application use.

Abstract: Initialization status of a register to be used as a pointer to a reference data structure is used to determine how a stub is to be generated to access the reference data structure. The register is one type of pointer configuration to be used to access the reference data structure, which is used to resolve a symbol associated with a function of a program. An indication is obtained as to whether the register has been initialized with a reference data structure pointer. Based on obtaining the indication, a stub is generated that is to be used to access the function. The generating depends on whether the register has been initialized. If the register has not been initialized, then the stub is generated to include another type of pointer configuration to be used to access the reference data structure.

Abstract: A matching portion detector detects matching portions the respective contents of which match each other, in a source program. A similar portion detector detects, on the basis of the matching portions detected by the matching portion detector, similar portions each containing a part that matches a part of another similar portion and another part that does not match, and each satisfying a criterion, in the source program. A non-matching portion analyzer analyzes the similar portion detected by the similar portion detector, and outputs an index indicating a degree of similarity between the similar portion and another similar portion that partially match each other.

Abstract: Initialization status of a register to be used as a pointer to a reference data structure is used to determine how a stub is to be generated to access the reference data structure. The register is one type of pointer configuration to be used to access the reference data structure, which is used to resolve a symbol associated with a function of a program. An indication is obtained as to whether the register has been initialized with a reference data structure pointer. Based on obtaining the indication, a stub is generated that is to be used to access the function. The generating depends on whether the register has been initialized. If the register has not been initialized, then the stub is generated to include another type of pointer configuration to be used to access the reference data structure.

Abstract: A method for deploying a software program on a target computing device includes receiving late-binding configuration actions; combining the late-binding configuration actions with a target computing device-specific model to produce a final configuration model; and providing the final configuration model to the target computing device. The final configuration model is executed by the target computing device to configure the target computing device with the software program.

Abstract: An artifact manager generates an abstraction for artifacts and repositories in a deployment platform such that the artifacts may be located uniformly and securely in each deployment environment during the deployment process. The described system includes a release automation platform having a release pipeline which is responsible for deploying build artifacts into multiple deployment environments, testing the build artifacts thoroughly in each environment, and follow organization-specific approval processes to promote the build artifacts to a next deployment environment.

Abstract: At least one application is received from a user. The at least one application is stored on a communication platform. A catalog is received. The catalog includes at least one service. Each service of the at least one service is associated with a platform. An indication of a selection, from the user, is received. The selection comprises a first service associated with a first platform, and a second service associated with a second platform. The first service stores the at least one application from the user. The second service runs the at least one application from the user. Responsive to receiving the indication, the at least one application is deployed to the indicated first platform. Additionally, responsive to receiving the indication, a service bridge from the communication platform to the second platform is deployed. The at least one application is run, on the first platform utilizing the service bridge.

Abstract: A processor is described having an instruction execution pipeline. The instruction execution pipeline has an instruction fetch stage to fetch an instruction specifying multiple target resultant registers. The instruction execution pipeline has an instruction decode stage to decode the instruction. The instruction execution pipeline has a functional unit to prepare resultant content specific to each of the multiple target resultant registers. The instruction execution pipeline has a write-back stage to write back said resultant content specific to each of said multiple target resultant registers.

Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.

Abstract: A computation method includes: obtaining one or more first performance values of one or more instructions in a specific code for each of a plurality of first combinations of behavior result of a cache memory when a plurality of accesses to a memory area are executed; obtaining a second combination of behavior result of the cache memory when the plurality of accesses are executed based on an execution result of behavior simulation of the cache memory for a case where a processor executes a program including the specific code; and computing, by a computer, a third performance value when the processor executes the specific code based on one or more second performance values of the one or more instructions corresponding to the second combination among the one or more first performance values when the second combination is included in the plurality of first combinations.

Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.

Abstract: A data processing apparatus and method for accessing operands stored within a set of registers. Instruction decoder circuitry, responsive to program instructions, generates register access control signals identifying for each program instruction which registers in the register set are to be accessed by the processing circuitry when performing the processing operation specified by that program instruction. The set of registers are logically arranged as a plurality of register groups, with each register in the set being a member of more than one register group. Each program instruction includes a register specifier field, and instruction decoder circuitry is responsive to each program instruction to determine a selected register group, and to determine one or more selected members of that selected register group. The instruction decoder circuitry then outputs register access control signals identifying the register corresponding to each selected member of the selected register group.

Abstract: Embodiments of the present invention relate to fast and conditional data modification and generation in a software-defined network (SDN) processing engine. Modification of multiple inputs and generation of multiple outputs can be performed in parallel. A size of each input or output data can be large, such as in hundreds of bytes. The processing engine includes a control path and a data path. The control path generates instructions for modifying inputs and generating new outputs. The data path executes all instructions produced by the control path. The processing engine is typically programmable such that conditions and rules for data modification and generation can be reconfigured depending on network features and protocols supported by the processing engine. The SDN processing engine allows for processing multiple large-size data flows and is efficient in manipulating such data. The SDN processing engine achieves full throughput with multiple back-to-back input and output data flows.

Abstract: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.

Abstract: In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

Abstract: An apparatus for processing instructions includes a mapping unit comprising a plurality of mappers wherein each mapper of the plurality of mappers maps a logical sub-register reference to a physical sub-register reference, a decoding unit configured to receive an instruction and determine a plurality of logical sub-register references therefrom, and an execution unit. The mapping unit may be configured to distribute the plurality of logical sub-register references amongst the plurality of mappers according to at least one bit in the instruction and provide a corresponding plurality of physical sub-register references. The execution unit may be configured to execute the instruction using the plurality of physical sub-register references. Corresponding methods are also disclosed herein.

Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.

Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.

Abstract: A system, method, and computer program product for generating executable code for performing large integer operations on a parallel processing unit is disclosed. The method includes the steps of compiling a source code linked to a large integer library to generate an executable file and executing the executable file to perform a large integer operation using a parallel processing unit. The large integer library includes functions for processing large integers that are optimized for the parallel processing unit.

Abstract: Embodiments of the present invention may include a data processing system comprising a processing execution block to execute instructions stored in an instruction queue, a programmable hardware accelerator, and a controller programmed to monitor the instruction queue to detect a first type of instructions stored in the instruction queue, reprogram the programmable hardware accelerator to execute the first type of instructions, and transmit the first type of instructions to the programmable hardware accelerator to be executed.

Abstract: A sensor having a control and evaluation unit (2) and a memory unit (4), wherein an application program (6) for parameterizing and/or diagnosis is provided for the sensor (1), wherein an HTML description (8) is stored in the memory unit (4) wherein the HTML description (8) includes a bootstrap loading mechanism (10), wherein the bootstrap loading mechanism (10) is configured to transfer the application program (6) into a browser (12) on an end device (14) and the application program (6) can be started in the browser (12).

Abstract: A method, computer program product, and computing system for initiating a computing device includes setting a master reboot flag to no reboot required. A first software component in an initiation component stack is executed. Upon completing execution of the first software component, a determination is made concerning whether the computing device requires: an immediate reboot, a deferred reboot, or no reboot.

Abstract: A start-up control device includes a processor that executes a procedure. The procedure includes: acquiring data relating to communication processing when communication connection of plural data processing devices is initiated; and based on the acquired data relating to communication processing, controlling start-up of the plural data processing devices such that a data processing device that transmitted a response to a request for the connection is started-up earlier than a data processing device that transmitted the request.

Abstract: The present disclosure describes apparatuses and techniques for patching boot code of read-only memory (ROM). In some aspects, execution of boot code from a ROM is initiated to start a boot process of a device. Execution of the boot code from the ROM is then interrupted to enable execution of other boot code, such as corrected boot code or additional boot code, from another memory. Once the other boot code is executed, execution of the boot code from the ROM is resumed to continue booting the computing device. By so doing, the corrected boot code or additional boot code can be executed during the boot process effective to patch the boot code stored in the ROM.

Abstract: A method or system comprises reading content of a plurality of system files from storage media of a storage device, generating a master storage device system file, and storing the master storage device system file on the storage media at a master system file location. The location of the master system file is provided to boot firmware or hardware. As a result, when the system boots up, the master system file is read into a temporary cache.

Abstract: In accordance with embodiments of the present disclosure, a method may include during boot of an information handling system, obtaining from a management controller integral to the information handling system information regarding resource requirements for one or more peripheral devices communicatively coupled to the one or more processor sockets integral to the information handling system and the management controller. The method may also include determining whether a default allocation of resources for the one or more peripheral devices among the one or more processor sockets by a basic input/output system integral to the information handling system satisfies the resource requirements. The method may further include, in response to determining the default allocation does not satisfy the resource requirements, rebalancing resources among the one or more processor sockets to satisfy the resource requirements prior to enumeration of the one or more peripheral devices.

Abstract: Technologies for managing image discovery includes a server controller to cause a server to enter a pre-boot state. The server controller communicates with the server while the server maintains the pre-boot state to determine identification data of the server in response to a transitioning the server to the pre-boot state. The server controller identifies a boot image of the server based on the identification data of the server and associates the server with the identified boot image.

Abstract: Architecture that includes an asynchronous library which remembers the synchronization context that initiated an asynchronous method call and when the request is completed, the library restores the synchronization context of the calling thread before executing a callback. This ensures that the callback executes on the same thread as the original asynchronous request. The callback to the asynchronous operation that asynchronous library provides automatically “jumps threads” to maintain thread affinity.

Abstract: A method for page view switching is provided. The method includes detecting a view switching operation in an application interface by a user to switch from a current view to a target view. The method also includes destroying the current view corresponding to the view switching operation and creating a view object corresponding to the target view in the view switching operation by calling a view controller class. Further, the method includes assigning values to the view object through a view controller and displaying the view object with the assigned values on the application interface to display the target view to the user.

Abstract: A method and system for applying a system change in an automated fashion and verifying the correct operation of a computing device after the system change includes allowing the computing device an opportunity to at least temporarily apply the system change, determine whether the system change is successful, and discard the system change if not successful, using operating system and BIOS components.

Abstract: A method of manufacturing an aircraft. A plurality of documents, each comprising corresponding unstructured text and each being from a different source, is received at a processor, a particular document being in the plurality of documents. The particular document is selected by the processor based on a policy. The corresponding unstructured text for the particular document is converted by the processor into a structured language. The structured language is compiled by the processor into rules for a rules engine comprising software stored on a non-transitory computer readable storage medium. The rules for the rules engine are parsed by the processor into a set of rules. The aircraft is constructed according to the set of rules.

Abstract: A system includes a dynamic configuration property database for a computer-based service. The system executes an application program interface that couples the computer-based service to the database. The system reads a dynamic configuration property from the database while the computer-based service is executing and without requiring the computer-based service to cease execution. The system also provides the dynamic configuration property to the computer-based service while the computer-based service is executing such that the computer-based service can use the configuration property without requiring the computer-based service to cease execution and without having to restart the computer-based service.

Abstract: A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The virtual adapter is for use by a guest of the host system in performing data input and output. The activating activates the virtual adapter absent involvement of the guest. Based on activating the virtual adapter, the control component obtains configuration information of the activated virtual adapter from the physical adapter, the configuration information generated based on the activating. The control component ascertains a configuration of the activated virtual adapter based on the obtained configuration information.

Abstract: Approaches to enable the configuration of computing resources for executing virtual machines on behalf of users to be cryptographically attested to or verified. When a user requests a virtual machine to be provisioned, an operator of the virtualized computing environment can initiate a two phase launch of the virtual machine. In the first phase, the operator provisions the virtual machine on a host computing device and obtains cryptographic measurements of the software and/or hardware resources on the host computing device. The operator may then provide those cryptographic measurements to the user that requested the virtual machine. If the user approves the cryptographic measurements, the operator may proceed with the second phase and actually launch the virtual machine on the host. In some cases, operator may compare the cryptographic measurements to a list of approved measurements to determine whether the host computing device is acceptable for hosting the virtual machine.

Abstract: The current document is directed to methods and subsystems for communication between virtualization layers and guest operating systems. A hardware baseboard management controller (“BMC”) provides an out-of-band communications link and management interface to a computer system that can be accessed by a system administrator through a remote console. A virtualization layer may provide a virtualized BMC (“vBMC”) that provides a data-and-command-exchange medium between a guest operating system and the virtualization layer. The virtualization layer may transmit commands, query status and configuration information, and transfer data through this data-and-command-exchange medium to the guest operating system.

Abstract: An installer installing an operating system on a host computer system detects that the operating system is to be run under a hypervisor, and causes at least one configuration parameter of the operating system to be adjusted based on the hypervisor. A migration tool migrating a virtual machine from one hypervisor to another hypervisor, identifies the types of the two hypervisors, the operating system used by the virtual machine, and causes at least one configuration parameter of the operating system to be adjusted based on the target hypervisor.

Abstract: Three embodiments of one-way cross-domain systems for transferring information from a client in a first security domain to a server in a second separate security domain are disclosed. In addition, three embodiments of bilateral cross-domain systems for transferring first information from a client in a first security domain to a server in a second separate security domain and second information from the server in the second separate security domain to the client in the first security domain are also disclosed. Each of the one-way and bilateral cross-domain systems is based upon a single computer server which employs a number of virtual machines to implement send and receive servers. The single computer server also implements one (for the one-way cross-domain systems) or two (for the bilateral cross-domain systems) virtual one-way data links in either virtual machines or within the hypervisor portion of the operating system.

Abstract: A virtualization management component of a particular host at a virtualized computing determines that a packet duplication phase of a migration of a virtual machine from a source host to the particular host has begun. The virtualization management component detects that a migrated version of the virtual machine, instantiated at the particular virtualization host, has generated a baseline packet directed to a destination address. The virtualization management component sends a first encapsulation packet comprising the baseline packet to an encapsulation intermediary associated with the destination address. The virtualization management component sends a second encapsulation packet comprising the baseline packet to the source virtualization host, with a directive to forward the second encapsulation packet to the encapsulation intermediary.

Abstract: An example method for secure virtual machine access to a protected virtual machine function includes storing a first virtual machine function instruction, which is executable to configure access privileges of a guest according to a trampoline view, as a last instruction on a first trampoline page. The method also includes storing a clear interrupt flag instruction as a first instruction on a second trampoline page. The method further includes storing a second virtual machine function instruction, which is executable to configure access privileges of the guest according to a protected view, as a last instruction on the second trampoline page. The method also includes in response to detecting an extended page fault violation while the trampoline view is active, clearing the interrupt flag of the guest and entering execution on an instruction following the clear interrupt flag instruction on the second trampoline page.

Abstract: The method includes post copy migrating a guest virtual machine from a migration source host to a migration target host, executing the instruction stream of the guest virtual machine on the migration target host, and determining, by the migration target host, when the guest virtual machine encounters the page fault. When the guest virtual machine encounters the page fault, the method includes requesting, by the migration target host, the not-present page from the migration source host for loading on the migration target host, and emulating, on an emulator executing on or in communication with the migration target host, continued execution of the instruction stream of the guest virtual machine. The method also includes identifying, by the emulator, future page references to future pages from the emulated continued execution of the instruction stream, and requesting the future pages from the migration source host in parallel with the not-present page request.

Abstract: An electronic official document (EOD) processing method, wherein a work action set consisting of N work actions is defined, comprising: (1) selecting M work actions from the work action set, setting a corresponding working user for each selected work action, and sequencing all selected work actions into a workflow by order of execution; (2) inputting a to-be-processed EOD as a first EOD into the first work action in the workflow; (3) starting an integer i from 1 and increasing the integer i by 1 each time until the integer i reaches M, and executing the following every time the integer i is increased: the working user corresponding to the i-th work action performs an operation specified in the i-th work action on the No. i EOD, and stores the processing result as a No. i+1 EOD; and (4) outputting the No. M+1 electronic document as the processing result.

Abstract: A process operating method is provided. The method includes determining an execution application, generating an application process for the determined execution application, loading the determined execution application from a secondary memory to the generated application process, generating a platform child process that is a child process of a platform process, and loading a predetermined sub-module of the application to the platform child process.