Abstract: A system may obtain an executable code segment of program code. The executable code segment may be associated with an emitter, and the program code, when executed, may be associated with a plurality of execution states. Each execution state, of the plurality of execution states, may correspond to a state of execution at a point in the execution of the program code that causes an event, of the plurality of events. The system may execute the executable code segment. The system may receive, from the emitter and based on executing the executable code segment, a program state corresponding to the particular execution state. The emitter may emit the information based on a particular event caused by executing the executable code segment. The system may collect the program state and information describing the particular event.

Abstract: A circuit may be configured to store data to a reserved zone of a non-volatile solid state memory (NVSSM) in a log structured manner and to use information stored in the reserved zone to restore data as needed. In some embodiments, a reserved area of a NVSSM may include die from one or more non-volatile memory modules, which can be divided into blocks and the blocks can be combined to form frames. In some examples, the frames may contain frame headers that can contain a unique identifier which can indicate which frame is to be used to restore data structures, such as during power up or for other restore events.

Abstract: A vehicle control device for supplementing/changing the functionality of a vehicle control device. A vehicle control device is created having at least one processor, a memory coupled to the processor, a plurality of application modules, and at least one communication interface for interchanging data with other vehicle control devices or an external vehicle device. Also disclosed is a method for supplementing/changing the functionality of a vehicle control device.

Abstract: Improved techniques for storing data involve storing compressed data in blocks of a first AU size and storing uncompressed data in blocks of a second AU size larger than the first AU size. For example, when a storage processor compresses a chunk of data, the storage processor checks whether the compressed chunk fits in the smaller AU size. If the compressed chunk fits, then the storage processor stores a compressed chunk in a block having the smaller AU size. Otherwise, the storage processor stores the uncompressed chunk in a block having the larger AU size. Advantageously, the improved techniques promote better disk and cache utilization, which improves performance without disrupting block mapping.

Abstract: A device including a network interface, a memory, and at least one processor is provided. The memory may include a random access memory (RAM) and nonvolatile memory. The processor may be coupled to the memory and coupled to the network interface and configured to designate an uninitialized section of RAM, generate a network device identifier for the device using data from the uninitialized section of RAM, store the network device identifier in a nonvolatile memory, and assign the network device identifier to the device. The at least one processor may be further configured to generate the network device identifier using the data from the uninitialized section of RAM as a seed for a pseudorandom number generator.

Abstract: A method of operating a controller includes receiving write data having chunks from a host, assigning each of finger prints to each of the chunks, counting the number of duplications of each of the finger prints, and changing a physical address assigned to each of first finger prints among the finger prints based on a count value of each of the finger prints based on a count value of each of the finger prints, and the physical address is assigned by a flash translation layer (FTL).

Abstract: An application programming interface (API) may include an initiator configured to initiate a guest safepoint via an action represented in a guest language executed on a virtual machine, provide a safepoint action to a group of guest threads, synchronize the guest threads such that each guest thread in the group executes the safepoint action once all guest threads in the group enter the guest safepoint, and synchronize the guest threads such that each guest thread in the group exits the guest safepoint once all guest threads in the group complete execution of the safepoint action. The API may also include a guest configured to determine whether a guest safepoint is initiated, enter the guest safepoint, execute the safepoint action while execution of a guest action is paused, and exit the guest safepoint and resume execution of the guest action once the safepoint action completes execution.

Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

Abstract: A separate distributed buffer cache system may be implemented for a storage client of a distributed storage system. Storage I/O requests may be sent from a storage client to one or more buffer cache nodes in a distributed buffer cache system that maintain portions of an in-memory buffer cache to which the requests pertain. The distributed buffer cache system may send the write requests on to the distributed storage system to be completed, and in response to receiving acknowledgements from the storage system, sending a completion acknowledgement back to the storage client. Buffer cache nodes may update buffer cache entries for received requests such that they are not available for reads until complete at the distributed storage system. For read requests where the buffer cache entries at the buffer cache node are invalid, valid data may be obtained from the distributed storage system and sent to the storage client.

Abstract: Methods and systems are presented for allocating CPU cycles among processes in a storage system. One method includes operations for maintaining segments in a first memory, each segment including blocks, and for maintaining a block temperature for each block in a second memory. The first memory is a read-cache where one segment is written at a time, and each block is readable from the first memory without reading the corresponding complete segment. The block temperature is based on the frequency of access to the respective block, and a segment temperature is based on the block temperature of its blocks. Additionally, the segment with the lowest segment temperature is selected for eviction from the second memory, and blocks in the selected segment with a block temperature greater than a threshold temperature are identified. The selected segment is evicted, and a segment with the identified blocks is written to the first memory.

Abstract: A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

Abstract: A system includes a database that stores data on one or more memory devices and a business object layer that receives a request for data associated with a user stored on the database. The system includes a first cache that reads and stores the requested data from the database in response to the request from the business object layer, where the first cache is partitioned into different segments and the different segments are stored across multiple different computing devices. The system includes a second cache that reads and stores the requested data from the first cache. The business object layer filters and applies business logic to the data before the second cache reads the requested data from the first cache. The second cache is stored on a single computing device that received the request. The business object layer delivers the requested data from the second cache.

Abstract: The present invention provides a dynamic set associative cache apparatus for a processor. When read access occurs, the apparatus first determines a valid/invalid bit of each cache block in a cache set to be accessed, and sets, according to the valid/invalid bit of each cache block, an enable/disable bit of a cache way in which the cache block is located; then, reads valid cache blocks, compares a tag section in a memory address with a tag block in each cache block that is read, and if there is a hit, reads data from a data block in a hit cache block according to an offset section of the memory address.

Abstract: In accordance with an embodiment, described herein is a system and method for compacting a pseudo linear byte array, for use with supporting access to a database. A database driver (e.g., a Java Database Connectivity (JDBC) driver) provides access by software application clients to a database. When a result set (e.g., ResultSet) is returned for storage in a dynamic byte array (DBA), in response to a database query (e.g., a SELECT), the database driver determines if the DBA is underfilled and, if so, calculates the data size of the DBA, creates a static byte array (SBA) in a cache at the client, compacts the returned data into the SBA, and stores the data size as part of the metadata associated with the cache. In accordance with an embodiment, the DBA and the SBA can use a same interface for access by client applications.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.

Abstract: A system on chip (SoC) includes a central processing unit (CPU), an intellectual property (IP) block, and a memory management unit (MMU). The CPU is configured to set a prefetch direction corresponding to a working set of data. The IP block is configured to process the working set of data. The MMU is configured to prefetch a next page table entry from a page table based on the prefetch direction during address translation between a virtual address of the working set of data and a physical address.

Abstract: The present disclosure relates to sharing a context on a coherent hardware accelerator among multiple processes. According to one embodiment, in response to a first process requesting to create a shared memory space, a system creates a shared hardware context on the coherent hardware accelerator and binds the first process and the shared memory space to the hardware context. In response to the first process spawning one or more second processes, the system binds the one or more second processes to the shared memory space and the hardware context. Subsequently, the system performs one or more operations initiated by the first process or one of the one or more second processes on the coherent hardware accelerator according to the bound hardware context.

Abstract: A method of enhancing a refresh PCI translation (RPCIT) operation to refresh a translation lookaside buffer (TLB) includes determining, by a computer processor, a request to perform at least one RPCIT instruction for purging at least one translation from the TLB. The method further includes purging, by the computer processor, the at least one translation from the TLB in response to executing the at least one RPCIT instruction. The computer processor selectively performs a synchronization operation prior to completing the at least one RPCIT instruction.

Abstract: Disclosed here are methods, systems, paradigms and structures for deleting shared resources from a cache in a multi-threaded system. The shared resources can be used by a plurality of requests belonging to multiple threads executing in the system. When requests, such as requests for executing script code, and work items, such as work items for deleting a shared resource, are created, a global sequence number is assigned to each of them. The sequence number indicates the order in which the requests and work items are created. A particular work item can be executed to delete the shared resource if there are no requests having a sequence number lesser than that of the particular work item executing in the system. However, if there is at least one request with a sequence number lesser than that of the particular work item executing, the work item is ignored until the request completes executing.

Abstract: A page replacement algorithm is provided. An idle range of memory pages is determined based, at least in part, on indications of references to memory pages in the idle range of memory pages, wherein the idle range of memory pages is a set of one or more memory pages. A first memory page is identified in the idle range of memory page for paging out of memory. The first memory page is identified based, at least in part, on indications of modifications to the memory pages. The first memory page is paged out of memory.

Abstract: An approach is provided for suggesting data for deletion from an electronic data storage medium. An external device detects initiation of transfer of data from first storage medium to second storage medium. Next, the external device determines an available storage in the second storage medium for the data. Then, the external device generates a list to suggest content for deletion within the second storage medium to accommodate the data.

Abstract: Described are data replication techniques. Y cycles of writes directed to a first storage device of a first data storage system are collected, Y>2. Each of the Y cycles denotes writes directed to the first storage device at an occurrence of a fixed time interval. Writes of cycle N?1 directed to the first storage device are transmitted from the first data storage system to a second data storage system. Writes of cycle N?2 are applied to a second storage device. An acknowledgement regarding cycle N?1 is sent from the second data storage system to the first data storage system responsive to determining that the writes of cycle N?1 directed to the first storage device have been received by the second data storage system and that the writes of cycle N?2 directed to the first storage device have been applied to the second storage device.

Abstract: Systems, apparatuses and methods may provide for identifying a stack pointer associated with a sequence of code being executed on a computing system and counting a number of exchange updates to the stack pointer. Additionally, a hardware interrupt may be generated if the number of exchange updates reaches a threshold. In one example, the hardware interrupt is a performance monitoring interrupt.

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Abstract: A PCIe bus adapted for cross clock compensation of asynchronous clocks includes one or more PHY data ports provided in a PHY layer having a transmit clock (TCLK) for timing data transmitted to a peripheral device and a receive clock (RCLK) for timing data received from the peripheral device, one or more media access control (MAC) ports provided in a MAC layer having an interface clock (PCLK) for timing data transmitted to the PHY layer and data received from the PHY layer, wherein the PCLK and one or both of the TCLK and the RCLK are asynchronous, and one or more backpressure ports at an interface between the PHY layer and the MAC layer for controlling reading and writing of one of the PHY layer and the MAC layer. In some aspects, the PCLK frequency is set to be always greater than a maximum frequency of the RCLK and the TCLK.

Abstract: A master-slave system includes a master unit having a digital output for providing a signal or a serial signal sequence of signals, and at least two slave units. Each of the slave units includes at least one digital serial memory having a size of one bit, and each slave unit includes an input and an output. The slave units are serially connected to one another via the inputs and the outputs via a signal line (5). The output of a first slave unit is connected via the signal line to the digital output of the master unit. The master slave system is configured so that a signal supplied by the digital output is detected at the input of the slave unit, in order to raise the address of the corresponding slave unit in each case by the value “1”, to store the signal change in the memory and to output a signal corresponding to the content of the memory at the output of the memory.

Abstract: According to an embodiment, a circuit for using a shared memory is provided, which has a plurality of function circuits, a bus, an arbitrator, and a communication measuring device. Each of a plurality of the function circuits performs a prescribed calculation. The bus communicates an input/output signal of each of the function circuits. The arbitrator assigns a use right of the bus to each of the function circuits. The communication measuring device measures a communication time of each of the function circuits, determines whether or not the measured communication time is within a range of a reference communication time set for each of the function circuits, and stores this determination result in a determination result storage device accessible from outside.

Abstract: According to one embodiment, there is provided a bus access controller including a memory, multiple buffers, and an issuance circuit. Information necessary for bus access can be set in the memory. The multiple buffers store information set in the memory. The issuance circuit is connected to a bus. The issuance circuit issues a bus-access instruction, according to information stored in a buffer selected from among the multiple buffers in response to a request.

Abstract: Systems and techniques for managing network processing on a central processing unit including multiple cores are described. Techniques may determine respective resource utilization for one or more processing cores. In one example resource utilization for cores may be determined based on one or more of task utilization time, processor load based on hardware interrupts, cycles spent on processing network packets, utilization based on software interrupts, and idle time. Interrupts may be steered to a core based on resource utilization.

Abstract: A method of providing access to first data stored at a first device to a second device, the first device storing the first data in a memory accessible to said second device. The method comprises, at a control element distinct from each of said first and second devices accessing the stored first data in said memory accessible to said second device before said first data is accessed in said memory accessible to said second device by said second device.

Abstract: An interface unit is provided for the arrangement between a bus system, to which a processor unit and a data memory are connectable, and a data transporting unit, in particular a network processor, are described. The interface unit carries out a direct memory access to the data memory as a function of an identifier (chid) previously agreed upon between an application and the data transporting unit.

Abstract: In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB3).

Abstract: An electronic device coupling system includes a master electronic device and a plurality of slave electronic devices which are each independently connected to the master. The master electronic device includes connecting module and identity module, the slave electronic device includes coupling module and identify module. The identity module stores identity information of each slave device and sends out serially all the identity information. The identify module confirms correspondence of the identity information to a selected slave device. The connecting module has a plurality of matching codes corresponding to each connecting port and each group address code. The master device can couple to a slave device when the identity information corresponds to a selected slave device. The coupling module is couplable to the connecting module according to the matching codes. An electronic device coupling method is further provided.

Abstract: An extensible host controller applied to a host includes a universal serial bus (USB) module, a control unit, and a peripheral component interconnect express (PCIE) bus. The USB module includes a USB unit and a predetermined unit. The PCIE bus is coupled to the control unit, wherein the PCIE bus supports a USB mode and a predetermined mode. When a first host with a first extensible host controller is connected to the USB module, the control unit makes the host utilize the USB mode and the USB unit, or the predetermined mode and the predetermined unit to communicate with the first host according to a determination way.

Abstract: The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices.

Abstract: A configurable sponge function engine. The configurable engine includes a state register having bitrate and capacity sections, each having a variable size, where a sum of the bitrate and capacity sizes is fixed. A controller generates a bitrate size indication. A configurable message processor receives an input message from an input bus, receives the size indication, fragments the input message into fragmented blocks of a size specified by the size indication, and converts the blocks to a bus width of the bitrate and capacity sizes. An iterative calculator receives the blocks, performs iterative processing operations on the blocks, and stores a result of each operation in the state register overwriting a previous register value. An output adaptor receives a value stored in the state register after the block corresponding to the end of the input message is processed and outputs the register value converted to have an output bus width.

Abstract: Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data.

Abstract: Methods and systems are disclosed relating to in-vehicle entertainment, information presentation, and/or processing. Aspects of multimedia in-vehicle entertainment systems that may incorporate removable and/or portable tablet-type computing devices are described. In certain configurations, a hinged tablet computer carrier includes guide rails into which a portable tablet computer may slide while in an open position, and which can hinge into a closed or locked position that holds the tablet computer in place, positions it for viewing, and effects mechanical and electrical coupling of the tablet computer with other components of the in-vehicle entertainment system. Exemplary placement could include headrest, seatback, overhead, or in-dash mounting. Hinging or sliding could be vertical or horizontal. Various other mechanical, electronic, and electro-mechanical aspects of the methods and systems are described.

Abstract: A communication device includes a communication unit configured to communicate with a LAN, and IO ports connectable to a manufacturing apparatus, and a controller. The IO ports are configured and/or programmed to exchange ON/OFF signals including multiple bits with the manufacturing apparatus. The controller is configured and/or programmed to receive communication requests from communication destinations via the LAN, store network addresses of communication destinations and IO port designations, change a value of the ON/OFF signals of designated IO ports in accordance with requests from communication destinations, and transmit the ON/OFF signals of designated IO ports to communication destinations via the communication unit and the LAN in accordance with requests from the communication destinations.

Abstract: A data processing system comprising a host computer system and a network interface device for connection to a network, the host computer system and network interface device being coupled together by means of a data bus, and: the network interface device comprising: a controller unit having a first data port for connection to a network, a second data port, and a data bus interface connected to said data bus, the controller unit being operable to perform, in dependence on the network endpoints to which data packets received at the network interface device are directed, switching of data packets between the first and second data ports and the data bus interface; and an accelerator module having a first medium access controller coupled to said second data port of the controller unit and a processor operable to perform one or more functions in hardware on data packets received at the accelerator module, the said first medium access controller being operable to support one or more first network endpoints; the host

Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Abstract: A method maintaining a fixed QoS for a PCIe device accessed by multiple hosts includes; receiving commands from the hosts in PCIe function queues of the PCIe device, fetching the commands from the PCIe function command queues, queuing the commands according to a command arbitration policy established for the PCIe device, storing the queued commands in an internal memory of the PCIe device, retrieving the queued commands from the internal memory in a sequence determined by applying a calculated QoS to at least one of the queued commands, and allocating PCIe device resources based on payload information corresponding to each one of the retrieved commands.

Abstract: Embodiments are directed to a system comprising: a first device, and a second device coupled to the first device via an interface that provides a handshaking algorithm that ensures that only one of the first device and the second device initiates communication over the interface at a given point in time.

Abstract: A computing device includes a processor to perform a coefficient calculation control for (i) displaying a mathematical formula including a coefficient on a display unit, (ii) displaying the coefficient name, and (iii) receiving a coefficient value to calculate the mathematical formula; and a regression calculation control for storing numeric data sets of independent and dependent variables in a memory and calculating a value of a coefficient in a regression formula representing the relationship between the independent and dependent variables based on the numeric data sets. The coefficient calculation control performs a coefficient value displaying control for displaying the value of the coefficient in the regression formula calculated through the regression calculation control and performs a post-regression calculation control for using the regression formula as the mathematical formula to calculate the mathematical formula using the displayed coefficient value.

Abstract: The present invention describes a new method for implementing highly available data-parallel-operations on a computational grid. This new method provides high availability after a server fails or the grid experiences a partial network failure. The present invention invokes the data parallel operation's method on selected objects stored in partitions within a highly available distributed cache. It thereby takes advantage of the use of highly available data partitions implemented by the distributed cache as a means for reliably tracking the progress of method invocations within a data parallel operation even after a server or network failure occurs. Using the cache's partitions as the basis for tracking enables the present invention's method to restart method invocations and thereby ensure completion of the data-parallel operation. It also uses a completion object within the cache to ensure that completion of the data parallel operation is detected and reported in a highly available manner.

Abstract: A memory appliance system is described and includes a processor coupled to one or more communication channels with a command interface, wherein the processor is configured for communicating commands over the communication channels. A plurality of Smart Memory Cubes (SMCs) is coupled to the processor through the communication channels. Each of the SMCs includes a controller that is programmable, and a plurality of memory devices. The controller is configured to respond to commands from the command interface to access content stored in one or more of the plurality of memory devices and to perform data operations on content accessed from the plurality of memory devices.

Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Abstract: Systems and methods for determining when to turn off an engine are described. The systems and methods may identify when an amount of carboxyhemoglobin exceeds a predetermined threshold; and monitor the amount of carboxyhemoglobin for a period of time. The systems and methods may determine when the amount of carboxyhemoglobin exceeds the predetermined threshold during the time period; and turn off the engine when the amount of carboxyhemoglobin exceeds the predetermined threshold during the time period.

Abstract: A folded butterfly module performs a radix-22 butterfly operation, and includes: a buffer operable to store first and second to-be-stored data and output first and second stored data; a first multiplexer operable to output one of the second stored data and input data as first selection data; a butterfly operator performing a radix-2 butterfly operation on the first stored data and the first selection data to generate operation data and the second to-be-stored data; a second multiplexer operable to output one of the input data and the operation data as the first to-be-stored data; a third multiplexer operable to output one of the operation data and the second stored data as second selection data; and a multiplier generating output data that equal a product of the second selection data and twiddle data.