Abstract: A substrate fixing device includes a baseplate, an electrostatic chuck, and an insulating layer interposed between the baseplate and the electrostatic chuck. The insulating layer includes a heating element formed of a first material and a wiring line connected in series to the heating element. The wiring line includes a first conductive layer formed of the first material and a second conductive layer joined onto the first conductive layer. The second conductive layer is formed of a second material having a resistivity lower than the resistivity of the first material.

Abstract: Precision screen printing is described that is capable of sub-micron uniformity of the metallization materials that are printed on green sheet ceramic. In some examples, puck is formed with electrical traces by screen printing a paste that contains metal on a ceramic green sheet in a pattern of electrical traces and processing the printed green sheet to form a puck of a workpiece carrier. In some example, the printing includes applying a squeegee of a screen printer to the printed green sheet in a squeegeeing direction while the green sheet is on a printer bed of the screen printer. The method further includes mapping the printer bed at multiple locations along the squeegeeing direction, identifying non-uniformities in the printer bed mapping, and modifying a printer controller of the screen printer to compensate for mapped non-uniformities in the printer bed.

Abstract: According to one embodiment, an electrostatic chuck includes a ceramic dielectric substrate including a sealing ring provided at a peripheral edge portion of the ceramic dielectric substrate, and an electrode layer including a plurality of electrode components. An outer perimeter of the ceramic dielectric substrate is provided to cause a spacing between the outer perimeter of the ceramic dielectric substrate and an outer perimeter of the electrode layer to be uniform. The spacing between the outer perimeter of the electrode layer and the outer perimeter of the ceramic dielectric substrate is narrower than a spacing of the electrode components. A width of the sealing ring is not less than 0.3 millimeters and not more than 3 millimeters. A width where the electrode layer overlaps the sealing ring is not less than ?0.7 millimeters and not more than 2 millimeters.

Abstract: Carrier onto which a wafer can be temporarily bonded. The carrier comprises a plate shaped laminate. The plate shaped laminate comprises a first layer. The first layer comprises a metal foil or a metal sheet. The plate shaped laminate comprises a second layer comprising a porous metal medium with three-dimensional open pores. The porous metal medium comprises metal fibers. The first layer is permanently bonded to the porous metal medium thereby closing the pores of the porous metal medium at the side where the first layer is located.

Abstract: The transfer of devices or device components from a carrier substrate to a further carrier substrate or to a plurality of further carrier substrates can be performed with little effort (few transfer steps) to the at least one further carrier substrate. The method comprises producing first devices on the first carrier substrate in a two-dimensional grid. It comprises defining positions on the second carrier substrate on the basis of the two-dimensional grid for at least some of the first devices. It comprises releasing a plurality of the first devices from the first carrier substrate while maintaining the two-dimensional grid. Finally, the plurality of first devices are applied to the second carrier substrate in the defined positions while maintaining the two-dimensional grid or a multiple thereof in at least one of the two directions.

Abstract: An apparatus for processing wafer-shaped articles comprises a rotary chuck having a series of contact elements surrounding a wafer-shaped article when mounted on the rotary chuck. A non-rotating plate is positioned interiorly of the series of contact elements. The plate includes a gas supply that is configured to supply gas so as to support a wafer-shaped article without contacting the non-rotating plate according to the Bernoulli principle.

Abstract: There is provided a substrate mounting method of brining a substrate close to a mounting table to mount the substrate on the mounting table by reducing a protrusion amount of a plurality of projections configured to protrude from a substrate-mounting surface of the mounting table and to support the substrate, the protrusion amount being defined to protrude from the substrate-mounting surface. The method includes: after at least a portion of the substrate is brought into contact with the substrate-mounting surface, halting an operation of bringing the substrate close to the mounting table; and after the halting the operation of bringing the substrate close to the mounting table, resuming the operation of bringing the substrate close to the mounting table.

Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

Abstract: A method includes forming a trench in a stack comprising a substrate, a buried oxide layer formed above the substrate, a semiconductor layer formed above the buried oxide layer and a hard mask layer formed above the semiconductor layer. A first liner is formed in the trench. A first oxide layer is formed in the trench. A diffusionless anneal process is performed to densify the first oxide layer. The first oxide layer is recessed to define a recess. A second oxide layer is formed in the recess.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: forming a dielectric layer on a semiconductor substrate; forming a functional layer on the dielectric layer; forming a hard mask layer on the functional layer; patterning the semiconductor substrate to form an opening on the semiconductor substrate, wherein the opening goes through the hard mask layer, the functional layer and extends into the dielectric layer; performing an oxidization process on side surfaces of the functional layer inside the opening to form oxide layers; performing a first process on the semiconductor substrate to remove a portion of the dielectric layer underneath the opening to expose the semiconductor substrate; and removing the oxide layers on the side surfaces of the functional layer to form a contact hole. The contact hole has a wider opening in the upper part than in the lower part.

Abstract: A copper or copper alloy is formed in a reflow enhancement layer lined opening present in an interconnect dielectric material layer. A ruthenium (Ru) or osmium (Os) doped copper or copper alloy cap is then formed via ion implantation and annealing in an upper portion of a copper or copper alloy present in the opening. The upper portion of the copper or copper alloy containing the ruthenium (Ru) or osmium (Os) doped copper or copper alloy cap can mitigate or even present prevent preferential loss of copper which can aid in lowering the interconnect resistance of the structure.

Abstract: The present invention provides a TFT structure and a repair method thereof, a GOA circuit. The TFT structure and the repair method thereof includes a source (10) having a plurality of independent U shape source branches (101). The drain (20) comprises a plurality strip drain branches (201). Each independent U shape source branch (101) is solely connected to a first metal line (30) with a connection part (103), and all the plurality of strip drain branches (201) are electrically coupled to a second metal line (40). The respective independent U shape source branches (101) and the corresponding strip drain branches (201) construct a plurality of independent source-drain conduction channels; as some independent U shape source branch (101) and the corresponding strip drain branch (201) are detected having a defect, the repair can be implemented by disconnecting the independent U shape source branch (101) and disconnecting the corresponding strip drain branch (201).

Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming an electrically-conducting connection in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.

Abstract: A method for producing a semiconductor body is disclosed. In an embodiment the method includes providing a semiconductor body, applying a first mask layer and a second mask layer to the semiconductor body and forming at least one second mask opening in the second mask layer and at least one recess in the semiconductor body in a region of the at least one first mask opening in the first mask layer, wherein the recess comprises a side face and a bottom face and the recess forms an undercut with the second mask opening, when viewed from the first mask opening. The method further includes applying a contact layer to the first mask layer and the bottom face of the at least one recess using a directional deposition method and applying a passivation layer to the side face of the at least one recess.

Abstract: A wafer processing method of dividing along a plurality of projected dicing lines set on the wafer includes a placing step of placing the wafer on a heating table with a tape interposed therebetween, the wafer having modified layers, from which to start to divide the wafer, formed therein at positions aligned with the projected dicing lines, the tape being applied to one surface of the wafer, and a dividing step of dividing the wafer on the heating table by heating with the heating table and thereafter cooling an exposed opposite surface in its entirety of the wafer with a cooing unit whereby the wafer starts being ruptured from the modified layers along the projected dicing lines due to a thermal shock caused by a temperature difference developed between the heated and cooled surfaces of the wafer.

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Abstract: Method for fabricating semiconductor device comprising: forming a dummy gate on a first nitrided oxide layer and a non-nitrided oxide layer; nitridizing an exposed section of the non-nitrided oxide layer to form a second nitrided oxide layer; forming an interlayer dielectric on the first nitrided oxide layer and the second nitrided oxide layer; removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening; removing the dummy gate from the non-nitrided oxide layer to form a second opening with a non-nitrided portion of oxide layer exposed in the second opening; removing the non-nitrided portion of the oxide layer; forming a first dielectric layer and first metal gate material in the first opening; and forming a second dielectric layer and second metal gate material in the second opening.

Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

Abstract: A method includes isolating a first and at least a second region on a semiconductor substrate, and forming one or more devices on each of the first and at least second regions. Forming the one or more devices includes forming at least one gate structures in each of the first and at least second regions on a first surface of the substrate, depositing a spacer over the gate structures in each of the first and the at least second regions and over the first surface of the substrate, etching horizontal portions of the spacer in the first region, growing epitaxial portions in the first region in alignment with said at least one gate structure in the first region, oxidizing exposed surfaces of the epitaxial portions in the first region, and repeating the etching, growing and oxidizing steps for the at least second region.

Abstract: A cartridge in an oven enclosure includes a pre-heating feature for an incoming purge gas before the purge gas enters the space around an optical component, such as a nonlinear optical crystal, in an oven cell. The incoming purge gas can be pre-heated as it travels along a gas pathway around a cartridge. The cartridge can include a heater. The oven enclosure can have two windows positioned such that a laser beam can enter through one of the windows, pass through the optical component, and exit through another of the windows. A second harmonic beam can be generated with the optical component.

Abstract: A test apparatus includes a lighting unit radiating light on a to-be-tested object having a light transmitting resin containing a light conversion material; a camera unit obtaining an image of the to-be-tested object while the light transmitting resin is emitted by receiving light emitted by the lighting unit; and a controller determining whether the to-be-tested object is defective by calculating gray values from the image obtained by the camera unit.

Abstract: A substrate processing apparatus includes: a reaction tube configured to accommodate a substrate holder holding a plurality of substrates and process a substrate held on the substrate holder; a heating unit installed outside the reaction tube and configured to heat an inside of the reaction tube; a protection tube installed to extend in a vertical direction in contact with an outer wall of the reaction tube; an insulating tube disposed inside the protection tube and having through-holes extending in a vertical direction; a thermocouple having a thermocouple junction provided at an upper end thereof, and thermocouple wires joined at the thermocouple junction and inserted into the through-holes of the insulating tube; a gas supply unit configured to supply a gas, for processing a substrate accommodated in the reaction tube, into the reaction tube; and an exhaust unit configured to exhaust a gas from the reaction tube.

Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

Abstract: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.

Abstract: A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.

Abstract: A leadframe and air cavity packages formed using the leadframe are described. Using the leadframe, several air cavity packages can be quickly formed at one time. A method of manufacture using the leadframe can include forming the leadframe from a strip conductive material, where the leadframe includes conductive leads and downset facets. The method can also include forming slugs from conductive material, and arranging the slugs into respective positions relative to the downset facets of the leadframe. The method can also include fastening the slugs to the leadframe using the downset facets, and forming plastic packages around the leadframe and the slugs, where each of the plastic packages includes an air cavity in which at least a portion of a respective one of the slugs and at least a portion of a respective one of the conductive leads is exposed.

Abstract: An electronic component-mounted body (1) in accordance with an embodiment of the present invention is configured such that an IC chip (20) is fixed, with use of a post (30) having a thermosetting property, to a wiring substrate (10) having an anisotropic linear expansion coefficient.

Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (I-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Abstract: The present invention relates to a ceramic substrate (100) comprising: a front side (100-1), which comprises: i) a power semiconductor (102-1, . . . , 102-n); and ii) a first metallic layer (104) comprising at least one first metallic plane contact (104-1, . . . , 104-n), which is configured to connect the power semiconductor (102-1, . . . , 102-n) to a first terminal (105-1, . . . , 105-n) on an edge (100-3) of the ceramic substrate (100); a back side (100-2), which comprises: i) a capacitor (103) which is attached to a ii) second metallic layer (108) comprising at least one second metallic plane contact (108-1, . . . , 108-n), which is configured to connect the capacitor (103) to a second terminal (107-1, . . . , 107-n) on the edge (100-3) of the ceramic substrate (100); and a metallic frame (110), which is configured to connect the first metallic layer (104) to the second metallic layer (108).

Abstract: An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

Abstract: A semiconductor device includes a carrier, a semiconductor die and a die attach material arranged between the carrier and the semiconductor die. A fillet height of the die attach material is less than about 95% of a height of the semiconductor die. A maximum extension of the die attach material over edges of a main surface of the semiconductor die facing the die attach material is less than about 200 micrometers.

Abstract: A method of making an interconnect substrate includes steps of: providing a base and a plurality of posts projecting from the base, providing a dielectric compound on the base, forming a top routing circuitry on the dielectric compound and electrically coupled to the posts; and selectively removing portions of the base to form a plurality of terminals. The terminals are below the posts and extend laterally from the posts to provide electrical contacts underneath the dielectric compound. The dielectric compound covers sidewalls of the posts and provides a dielectric platform for the top routing circuitry deposited thereon. The top routing circuitry laterally extends on the dielectric compound and is electrically connected to the terminals by the posts.

Abstract: Examples disclosed herein relate to a heat sink. Examples include a thermoconductive base thermally coupled to a device. Examples include a fin thermally coupled to and extending from a first surface of the thermoconductive base to dissipate heat generated by the device. Examples include a heat insulation layer disposed on a distal end of the fin to insulate the distal end of the fin from heat generated by the device.

Abstract: A method of manufacturing a bonded body is provided in which a copper member (13B) formed from copper or a copper alloy, and an aluminum member (31) formed from an aluminum alloy in which a Si concentration is set in a range of 1 mass % to 25 mass % are bonded to each other. In the aluminum member before the bonding, D90 of an equivalent circle diameter of a Si phase at a bonding surface with the copper member is set in a range of 1 ?m to 8 ?m, and the aluminum member and the copper member are subjected to solid-phase diffusion bonding.

Abstract: A semiconductor module includes a first recessed portion and a second recessed portion formed in an insulating plate at positions close to a first long side and a second long side opposite to the first long side, and a first protruding portion and a second protruding portion formed on a case at bottom surfaces of a first side wall and a second side wall opposite to the first side wall. The first protruding portion and the second protruding portion are engaged with the first recessed portion and the second recessed portion with bonding adhesive in between. Thereby, a joined area between the insulating plate and the containment unit (case) increases. Accordingly, joining force between the insulating plate and the containment unit (case) increases to prevent generation of a gap between the insulating plate and the containment unit (case).

Abstract: A bonded body is provided in which an aluminum alloy member formed from an aluminum alloy, and a metal member formed from copper, nickel, or silver are bonded to each other. The aluminum alloy member is constituted by an aluminum alloy in which a concentration of Si is in a range of 1 mass % to 25 mass %. The aluminum alloy member and the metal member are subjected to solid-phase diffusion bonding. A compound layer, which is formed through diffusion of Al of the aluminum alloy member and a metal element of the metal member, is provided at a bonding interface between the aluminum alloy member and the metal member. A Mg-concentrated layer, in which a concentration of Mg is to 3 mass % or greater, is formed at the inside of the compound layer, and the thickness of the Mg-concentrated layer is in a range of 1 ?m to 30 ?m.

Abstract: An apparatus including a primary device and at least one secondary device coupled to a substrate; a heat exchanger disposed on the primary device and on the at least one secondary device, wherein the heat exchanger includes at least one portion disposed over an area corresponding to the primary device or the at least one second device including a deflectable surface; and at least one thermally conductive conduit coupled to the heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including the heat exchanger including at least one floating section operable to move in a direction toward or away from at least one of the plurality of dice and at least one thermally conductive conduit disposed in a channel of the heat exchanger and connected to the at least one floating section; and coupling the heat exchanger to the multi-chip package.

Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.

Abstract: A power electronics module comprises a first liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the first liquid cooler comprises a metal body providing a first terminal of the power electronics module; a second liquid cooler comprising a cooling channel for receiving a cooling liquid, wherein the second liquid cooler comprises a metal body providing a second terminal of the power electronics module; a plurality of semiconductor chips arranged between the first liquid cooler and the second liquid cooler, such that a first electrode of each semiconductor chip is bonded to the first liquid cooler, such that the first electrode is in electrical contact with the first liquid cooler, and an opposite second electrode of each semiconductor chip is in electrical contact with the second liquid cooler; and an insulating encapsulation, formed by molding the first liquid cooler, the second liquid cooler and the plurality of semiconductor chips into an insulation material, such that the fir

Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

Abstract: A power module includes a first die pad, a first switching element, a second die pad, a second switching element, an integrated circuit element, an encapsulation resin, and a lead frame assembly. The encapsulation resin encapsulates the first switching element, the second switching element, and the integrated circuit element. The lead frame assembly includes an outer lead and an inner lead. The lead frame assembly includes a first lead frame and a second lead frame. The first lead frame includes a first inner lead connected to the first die pad and a first outer lead connected to the first inner lead. The second lead frame includes a second inner lead connected to the second die pad and a second outer lead connected to the second inner lead.

Abstract: Disclosed herein is a semiconductor chip package having a heat dissipating structure. The semiconductor chip package including: a semiconductor chip configured such that a plurality of terminals protrudes from the upper surface thereof; lead frames connected to the terminals located on the upper surface of the semiconductor chip; and a package body configured to protect the semiconductor chip and the lead frames and to form the outside shape of the semiconductor chip package, and formed by molding. The lower surfaces of the lead frames are exposed to the outside. The lower surface of the package body is partially cut out such that the bottom surface of the semiconductor chip is exposed to the outside.

Abstract: A manufacturing method of a semiconductor module includes: sealing an assembly with resin, the assembly including a semiconductor chip, a heat-dissipation plate on the semiconductor chip, and multiple terminals, such that the resin includes a first surface, a second surface located opposite to the first surface, and a side surface, a groove extends in the side surface from the first surface to the second surface, an inner surface of the groove includes a first tapered surface, and a second tapered surface provided between the first tapered surface and the first surface, the second tapered surface inclining toward the first surface at a greater inclination angle than an inclination angle of the first tapered surface; and cutting the first surface within an area located on a first surface side from a boundary between the first tapered surface and the second tapered surface such that the heat-dissipation plate exposes.

Abstract: Provided is a lead frame including: one or more solder bonding regions containing copper material or copper plating; and a molding resin adhesion region containing a copper oxide film. The solder bonding regions are exposed on a surface of the lead frame. Further, provided is a lead frame manufacturing method including: forming a resist film in a molding resin adhesion region that is included in a surface of a lead frame member made of copper, or that is included in a surface of a copper-plated lead frame member; forming a plating film by performing a metal plating process on one or more solder bonding regions included in the surface of the lead frame member; removing the resist film; and forming a copper oxide film by oxidizing the molding resin adhesion region.

Abstract: Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.

Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad.

Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.