Patents Issued in March 13, 2018
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Patent number: 9916155Abstract: Projects may be recalled by a system based on a selection of a screenshot associated with the project. A request to access a project, by a selection of a screenshot from a group of screenshots may be received. The screenshot may be mapped to a particular workspace location, and it may be associated with trace data stored in a file. The associated trace data may be identified by the system, and the trace data can be read. Using the trace data, the system can access the project associated with the screenshot and launch the workspace and the project.Type: GrantFiled: December 1, 2015Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Awanish K. Singh, Jaspreet Singh
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Patent number: 9916156Abstract: A system for visualizing a congruency of versions of an application across phases of a release pipeline includes a selecting engine to select a phase from a number of phases; a representing engine to represent, via a user interface (UI), a congruency for a number of versions of an application compared against a target version of the application across the phases of a release pipeline, the congruency for the number of versions of the application represented with identifiers; a differentiating engine to differentiate a latest-deployed version of the application against a planned version of the application in a particular environment; and a comparing engine to compare, based on a selection, properties of the versions of the application.Type: GrantFiled: June 20, 2016Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael D. Elder, Sara Russell, Lucinio Santos, John-Mason P. Shackelford, John E. Swanke
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Patent number: 9916157Abstract: In various embodiments, methods, systems, and non-transitory computer-readable media are disclosed that allow users to specify runtime customizations of documents developed using a desktop integration framework. Workbook metadata is a set of information that describes how a given workbook is integrated with a particular web application. When a workbook is being published, metadata may be written into a local cache in the published workbook as well as a workbook definition file. Metadata management may be handed by a metadata service allowing updates and customization of published workbooks independently of a local cache in the published workbook and the workbook definition file. A workbook composer enables users to customize the metadata and store the customizations using the metadata manager.Type: GrantFiled: June 13, 2014Date of Patent: March 13, 2018Assignee: Oracle International CorporationInventors: Yixuan Geng, Edmund Alexander Davis
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Patent number: 9916158Abstract: A system and method to build feature evolution models for existing applications (“apps”) in the market based on open app data repositories). A feature evolution model of an app depicts the app name, its historical versions (historical version labels, release timestamps of each version), rating values of each version, and structured features (e.g., umbrella features and low-level features) each version introduces, improves or deletes. There is further extracted from the app description and release logs the app name, historical version labels, release timestamps, use the rating info of the app to extract and assign rating values for each version of the app, and apply NLP techniques and source code analysis techniques to extract “structured features” of the app through analyzing the app description, the release logs, and corresponding source code revisions of the app. Upon the built feature evolution models, various feature insights may be easily extracted and generated.Type: GrantFiled: July 20, 2016Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Ya Bin Dang, Qi Cheng Li, Shao Chun Li, Guang Tai Liang, Xin Zhou
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Patent number: 9916159Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.Type: GrantFiled: January 14, 2016Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz
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Patent number: 9916160Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.Type: GrantFiled: December 5, 2014Date of Patent: March 13, 2018Assignee: Intel CorporationInventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K Feghali, Erdinc Ozturk, Martin G Dixon, Sean Mirkes, Bret L Toll, Maxim Loktyukhin, Mark C Davis, Alexandre J Farcy
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Patent number: 9916161Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.Type: GrantFiled: June 25, 2015Date of Patent: March 13, 2018Assignee: Intel CorporationInventor: Ahmad Yasin
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Patent number: 9916162Abstract: Methods and systems may synchronize workloads across local thread groups. The methods and systems may provide for receiving, at a graphics processor, a workload from a host processor and receiving, at a plurality of processing elements, a plurality of threads that from one or more local thread groups. Additionally, the processing of the workload may be synchronized across the one or more thread groups. In one example, the global barrier determines that all threads across the thread groups have been completed without polling.Type: GrantFiled: December 8, 2014Date of Patent: March 13, 2018Assignee: Intel CorporationInventor: Niraj Gupta
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Patent number: 9916163Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.Type: GrantFiled: January 9, 2017Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventor: Changhoan Kim
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Patent number: 9916164Abstract: Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.Type: GrantFiled: June 11, 2015Date of Patent: March 13, 2018Assignee: Intel CorporationInventors: Vineeth Mekkat, Girish Venkatasubramanian, Howard H. Chen
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Patent number: 9916165Abstract: A basic input/output system may be configured to, during boot of an information handling system in a pre-operating system environment of the information handling system, calculate an amount of energy required to perform a persistent memory save operation in a persistent memory of the information handling system in order to transfer data from a volatile memory of the persistent memory communicatively coupled to the processor to a non-volatile memory of the persistent memory communicatively coupled to the volatile memory, cause charging of an energy storage device for providing electrical energy to perform persistent memory save operations at least until a charging level of the energy storage device satisfies the amount of energy, and boot to an operating system of the information handling system responsive to the charging level of the energy storage device satisfying the amount of energy.Type: GrantFiled: August 20, 2015Date of Patent: March 13, 2018Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, Shane Michael Chiasson
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Patent number: 9916166Abstract: This invention provides an array-type processing device which can reduce power consumption and can also reduce a processing performance drop caused by switching of configuration information. An array-type processing device, which includes a first domain and a second domain, the device comprises a plurality of processing units which are allocated in the first domain, and each of which includes a plurality of processing elements and a router configured to control connections between the plurality of processing elements, a configuration information supply unit configured to supply configuration information to one or more processing units of the plurality of processing units, the configuration information supply unit being allocated in the second domain, and a power supply control unit configured to control the power supply to the plurality of processing units, the power supply control unit being allocated in the second domain.Type: GrantFiled: February 12, 2014Date of Patent: March 13, 2018Assignee: CANON KABUSHIKI KAISHAInventor: Eiji Aizawa
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Patent number: 9916167Abstract: Testing correct mirroring of a GUI. Two GUI specifications are received, one that specifies text elements in a left-to-right natural language and another that specifies text elements in a right-to-left natural language and corresponds to a horizontally mirrored counterpart of the first GUI specification. For each child element in the first specification a start position, width, and a width of its parent GUI element are determined; for the corresponding specification a start position and width for the counterpart element is determined, a horizontally mirrored start position is calculated for the child element, it is determined whether the start position and width of the counterpart child GUI element are within a predefined tolerance of the calculated horizontally mirrored start position and the width, respectively, of the child GUI element; and, if not, the second GUI specification is updated with the calculated horizontally mirrored start position or width.Type: GrantFiled: October 4, 2016Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Mohamed Bahgat, Mariam Moustafa Reda AbdALLAH El-Tantawi
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Patent number: 9916168Abstract: Testing correct mirroring of a GUI. Two GUI specifications are received, one that specifies text elements in a left-to-right natural language and another that specifies text elements in a right-to-left natural language and corresponds to a horizontally mirrored counterpart of the first GUI specification. For each child element in the first specification a start position, width, and a width of its parent GUI element are determined; for the corresponding specification a start position and width for the counterpart element is determined, a horizontally mirrored start position is calculated for the child element, it is determined whether the start position and width of the counterpart child GUI element are within a predefined tolerance of the calculated horizontally mirrored start position and the width, respectively, of the child GUI element; and, if not, the second GUI specification is updated with the calculated horizontally mirrored start position or width.Type: GrantFiled: October 5, 2016Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Mohamed Bahgat, Mariam Moustafa Reda AbdALLAH El-Tantawi
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Patent number: 9916169Abstract: Configurable electronic devices contain identifying information in a dual-ported memory. A plurality of un-configured units are assembled into a set. Using identifying information, a provisioning server matches each particular unit to configuration settings needed to appropriately configure that device for use by a specific end user. The configuration settings and/or data may be transmitted to the devices via their embedded RFID systems and stored in their dual-ported memory (via the first memory port). The electronic devices may comprise processor-based systems and, upon system initialization, the configuration data can be read from the memory via a second port thereof and used to configure the device for use by the user. In this way, devices may be configured as a set destined for a particular end user immediately prior to shipment and/or deployment and it is not necessary to separately track customized units prior to assembling them into a set.Type: GrantFiled: April 15, 2011Date of Patent: March 13, 2018Assignee: Polycom, Inc.Inventors: Bryan Edwards, Peter Santeusanio, John Bahr, Kent Graham Bodell, Stephen Rolapp, Caglan M. Aras
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Patent number: 9916170Abstract: A method for simulating a virtual computing environment includes specifying one or more flavors of resource consumers and one or more flavors of datastores to be provisioned on a tree of hosts for a simulation of a distributed virtualization scheduler. The method also includes generating a tree of hosts for the resource consumers and datastores based on the specified flavors and using a tree generator component of the distributed virtualization scheduler. The method further includes generating a plurality of resource consumer requests for the generated tree of hosts according to a pattern-based input, where the resource consumer requests include requests for the specified resource consumer flavors and the specified datastore flavors. The method also includes simulating execution of the resource consumer requests on the generated tree of hosts using the distributed virtualization scheduler, and utilizing a result of the simulated execution to improve a placement decision for a resource consumer.Type: GrantFiled: December 30, 2015Date of Patent: March 13, 2018Assignee: VMWARE, INC.Inventors: Badhrinath Sampathkumar, Yongkun Gui
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Patent number: 9916171Abstract: In an approach for detecting one or more applications in a VM, one or more processors establish a time duration. One or more processors detect two or more files, each file in the two or more files having a time stamp time that differs from a last modified time stamp time of at least one other file in the two or more files by no more than the time duration. One or more processors record an identifier for each file of the two or more files, a location, a name, and a last modified time stamp time of each file of the two or more files. One or more processors map the two or more files to an application installed on the VM.Type: GrantFiled: July 10, 2014Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Vasanth Bala, Ea-Ee Jan, Lakshminarayanan Renganarayana, Wolfgang O. H. Richter, Xiaolan Zhang
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Patent number: 9916172Abstract: According to one embodiment of the present invention, the scheduling method includes an acquisition step of acquiring operation state information on a virtual CPU (vCPU) and lock information on an OS in the operation of the vCPU and of a virtual machine (VM) driving the vCPU and including the OS, and a determination step for determining whether the vCPU is in a lock holder preemption (LHP) state on the basis of the operation state information and the lock information. According to one embodiment of the present invention, the LHP can be easily and precisely known on a system using the VM. Also, even with an increase in the number of cores, scalability can be supported in a system by adjusting the pCPU to which operations of the vCPU are allocated through a scheduling scheme.Type: GrantFiled: March 5, 2013Date of Patent: March 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin Ho Lee, Yong Seok Park, Jong Hun Yoo, Seong-Soo Hong
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Patent number: 9916173Abstract: A hypervisor of a host receives an indication of an exit from a guest to the hypervisor and a memory-mapped input output (MMIO) address that caused the exit to hypervisor. The hypervisor walks a page table of the guest to identify a guest address associated with the MMIO address that caused the exit to the hypervisor. The hypervisor decodes an instruction of the guest referenced by the guest address to determine a type of operation that the guest intended to execute and a location of MMIO information. The hypervisor records, in a page table entry for the MMIO address of a host page table, an association with the type of operation and the location of the MMIO information. The hypervisor executes the operation on behalf of the guest based on the type of the operation and the MMIO information.Type: GrantFiled: November 25, 2013Date of Patent: March 13, 2018Assignee: Red Hat Israel, Ltd.Inventors: Michael Tsirkin, Gleb Natapov
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Patent number: 9916174Abstract: Methods, computer program products, and network authority devices are presented. The methods include, for instance: updating a source network with migration information of a virtual machine to redirect network traffic for the virtual machine to a destination network; and updating at least one remote network with the migration information of the virtual machine. In one embodiment, the updating includes updating the source network concurrent with a migration of the virtual machine to minimize interruption of the network traffic. In another embodiment, the updating includes updating a network device of the source network to forward the network traffic for the virtual machine to another network device of the destination network. In a further embodiment, the updating includes updating the source network to redirect the network traffic from at least one client on the at least one remote network.Type: GrantFiled: May 27, 2015Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heng Guo Ge, Jing Lu, Da Shen, Jun Yao
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Patent number: 9916175Abstract: A network of nodes transports a plurality of flows from central nodes to a plurality of display sessions executing processes that operate under the control of one or more central operating systems. A plurality of isolated virtual nodes comprises 1) a plurality of virtual graphics nodes that concurrently process graphics flows used in the plurality of display sessions at the plurality of remote zero client nodes and 2) a plurality of virtual switches that switch the concurrently processed graphic flows from the virtual graphics nodes to the plurality of remote zero client nodes. Two or more graphic flows are used simultaneously in two or more display sessions at a single remote zero client node that executes a separating operating system for separating the two or more display sessions from each other based on a a separation policy for the two or more graphics flows.Type: GrantFiled: January 27, 2016Date of Patent: March 13, 2018Assignee: Objective Interface Systems, Inc.Inventors: R William Beckwith, J Nicolas Watson
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Patent number: 9916176Abstract: A methods and device for accessing virtual machine (VM) data are described. A computing device for accessing virtual machine comprises an access request process module, a data transfer proxy module and a virtual disk. The access request process module receives a data access request sent by a VM and adds the data access request to a request array. The data transfer proxy module obtains the data access request from the request array, maps the obtained data access request to a corresponding virtual storage unit, and maps the virtual storage unit to a corresponding physical storage unit of a distributed storage system. A corresponding data access operation may be performed based on a type of the data access request.Type: GrantFiled: November 23, 2016Date of Patent: March 13, 2018Assignee: Alibaba Group Holding LimitedInventor: Xiao Fei Quan
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Patent number: 9916177Abstract: A computerized predictive workload scheduling tool and methods for analytically implementing a predictive job schedule. The scheduling tool incorporates and uses analytics to leverage information from a plurality of data sources to anticipate and pro-actively correct computing system job failures before they occur. The predictive scheduling tool generates a job schedule, analyzes the job schedule for predictable failures and resolves the identified failures by amending the job schedule. The job schedule generated and analyzed by the scheduling tool is deployed, analyzed and resolved for errors as needed or identified to prevent failures from occurring.Type: GrantFiled: August 19, 2015Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Murilo Goncalves de Aguiar, Juscelino Candido de Lima, Jr.
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Patent number: 9916178Abstract: Technologies for integrated thread scheduling include a computing device having a network interface controller (NIC). The NIC is configured to detect and suspend a thread that is being blocked by one or more communication operations. A thread scheduling engine of the NIC is configured to move the suspended thread from a running queue of the system thread scheduler to a pending queue of the thread scheduling engine. The thread scheduling engine is further configured to move the suspended thread from the pending queue to a ready queue of the thread scheduling engine upon determining any dependencies and/or blocking communications operations have completed. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2015Date of Patent: March 13, 2018Assignee: Intel CorporationInventors: James Dinan, Mario Flajslik, Tom St. John
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Patent number: 9916179Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes, by the first processor, initializing a time record, listening for zero or more probes from the one more additional processors, responding to each probe of the zero or more probes, and logging each probe of the zero or more probes to yield a probe log. The computer-implemented method further includes, by the first processor, receiving a probe report directive and, responsive to the probe report directive, generating a probe report indication based on the probe log. The probe report indication denotes whether, since the time record, the first processor has received any of the zero or more probes. The computer-implemented method further includes ending the time record. A corresponding computer program product and computer system are also disclosed.Type: GrantFiled: October 29, 2015Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 9916180Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes, by the first processor, initializing a time record, listening for zero or more probes from the one more additional processors, responding to each probe of the zero or more probes, and logging each probe of the zero or more probes to yield a probe log. The computer-implemented method further includes, by the first processor, receiving a probe report directive and, responsive to the probe report directive, generating a probe report indication based on the probe log. The probe report indication denotes whether, since the time record, the first processor has received any of the zero or more probes. The computer-implemented method further includes ending the time record. A corresponding computer program product and computer system are also disclosed.Type: GrantFiled: May 25, 2016Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 9916181Abstract: Disclosed aspects include managing asset placement with respect to a shared pool of configurable computing resources. A first set of first resource values is detected with respect to a set of assets. The first set of first resource values includes a first value. A second set of first resource values is detected with respect to the set of assets. The second set of first resource values includes a second value. The second value exceeds the first value. A set of asset weight values is detected with respect to the set of assets. The set of asset weight values indicates an asset utilization arrangement. A placement arrangement is determined for the set of assets using the first set of first resource values, the second set of first resource values, and the set of asset weight values. Accordingly, the set of assets is placed based on the placement arrangement.Type: GrantFiled: September 26, 2015Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Joseph W. Cropper, Kyle L. Henderson, Jennifer D. Mulsow, Jeffrey W. Tenner
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Patent number: 9916182Abstract: The present invention discloses a method and an apparatus for allocating a stream processing unit, and pertains to the field of communications technologies. The method includes: obtaining a parallelism degree and a resource usage rate of a stream processing component on each computing node, and determining the number of stream processing units according to the parallelism degree; generating a stream processing unit to be allocated, and determining a resource usage rate of the stream processing component as a resource usage rate of a corresponding stream processing unit; and allocating, according to a processing capability of the computing node on which the stream processing component is located and a resource usage rate of an allocated stream processing unit, the stream processing unit to be allocated to a corresponding computing node. According to the present invention, the steam data processing efficiency of a distributed stream processing system is improved.Type: GrantFiled: July 15, 2014Date of Patent: March 13, 2018Assignee: Huawei Technologies Co., Ltd.Inventor: Jianfeng Qian
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Patent number: 9916183Abstract: There is provided a method, a system and a computer program product for improving performance and fairness in sharing a cluster of dynamically available computing resources among multiple jobs. The system collects at least one parameter associated with availability of a plurality of computing resources. The system calculates, based on the collected parameter, an effective processing time each computing resource can provide to each job. The system allocates, based on the calculated effective processing time, the computing resources to the multiple jobs, whereby the multiple jobs are completed at a same time or an approximate time.Type: GrantFiled: September 2, 2016Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Ting He, Kang-Won Lee, Jian Tan, Yuting Ji
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Patent number: 9916184Abstract: Methods and systems for data relocation in global storage cloud environments are provided. A method includes locating a data server near a travel location of a user based on one or more travel plans of the user. The method further includes transferring data of the user from a home data server near a home location of the user to the data server near the travel location.Type: GrantFiled: December 2, 2011Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhushan P. Jain, Sandeep R. Patil, Sri Ramanathan, Matthew B. Trevathan, Ujwala P. Tulshigiri
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Patent number: 9916185Abstract: A facility is provided that, when installed, removes from an architecture a selected architectural function, such that the function is not able to be turned on/off regardless of other controls within the environment. When the facility is installed, the architectural function is not supported when processing in an architectural mode based on the architecture. It is as if the selected architectural function is no longer available in the architecture, and in fact, the code implementing the facility may have been deleted, bypassed, or otherwise eliminated. One such architectural function is virtual address translation, such as dynamic address translation (DAT), and the architecture is, for instance, ESA/390.Type: GrantFiled: March 18, 2014Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles W. Gainey, Jr., Michael K. Gschwind
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Patent number: 9916186Abstract: A facility is provided that, when installed, removes from an architecture a selected architectural function, such that the function is not able to be turned on/off regardless of other controls within the environment. When the facility is installed, the architectural function is not supported when processing in an architectural mode based on the architecture. It is as if the selected architectural function is no longer available in the architecture, and in fact, the code implementing the facility may have been deleted, bypassed, or otherwise eliminated. One such architectural function is virtual address translation, such as dynamic address translation (DAT), and the architecture is, for instance, ESA/390.Type: GrantFiled: November 26, 2014Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles W. Gainey, Jr., Michael K. Gschwind
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Patent number: 9916187Abstract: Techniques are provided for a graph database system that accepts custom graph analytic programs that are written in a high-level graph-specific programming language and compiles the programs into executables that, when executed, directly access graph data of a graph that is stored in the graph database. In this way, a low-level data-access API is avoided. Also, a graph analytic program, which only describes an abstract description of an algorithm, does not include any details regarding data access. In one technique, a user is not required to include explicit parallelization in a graph analytic program in order for the graph analytic program to take advantage of parallelization. A compiler of the graph database system identifies portions of the graph analytic program that can benefit from parallelization and, in response, generates parallelized executable code that corresponds to those portions.Type: GrantFiled: October 27, 2014Date of Patent: March 13, 2018Assignee: Oracle International CorporationInventors: Korbinian Schmid, Martin Sevenich, Sungpack Hong, Hassan Chafi
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Patent number: 9916188Abstract: A processing device executing a provisioner requests a node level task from a server. The processing device receives an assignment of a first node level task, wherein the first node level task is associated with a cluster management operation for a first cluster. The processing device determines a first plugin capable of performing the first node level task from a plurality of plugins, wherein each of the plurality of plugins comprises a self-contained program for performing a specific set of node level tasks. The processing device performs the first node level task by the first plugin, wherein the first node level task is an operation on a remote target host that does not include software associated with the provisioner. The processing device reports a result of the node level task to the server.Type: GrantFiled: March 13, 2015Date of Patent: March 13, 2018Assignee: CASK DATA, INC.Inventors: Albert Yen Shau, Christopher Gianelloni, Derek Lewis Wood, Jonathan Michael Gray, Nitin Motgi, Poorna Chandra Gowda Bannikkuppe Ramachandra, Rohit Sarma Nistala
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Patent number: 9916189Abstract: In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.Type: GrantFiled: September 6, 2014Date of Patent: March 13, 2018Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Martin T. Pohlack, Stephan Diestelhorst
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Patent number: 9916190Abstract: A web service tagging tool that includes a memory operable to store subscription tags and a web service application. The web service application includes a tagging engine configure to generate a subscription tag linking target data fields, target data location information, and a triggering event. The tagging engine is further configured to send data content comprising the subscription tag to the user application. The web service application further includes a data collection engine configured to receive data from the target data fields in response to the triggering event. The web service application further includes a data feed engine operably coupled to the data collection engine. The data feed engine is configured to generate one or more data feeds comprising at least a portion of the user data and to forward the one or more data feeds based on routing instructions.Type: GrantFiled: September 13, 2016Date of Patent: March 13, 2018Assignee: Bank of America CorporationInventors: Veerasekhar Addepalli, Ajinkya Atul Bokil
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Patent number: 9916191Abstract: A method of efficiently checking a filesystem for errors is provided, the filesystem including a set of data blocks and a set of VBPs, the set of VBPs arranged in a set of VBP blocks, each VBP block storing a plurality of the VBPs. The method includes multiple stages, one stage including iterating through VBP blocks of the filesystem to generate a validity bitmap, and a later stage including traversing a block pointer structure associated with each of a set of files of the filesystem, the traversal making reference to the validity bitmap.Type: GrantFiled: December 19, 2014Date of Patent: March 13, 2018Assignee: EMC IP Holding Company LLCInventors: Hao Pan, Feng Zhang, Kenny Zhou, Yi Wang, Kent J. Costa
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Patent number: 9916192Abstract: Dynamically collecting data pertaining to a program execution. A method can include monitoring execution of the program in a plurality of threads and, responsive to identifying an exception triggered by the program execution in a first of the plurality of threads, initiating at least one data collector to collect data exclusively relevant to the program execution in the first thread.Type: GrantFiled: January 12, 2012Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Peter R. MacFarlane
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Patent number: 9916193Abstract: A zone selective interlocking device includes a first port, a second port, an input bus, an output bus and a query signal receiving branch. The first and second port each are switchable between two states, connected to the input bus and connected to the output bus, and the zone selective interlocking device is operable in a first mode. In the first mode, the query signal receiving branch is turned on. Within a preset timeslot, a link fault query signal is permitted to be inputted to the query signal receiving branch through the first port, while a link fault query signal is prevented from being inputted to the query signal receiving branch through the second port. Based on whether a link fault query signal is received within the timeslot, a judgment is made on whether a fault has occurred in a communication link connected to a corresponding port.Type: GrantFiled: November 25, 2014Date of Patent: March 13, 2018Assignee: SIEMENS AKTIENGESELLSCHAFTInventors: Wei Gang Chen, Mario Dankert, Feng Du, Yue Zhuo
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Patent number: 9916194Abstract: System component failure diagnosis is provided. In response to determining that a number of component failure cases corresponding to a complex system stored in a historical diagnosis database is less than a pre-defined threshold number of component failure cases, a system component failure root cause is predicted using a rule-based reasoning method. In response to determining that the number of component failure cases corresponding to the complex system is greater than or equal to the pre-defined threshold number of component failure cases, the system component failure root cause is predicted using the rule-based reasoning method and a machine learning method. The diagnosis accuracy of the system component failure root cause predicted by the rule-based reasoning method and the machine learning method is calculated using a cross-validation method. The performance of the rule-based reasoning method and the machine learning method is evaluated using a statistical process control method.Type: GrantFiled: October 1, 2015Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventor: Yan Pang
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Patent number: 9916195Abstract: A method for performing a repair operation in a computer system using arrays having array cells includes detecting an error in an array. In response to detecting the error, error information is written to an error trap register. The error information includes error data and associated error detection information and a position in an array row. The error information is read from the error trap register and a corresponding data copy is determined and fetched in the computer system. One or more exact bit positions that caused the error are determined by comparing the error data with the corresponding data copy. The array cells which are associated with the determined one or more bit positions are disabled.Type: GrantFiled: January 12, 2016Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerrit Koch, Martin Recktenwald
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Patent number: 9916196Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.Type: GrantFiled: February 25, 2015Date of Patent: March 13, 2018Assignee: Rambus Inc.Inventors: Frederick A. Ware, Brent S. Haukness, John Eric Linstadt, Scott C. Best
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Patent number: 9916197Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.Type: GrantFiled: June 2, 2015Date of Patent: March 13, 2018Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck, Eitan Yaakobi
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Patent number: 9916198Abstract: A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.Type: GrantFiled: August 24, 2015Date of Patent: March 13, 2018Assignee: CARINGO, INC.Inventors: Don Baker, Paul R. M. Carpentier, Andrew Klager, Aaron Pierce, Jonathan Ring, Russell Turpin, David Yoakley
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Patent number: 9916199Abstract: Provided are a method and apparatus for an error tolerance aware data retention scheme in a storage device for multi-scale error tolerant data. A mapping of retention priorities to sectors of the storage units maps higher retention priorities to sectors having a higher retention capability. A data stream and retention metadata for the data stream indicate retention priorities for segments of the data stream. Segments of the data stream having less error tolerance are mapped to higher retention priorities than segments of the data stream having greater error tolerance. The mapping of retention priorities is used to determine a sector having a retention priority matching a retention priority of a segment of the data stream indicated in the retention metadata. The segment of the data stream is stored in the determined sector.Type: GrantFiled: March 30, 2016Date of Patent: March 13, 2018Assignee: INTEL CORPORATIONInventors: Tal Azogui, Vered Bar Bracha, Vallabhajosyula S. Somayazulu, Wei Wu
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Patent number: 9916200Abstract: Fault-tolerant distributed information handling systems and methods, including a method in a system including: a first host configured to store a first fragment of data, a second host configured to store a second fragment of data, a third host configured to store a third fragment of data, and a fourth host configured to store a first code derived at least from the first fragment of data, the second fragment of data, and the third fragment of data, are provided. The method includes: the first agent transmitting via a multicast operation an updated second fragment of data to the second host and the fourth host; a second agent corresponding to the second host transmitting via a unicast operation the second fragment of data to the fourth host; and generating a second code derived from the first code, the second fragment of data, and the updated second fragment of data.Type: GrantFiled: August 12, 2016Date of Patent: March 13, 2018Assignee: Dell Products, LPInventors: Ke Xu, Dharmesh M. Patel, William Brad Langford
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Patent number: 9916201Abstract: Embodiments relate to supporting transaction data committed to a stable storage. Committed data in the cluster is stored in the persistent cache layer and replicated and stored in the cache layer of one or more secondary nodes. One copy is designated as a master copy and all other copies are designated as replica, with an exclusive write lock assigned to the master and a shared write lock extended to the replica. An acknowledgement of receiving the data is communicated following confirmation that the data has been replicated to each node designated to receive the replica. Managers and a director are provided to support management of the master copy and the replicas within the file system, including invalidation of replicas, fault tolerance associated with failure of a node holding a master copy, recovery from a failed node, recovered of the file system from a power failure, and transferring master and replica copies within the file system.Type: GrantFiled: July 28, 2015Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Wendy A. Belluomini, Karan Gupta, Dean Hildebrand, Anna S. Povzner, Himabindu Pucha, Renu Tewari
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Patent number: 9916202Abstract: A technique for providing access to a data object serving as a target of snapshot-shipping replication includes taking a system snap of the data object after completion of each of multiple snapshot-shipping updates. In response to a data storage system receiving an IO (input/output) request to read and/or write to the data object, a data storage system redirects the IO request to a previously generated system snap, so that the data storage system performs the operation specified in the IO request on the system snap rather than of the data object itself.Type: GrantFiled: March 11, 2015Date of Patent: March 13, 2018Assignee: EMC IP Holding Company LLCInventors: Nagapraveen V. Seela, Michael C. Brundage, Yan Xu
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Patent number: 9916203Abstract: Embodiments are directed to a method of minimizing latency and input/output (I/O) operations in a data storage system by defining a sparse metadata segment tree to identify changed data blocks, wherein a full version of the tree is stored in a memory and modified versions of the tree are stored in cache memory, and using the sparse metadata segment tree to perform at least one data storage application including file verification, file replication, file restores, and file system snapshots.Type: GrantFiled: June 30, 2015Date of Patent: March 13, 2018Assignee: EMC IP Holding Company LLCInventors: Prashant Pogde, Yamini Allu, Mahesh Kamat
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Patent number: 9916204Abstract: An information processing apparatus, backup method, and program product that enable efficient differential backup. In one embodiment, an information processing apparatus for files stored in a storage device includes: a metadata management unit for managing metadata of files stored in the storage device; a map generation unit for generating a map which indicates whether metadata associated with an identification value uniquely identifying a file in the storage device is present or absent; and a backup management unit for scanning the metadata to detect files that have been created, modified, or deleted since the last backup, and storing at least a data block and the metadata for a detected file in a backup storage device as backup information in association with the identification value.Type: GrantFiled: February 9, 2017Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventors: Norie Iwasaki, Sosuke Matsui, Tsuyoshi Miyamura, Terue Watanabe, Noriko Yamamoto