Abstract: A system, method, and apparatus for secure live virtual machine guest based snapshot recovery. A virtual machine sends a request to access a snapshot of a first virtual disk of the virtual machine including a snapshot identifier. A hypervisor selects the snapshot using the snapshot identifier and creates a second virtual disk using the snapshot. The hypervisor then maps the second virtual disk to the virtual machine and notifies the virtual machine that the snapshot on the second virtual disk is accessible. The virtual machine accesses the snapshot on the second virtual disk including retrieving snapshot data from the second virtual disk without reverting a current virtual machine instance on the first virtual disk to the snapshot on the second virtual disk.

Abstract: In connection with a data distribution architecture, client-side “deduplication” techniques may be utilized for data transfers occurring among various file system nodes. In some examples, these deduplication techniques involve fingerprinting file system elements that are being shared and transferred, and dividing each file into separate units referred to as “blocks” or “chunks.” These separate units may be used for independently rebuilding a file from local and remote collections, storage locations, or sources. The deduplication techniques may be applied to data transfers to prevent unnecessary data transfers, and to reduce the amount of bandwidth, processing power, and memory used to synchronize and transfer data among the file system nodes. The described deduplication concepts may also be applied for purposes of efficient file replication, data transfers, and file system events occurring within and among networks and file system nodes.

Abstract: The invention relates to a computer implemented method for creating a backup of data by a computer system. The creation of the backup comprises: assigning a first memory space in a main memory to data and loading the data into the first memory space; allocating a second memory space in the main memory for acting as container of one or more images of the data in the first memory space; creating the one or more images of the data in the first memory space; and storing the created one or more images in the second memory space and storing a respective copy of at least one of the one or more images in the one or more non-volatile storage media.

Abstract: Techniques for determining one or more replication paths for resources in different failure domains, while maintaining a target resiliency level, are disclosed. A replication path is a sequence of at least a subset of the set of resources. Based on the sequence, a resource is selected for replicating at least a portion of the resource consumers corresponding to each of the subset of resources. A replication path may be determined by adding a resource to the replication path and/or replacing one resource with another resource to modify the replication path. The modified replication path maintains the target resiliency level if the modified replication path does not include any loop of a length less than or equal to the target resiliency level.

Abstract: According to an aspect, data asset reconstruction includes receiving a data lineage for a data asset, where the data lineage identifies a data source connected to the data asset by an intermediate process. It is determined whether the intermediate process can be used to reconstruct a lost data asset. Based on determining that the intermediate process can be used to reconstruct the lost data asset, reconstructing the lost data asset with the intermediate process and the data source.

Abstract: According to an aspect, data asset reconstruction includes receiving a data lineage for a data asset, where the data lineage identifies a data source connected to the data asset by an intermediate process. It is determined whether the intermediate process can be used to reconstruct a lost data asset. Based on determining that the intermediate process can be used to reconstruct the lost data asset, reconstructing the lost data asset with the intermediate process and the data source.

Abstract: A database recovery and index rebuilding method involves reading data pages for a database to be recovered as recovery bases; retrieving all log records from stored post-backup updates and sorting the retrieved log records; as the data pages to be recovered are read, applying the sorted log records to their respective data pages; as the applying completes for individual data pages, extracting and sorting index keys from the individual data pages for which the applying is complete, until all index keys have been extracted from all individual data pages and sorted; on an individual recovered page basis, writing the recovered individual data pages into the database; and when all index keys have been extracted and sorted from all of the recovered individual data pages, rebuilding indexes of the database using the sorted index keys and writing the rebuilt indexes to the non-transitory storage.

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.

Abstract: As disclosed herein a method, executed by a computer, includes determining, by a processor, that a first node of a HA cluster is unable to communicate with a second node of the HA cluster, and initiating, by a processor, by the first node, a handshake operation with a connected client, wherein the handshake operation comprises requesting that the client determine a status of the second node and receiving, from the client, a response indicating the status of the second node. The method further includes accepting, by a processor, new requests in response to determining that the second node is unavailable, and requesting, by a processor, restoration of communications between the first node and the second node in response to determining that the second node is available. A computer system and computer program product corresponding to the above method are also disclosed herein.

Abstract: Techniques for selectively utilizing memory available in a redundant host system of a cluster are described. In one embodiment, a cluster of host systems, with at least one redundant host system, with each host system having a plurality of virtual machines with associated virtual machine (VM) reservation memory is provided. A portion of a data store is used to store a base file, the base file accessed by all the plurality of virtual machines. A portion of the memory available in the redundant host system is assigned as spare VM reservation memory. A copy of the base file is selectively stored in the spare VM reservation memory for access by all the plurality of virtual machines.

Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) is assigned to backup the master PHB that satisfies the error threshold. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices.

Abstract: A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.

Abstract: The present invention discloses a method and apparatus for intercepting implanted information in an application. The method comprises: determining an Application Programming interface API invoked by an implanted information code as a key API in accordance with information collected in advance, wherein the key API is the API provided by an implanted information provider; after starting a target application, monitoring an act of the target application invoking the key API by hooking the key API; and if the target application initiates a request to invoke the key API, determining that the implanted information code is contained in the target application and intercepting the request to invoke the key API so as to stop the implanted information code from running and to realize the interception of the implanted information in the target application.

Abstract: A method, system and computer-usable medium are disclosed for detecting unanticipated consumption of power by a device. A first set of power consumption data is selected, followed by the collection of a second set of power consumption data, which respectively correspond to the consumption of a first and second amount of power by a device when it performs an authorized operation. The first and second sets of power consumption data are then compared to detect whether the second amount of power consumed is greater than the first amount of power consumed. If so, then a notification is generated, stating that the device has consumed an unanticipated greater amount of power as a result of performing the authorized operation.

Abstract: An improved technique for storing trace data involves storing software operation debug trace information in a buffer memory rather than in a log file in the main memory, and after completion of the software operation either (1) deleting the debug trace information upon the successful completion of the operation, or (2) transferring the debug trace information to a log file memory upon a failure of the operation.

Abstract: A computer-implemented method includes identifying a primary code segment, determining a confidence score associated with said primary code segment, and determining whether the confidence score exceeds a confidence threshold. The computer-implemented method further includes responsive to the confidence score exceeding the confidence threshold, determining a logger code segment associated with the primary code segment. A corresponding computer program product and computer system are also disclosed.

Abstract: Testing computer software applications is performed by identifying first and second executable portions of the computer software application, where the portions are configured to access a data resource, and where at least one of the portions is configured to write to the data resource, instrumenting the computer software application by inserting one or more instrumentation instructions into one or both of the portions, where the instrumentation instruction is configured to cause execution of the portion being instrumented to be extended by a randomly-determined amount of time, and testing the computer software application in multiple iterations, where the computer software application is executed in multiple parallel execution threads, where the portions are independently executed at least partially in parallel in different threads, and where the computer software application is differently instrumented in each of the iterations.

Abstract: A method to detect and diagnose where an error occurs in a source code that is associated with a software program or a website is provided. The method may include receiving a log report associated with the software program or the website, whereby by the log report is sent based on a hidden tag associated with the software program or the website. The method may also include analyzing the received log report. The method may further include detecting at least one error based on the analysis of the received log report. The method may include reverting back to a previous line in the source code associated with the software program or the website, whereby the reverting is based on the detection of the at least one error.

Abstract: Techniques are provided for integrating source code analysis tools with a code review tool. A user submits a code change to the code review tool and one or more code analysis tools are automatically initiated to analyze the changed code. Results of the code analysis tool(s) are automatically provided back to the code review tool. Additionally or alternatively, one or more tests are automatically run to test one or more executables that are based on the changed code. Results of the test(s) are automatically provided to the code review tool. In this way, an effect of a code change is automatically determined and available for review along with the code change. The results of any code analysis tools and/or tests may be posted synchronously or asynchronously with the corresponding code change.

Abstract: A system, method, and computer program product for testing a software component by simulating a computing component interface using captured network packet information. A method may include receiving a service request comprised of one or more network packets from a software component to be tested. Responsive to receiving the service request, the method may access a data store of captured network packet information and determine that a matching service request is stored in the accessed data store. The matching service request may be comprised of one or more network packets that match the service request. The method may identify an associated response that is stored in the accessed data store. The associated response may be one or more network packets that are stored in association with the matching service request. The method then sends the associated response to the first software component.

Abstract: A system of testing software is provided. The system comprises a first hardware system having hardware components to execute a first version of the software, and additionally comprises a second hardware system having hardware components to execute a second version of the software. Here, the first version of the software and the second version are different. In addition, the system includes a device configured to test the first hardware system and the second hardware system by providing first input data traffic to the first hardware system, providing second input data traffic to the second hardware system, and accessing performance values from the first hardware system and the second hardware system to evaluate a performance comparison between the first hardware system executing the first version of the software and the second hardware system executing the second version of the software.

Abstract: Computer-implemented systems, methods, and computer-readable media are provided for facilitating analysis of a software application to determine its compatibility with one or more computer platforms. In accordance with some embodiments, a processor may receive, via an operator interface, a selection of an application and a user identity, and the processor may determine compatibility status between the application and at least one computing platform of a device associated with the user identity, and generate a report with the compatibility results.

Abstract: An apparatus, method, and computer program product are provided for software development testing utilizing one or more minimal testing features. An acceptance testing system receives one or more first minimal testing features for a first software development component to be developed by a first provider, and one or more second first minimal testing features for a second software development component to be developed by a second provider. Before completion of the second software development component, it is determined whether the first software development component is complete. If it is determined that the first software development component is complete, testing is performed on the first software development component utilizing the one or more first minimal testing features, before the completion of the second software development component.

Abstract: In an approach for generating transaction tracking data that is used to simulate a customer environment or test case scenario, a processor receives user input data, wherein the user input data includes, at least, an application topology constructed using a graphical user interface. A processor validates the user input data for, at least, supported environments of components of the application topology. A processor generates transaction tracking data based on, at least, the user input data.

Abstract: The source code of a software artifact may be scanned, and a call tree model with leaf nodes may be generated based on the scan. A set of test cases can be executed against the software artifact and log data from the execution can be collected. A set of untested leaf nodes can be detected and a new set of test cases can be generated to test the untested nodes. The new set of test cases are executed and a subset of the test cases which cover the previously untested nodes are added to the existing set of test cases.

Abstract: A method for testing an application running on an electronic device includes parsing, by a test processor, a state model of the application representing relationships among a plurality nodes, each node representing an application state. The method further includes parsing, by the test processor, a test implementation file including a plurality of commands for manipulating at least one of the application and the electronic device, each of the plurality of commands associated with respective ones of the plurality of nodes, traversing, by the test processor, the state model of the application by selecting for testing an application node in accordance with the node relationships in the state model. The method also includes selecting, by the test processor, one or more of the plurality of commands for testing the application based on at least one criteria, and executing, by the test processor, the one or more selected commands.

Abstract: A system and methods are provided for distributed tracing in a distributed application. In one embodiment, a method includes observing a plurality of messages sent and received among components of the distributed application, generating a probabilistic model of a call flow from observed messages of the distributed system, and constructing a call flow graph based on the probabilistic model for the distributed application. Distributed tracing may include observing messages by performing the subscription-based observation techniques and operations to receive, message traces describing messages being communicated among components of the distributed application. In this regard, the tracing service may merge message traces from different instrumentation points with message traces obtained by observing message queues to generate a probabilistic model and call flow graph.

Abstract: A system and method for software deployment, where the system and method include, at a deployment service, obtaining a software package and determining that a client device is ready to receive at least a portion of the software package. If the client device is ready, providing at least the portion of the software package to the client device, launching at least the provided portion of the software package as set of instructions executing in a test container, and performing a set of tests on the executing set of instructions in the test container. Based at least in part on results of performing the set of tests, determining whether to cause at least the provided portion of the software package to execute in an active container on the client device.

Abstract: Methods and systems for performing mainframe batch testing and/or property-based validation testing using a finite-state machine are provided. According to certain aspects, a validation server may receive a set of batch data designed to validate a property under test, such as during mainframe batch testing. A validation server may validate that the set of batch data is in a proper format. The validation server may then cause a finite-state machine to process instructions contained within the set of batch data. Once the finite-state machine processes the set of batch data, the validation server may then validate that the finite-state machine adheres to the property under test. If the validation fails, the validation server may generate an error report describing the failure.

Abstract: A method includes performing an integration test on executable software units. The integration test fails and identifies a symptomatic executable software unit at which the failure of the integration test is detected. One or more modified source code files, including instructions likely responsible for the failure of the integration test, are located from a plurality of modified source code files. The location involves searching a binary change database for change history records relating to both the plurality of modified source code files and the executable software units. Degrees of functional interaction between portions of modified source code files corresponding to the change history records and portions of a source code file corresponding to the symptomatic executable software unit are determined. Based on this determination, the modified source code file(s) including the instructions likely responsible for the failure of the integration test are identified.

Abstract: An information processing device includes a plurality of processors each of which is coupled to at least some of the plurality of processors. A first processor from among the plurality of processors is configured to calculate a plurality of communication paths between a second processor and a third processor from among the plurality of processors, identify a communication path that does not pass through a processor that is a target of dynamic reconfiguration, as a path to be used, from among the plurality of calculated communication paths, and transmit information on the identified path to be used, to a processor on the identified communication path. The processor that receives from the first processor the information on the identified path executes communication processing between the second processor and the third processor, by using the communication path that is indicated by the received information on the path to be used.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for model based configuration parameter management. An association module is configured to group a plurality of erase blocks of a non-volatile memory medium based on an amount of time since data has been written to the plurality of erase blocks. A read module is configured to sample data of at least two word lines from at least one erase block from each of a plurality of groups of erase blocks. A configuration parameter module is configured to determine different read voltage thresholds for different word lines of groups of erase blocks using different read voltage threshold models for different groups based on sampled data.

Abstract: A memory system and method are provided for performing garbage collection on blocks based on their obsolescence patterns. In one embodiment, a controller of a memory system classifies each of the plurality of blocks based on its obsolescence pattern and performs garbage collection only on blocks classified with similar obsolescence patterns. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The embodiments relate to a computer system, computer program product and method for managing a garbage collection process. Processing control is obtained based on execution of a load instruction and a determination that an object pointer to be loaded indicates a location within a selected portion of memory undergoing a garbage collection process. The determination includes identifying a base address and size of a first memory block subject to the garbage collection, subdividing the first memory block into sections, assigning a binary value to each section, and determining if the first memory block corresponds to the enabled section. An image of the load instruction is obtained and a pointer address is calculated from the image. The object pointer is read and it is determined whether the object pointer is to be modified. The object pointer is modified and stored in a selected location.

Abstract: The present invention relates to an interleaving and de-interleaving method, an interleaver and a de-interleaver. The interleaving method includes: receiving N×M frames of data, and sequentially storing, with each frame as a unit, the N×M frames of data in storage space indicated by N×M addresses of a first storage unit; transferring the data stored in the storage space indicated by an ((X?1)×M+Y+1)th address of the first storage unit to the storage space indicated by a (Y×N+X)th address of a second storage unit; and according to an address sequence, outputting the data stored in the space indicated by the N×M addresses of the second storage unit frame by frame. The interleaving and de-interleaving solutions of the present invention have low implementation complexity, and high capacity of correcting a burst bit error.

Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.

Abstract: A storage system includes control devices and a second processor. The second processor determines a number of abnormal batteries when an abnormality has occurred in a first battery. The second processor assigns a second cache currently assigned to a second control device associated with the first battery to a first control device when the number is smaller than a threshold. The second processor assigns a mirror cache currently assigned to the second control device to a third control device when the number is smaller than the threshold. The second processor instructs the first control device to control write to a first storage device associated with a first cache by using the first cache. Data of the first cache is mirrored to the mirror cache. The second processor instructs the first control device to control write to a second storage device associated with the second cache by using the second cache.

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract: Improved techniques for maintaining cache coherence in a consistent state are provided. These techniques implement a data storage system using a journaled mirrored cache that ensures that storage operations making up certain transactions be performed atomically, so that a system failure does not result in data loss. The improved techniques also allow for efficient communication of mirroring information.

Abstract: Accessing partial cachelines in a data cache including storing a first portion of a cacheline in a cache entry of the data cache; relaunching a load instruction targeting a second portion of the cacheline, wherein the second portion of the cacheline is not stored in the data cache; determining that the load instruction targets a portion of the cacheline not stored in the cache entry; storing the second portion of the cacheline in the data cache; and reading the second portion of the cacheline from the data cache according to the load instruction.

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

Abstract: A method is provided for cache coherence being based on a hybrid approach relying on hardware-and software-implemented functionalities. In case a processor core is requested to perform a write operation on a memory line missed in the local cache of said core, a hardware-implemented coherence directory ensures that said processor core becomes assigned exclusive write permissions to indicate that the memory line in said local cache is up-to-date after said write. In case the processor core is requested to perform a read operation on a memory line missed in the local cache of said processor core, the coherence directory updates the coherence directory to indicate that none of the processor cores of the system has exclusive write permission on the memory line and relies on software executed on said processor core to ensure that the cached memory line is up-to-date before performing the read operation.

Abstract: The storage device of the present invention provides a decompression VOL having no corresponding relationship (mapping) with a final storage media to a superior device, and receives accesses from the superior device to the decompression VOL. Then, data written into the decompression VOL is compressed on-line in a cache memory, and the compressed data is mapped to a compression VOL which is a volume mapped to a final storage media. At the same time, by maintaining and managing a mapping information between an area in the decompression VOL where data has been written and a location in the compression VOL to which compressed data of the relevant data is mapped, when a read request is received from a superior device regarding the decompression VOL, the storage device converts a location information in the decompression VOL designated by the read request to a location information of the final storage media.

Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a write request including data to be written to the cache storage device. The logic is also configured to determine a size of the write request. Moreover, the logic is configured to select a chunk size from among a plurality of chunk sizes designated for storing data in the cache storage device. In addition, the logic is configured to allocate a fine block descriptor (FBD) having the selected chunk size to the write request.

Abstract: A method, device, and non-transitory computer readable medium that dynamically allocates cache resources includes monitoring a hit or miss rate of a service level objective for each of a plurality of prior workloads and a performance of each of a plurality of cache storage resources. At least one configuration for the cache storage resources for one or more current workloads is determined based at least on a service level objective for each of the current workloads, the monitored hit or miss rate for each of the plurality of prior workloads and the monitored performance of each of the plurality of cache storage resources. The cache storage resources are dynamically partitioned among each of the current workloads based on the determined configuration.

Abstract: A cache managing method of a display driving apparatus may be provided. The display driving apparatus including an encoder to generate compressed data by compressing raw data, a memory to store the compressed data, and a decoder to restore the compressed data and including a payload cache may be provided. The cache managing method including requesting an access to the compressed data, and managing the payload cache using a linked list according to the access request to the compressed data may be provided.

Abstract: Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.

Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.

Abstract: A logical address key is generated based at least in part on a logical address. Encoded data is generated by systematically error correction encoding the logical address key and write data. One or more physical addresses are determined that correspond to the logical address where the physical addresses that correspond to the logical address are dynamic. At the physical addresses, the encoded data is stored with the logical address key removed.