Abstract: A set of first signal light and reference light with a phase difference of almost 0 degree, a set of second signal light and reference light with a phase difference of almost 180 degrees, a set of third signal light and reference light with a phase difference of almost 90 degrees, and a set of fourth signal light and reference light with a phase difference of almost 270 degrees are generated. A first differential signal as a difference between a first light-receiving signal obtained by a first light-receiving element and a second light-receiving signal obtained by a second light-receiving element is calculated, and a second differential signal as a difference between a third light-receiving signal obtained by a third light-receiving element and a fourth light-receiving signal obtained by a fourth light-receiving element is calculated. The first differential signal and the second differential signal are supplied to respective FIR filters.

Abstract: Various systems and methods may benefit from determination of environmental signatures in recordings. For example, such signatures may aid forensic analysis and alignment of media recordings, such as alignment of audio or video recordings. A method can include extracting electric network frequency signals from an image sequence of a video recording or an audio recording. The method can also include synchronizing the video recording or the audio recording with at least one other datum based on the electric network frequency signals.

Abstract: Systems and methods for determining an occurrence of non-operation shock (NOS) in a disc drive are described. Such determining may be used to determine whether or not the disc drive should be recalibrated or compensated to account for changes induced by NOS. Determining NOS may be based at least in part on a harmonic of the spindle of the disc drive other than the first harmonic, such as a third harmonic of the spindle. In some embodiments, determining NOS may be based on the first harmonic of the spindle and at least one other harmonic of the spindle.

Abstract: Systems and methods for forward corrupted track detection and by-pass are described. In one embodiment, a storage system comprising a storage controller performs a read operation for a target track of a shingled magnetic recording (SMR) disk drive and detects a read operation failure of the read operation for the target track. The storage controller also performs a boundary track read operation on one or more tracks including or adjacent to the target track and detect a forward corruption area based on the boundary track read operation. In another embodiment, a method is provided that includes detecting a read operation failure of a read operation for a track of a disk drive and performing a boundary track read operation on one or more tracks including or adjacent to the target track. The method also includes detecting a forward corruption area based on the boundary track read operation.

Abstract: A device for recording and/or reading data to and/or from a magnetic tape includes a read/write head which has a first device set including a first plurality of magnetic data write and/or read elements and a second device set including a second plurality of magnetic data write and/or read elements. The device also includes a lateral positioning actuator and an azimuth actuator. The lateral positioning actuator and azimuth actuator are used together to position both device sets on the magnetic tape. The lateral positioning actuator laterally positions the read/write head such that during write and/or read operations the first and second pluralities of magnetic data write and/or read elements align laterally to first and second pluralities of recordable and/or readable data tracks on the magnetic tape. The azimuth actuator rotates the read/write head about an azimuthal angle. such that the elements align to lateral spacings.

Abstract: According to one exemplary embodiment, a method for editing at least one media file on a device is provided. The method may include receiving the at least one media file. The method may also include determining a content of interest region within the at least one media file. The method may then include generating an at least one edited media file based on the content of interest region and the at least one media file. The method may further include transmitting the at least one edited media file to a target destination.

Abstract: A computer implemented method and apparatus for editing video scenes based on learned user preferences. The method comprises identifying a plurality of scenes in a video; for each scene of the plurality of scenes: applying an effect to a representative frame of a scene, wherein the effect is based on learned user preferences; receiving an input that adjusts at least one effect on the representative frame; updating user preferences based on received input; and applying the at least one effect to all frames of the scene; interpolating the adjusted at least one effect at a boundary of two consecutive scenes; and applying the interpolated at least one effect to transitional frames between the two consecutive scenes.

Abstract: Video information defining video content may be accessed. The video content may include video frames. Motion vectors for the video frames may be determined. The motion vectors may represent motion of one or more visuals captured within individual video frames. A transformation matrix for the video frames may be determined based on the motion vectors. The transformation matrix may characterize rigid transformations between pairs of the video frames. Shakiness metrics for the video frames may be determined based on the transformation matrix. A shakiness threshold may be obtained. One or more of the video frames may be identified based on the shakiness metrics, the shakiness threshold, and algorithms with hysteresis or finite-state machines. A video summary of the video content may be generated. The video summary may include the one or more identified video frames.

Abstract: An electronic device is provided. The electronic device includes a voice input module which receives a voice from an outside to generate voice data, a memory which stores one or more images or videos, and a processor which is electrically connected to the voice input module and the memory. The memory includes instructions, when executed by the processor, causing the electronic device to link at least one of the voice data, the first metadata information based on the voice data, or second metadata information generated from the voice data and/or the first metadata information with the second image or video.

Abstract: A mobile terminal including a touchscreen; and a controller configured to display a video list in a first region of the touchscreen, display a selected video from the video list in a second region of the touch screen different than the first region, in response to a first type of input for selecting the video, and display the selected video in the first region of the touch screen, in response to a second type of input for selecting the video different than the first type of touch input. Further, the first type of input corresponds to a direct touch input to the touchscreen, and the second type of input corresponds to a proximity touch input to the touchscreen.

Abstract: Embodiments of a system and method for emotional tagging are generally described herein. A method may include receiving, at a device, biometric data and a timestamp, analyzing the biometric data to determine an emotional reaction occurred, tagging a portion of content with an emotional content tag based on the emotional reaction, wherein the portion of content was playing during a time corresponding to the timestamp, and sending the portion of content and the emotional content tag to a server. A method may include aggregating content tagged as emotional content, generating an emotional content video segment, and providing the emotional content video segment.

Abstract: In one embodiment, a capture video is received that is captured during the playback of a trace video on a media player on a hardware platform. The capture video may be an external capture of a display of the trace video on the media player. To allow the external capture to be analyzed, the trace video may include visible codes on frames of the trace video that can be captured by a capture device. Particular embodiments analyze the frames of the capture video to extract identifiers associated with the visual codes on the frames. Events that occurred during playback are determined by analyzing a sequence of identifiers from the capture video to an expected sequence of identifiers from the trace video. Then, particular embodiments determine whether an API call from the media player was received that corresponds to the event while the media player was playing the trace video.

Abstract: An apparatus comprises a spindle to rotate a magnetic recording medium and a magnetic field generator to expose a track of the medium to a DC magnetic field. The magnetic field generator is configured to saturate the track during an erase mode and reverse the DC magnetic field impinging the track during a writing mode. A laser arrangement heats the track during the erase mode and, during the writing mode, heats the track while the track is exposed to the reversed DC magnetic field so as to write a magnetic pattern thereon. A reader reads the magnetic pattern and generates a read signal. A processor is coupled to the reader and configured to determine an anisotropy parameter using the read signal. The apparatus can further comprise a Kerr sensor that generates a Kerr signal using the magnetic pattern.

Abstract: A method of servicing a data storage library having at least one access opening and at least one access door to permit access to an interior of the data storage library, the method including providing at least one barrier configured to at least partially surround the at least one library access opening when the at least one access door is opened, wherein the at least one barrier is configured to resist environmental conditions from exterior the barrier and data storage library from intruding into the interior of data storage library when the barrier is deployed. The method also includes deploying the at least one barrier when the at least one access door is opened to form an interior working space, accessing the interior space formed by the at least one barrier, and accessing the interior of the data storage library via the at least one library access opening.

Abstract: The invention relates to an assembly for securing a slide-in unit in a mounting cage of a computer system. The mounting cage has a first side panel and a second side panel opposite the first side panel. The first side panel has at least one engagement element for engaging into a lateral fastening opening of the slide-in unit. The first side panel and the second side panel are arranged at a distance to one another such that the slide-in unit can be inserted into the mounting cage past the engagement element. After the insertion, a fastening element secured to the second side panel cooperates with the slide-in unit in such a way that the slide-in unit is pushed in the direction of the first side panel and the engagement element engages in the respective lateral fastening opening of the slide-in unit.

Abstract: A data storage library includes at least a first library portion and at least a second library portion, wherein the second library portion is configured to store and receive media associated with data storage cartridges and comprises an environmental conditioning unit configured to control environmental conditions within the second library portion to be different than environmental conditions external to the second library portion. The data storage library also includes at least one acclimation chamber formed by the first library portion, wherein the at least one acclimation chamber permits gradual transition of environmental condition(s) within the at least one acclimation chamber toward at least one of the corresponding environmental condition(s) external and internal to the second library portion.

Abstract: A data storage system assembly includes a hermetically-sealed enclosure, a double-barrier sealing system comprising first and second sealing members spaced from each other, and a vacuum source that operates in the space between sealing members to generate a lower pressure in the space than in the enclosure. A lighter-than-air gas may be enclosed in the enclosure, and a plurality of non-hermetically-sealed data storage devices may be housed within the enclosure. Air, humidity, and other contaminants may be intercepted by the vacuum system rather than leak into and pollute the sealed internal environment of the storage system enclosure.

Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

Abstract: A memory macro includes a plurality of columns and a plurality of switching circuits. A column of the plurality of columns has a plurality of voltage supply nodes corresponding to a plurality of memory cells in the column. A switching circuit of the plurality of switching circuits corresponds to a column of the plurality of columns and is configured to selectively provide a first voltage value of a first voltage source or a second voltage value of a second voltage source to the voltage supply nodes. The first voltage value and the second voltage value differ by a predetermined voltage value.

Abstract: A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column.

Abstract: An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

Abstract: Systems and methods are provided for parallel column twist interleaving. Parallel bit-interleaving with column twist may be applied to an input bitstream based on one or more interleaving parameters. Bits in the input bitstream may be read, in sets having size based on a first interleaving parameter, and may then be processed based on a second interleaving parameter. The processing may comprise applying a shift to a combination of bits that include a current bit set and additional bits corresponding to previously processed bit sets and/or pre-set bits. The shift may be determined based on a column twist associated with the current corresponding. Bits generated based on processing in current and/or previous cycles may be stored into memory, and bits may be read from the memory, based on a third interleaving parameter, for generating an output interleaved bitstream.

Abstract: An I/O control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Abstract: A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.

Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.

Abstract: A circuit includes a first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store a first and a second logic values, respectively. The current sense amplifier is configured to couple the first reference cell to a first node of the current sense amplifier, and couple the second reference cell to a second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

Abstract: A semiconductor device includes a first row address generation circuit and a second row address generation circuit. The first row address generation circuit generates a first row address for refreshing memory cells connected to word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal. The second row address generation circuit generates a second row address for refreshing memory cells connected to word lines included in a first down block and a second down block from the refresh command and the active signal in response to the period selection signal and a second period signal.

Abstract: Provided is a periodic signal generation circuit including: a clock generation unit suitable for generating first to Nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “N”; a pulse generation unit suitable for generating first to Nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “N” by combining two or more clocks among the first to Nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to Nth periodic pulses depending on combination information.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. The second semiconductor device extracts an active signal, a pre-charge signal, and addresses from the command/address signal, performs an active operation on a memory cell corresponding to the addresses, and performs a refresh operation on the memory cell corresponding to counting signals generated by counting a number of pulses in a refresh signal.

Abstract: A system for measuring an access time of a memory includes a first delay unit configured to delay a clock signal by a first delay time and to output a first delayed clock signal, a second delay unit configured to delay the clock signal by a second delay time greater than the first delay time and to output a second delayed clock signal, a memory configured to store data, the data being read from the memory in response to the first delayed clock signal, a detection data storage configured to store the data read from the memory in response to the second delayed clock signal, and a controller configured to measure an access time of the memory based on a comparison of the data in the detection data storage and the data in the memory, the first delayed clock signal and the second delayed clock signal.

Abstract: An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell in the array may be a single-port or a multiport memory cell. Memory cells in the same column of the array are connected to shared bit lines, whereas memory cells in the same row of the array are connected to shared word lines. The memory cells in the same row may also be connected to a row control line. During normal operations, the row control line may provide a positive power supply voltage to each memory cell along that row. During write operations, the row control line may be driven to ground or tri-stated to help improve the write margin and the write performance of the selected memory cells. The aspect ratio of these memory cells may also be more square-like or balanced to help improve power delivery.

Abstract: Predicting data correlation using multivalued logical outputs in SRAM storage cells including generating a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points; writing, into storage cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each storage cell; and measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs.

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.

Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD-11 and PD-12) of the first inverter; and a second contact feature contacting second two pull-down devices (PD-21 and PD-22) of the second inerter.

Abstract: A method of sensing a resistance change memory device includes preparing a memory cell including a variable resistance element storing different data on the basis of a variable resistance, and a switching element connected to the variable resistance element and performing a threshold switching operation, measuring a first cell current by applying a first read voltage to the memory cell, the first read voltage being selected in a threshold-sensing range of a current-voltage characteristic curve of the memory cell, measuring a second cell current by applying a second read voltage to the memory cell, the second read voltage being selected in a resistance-sensing range of the current-voltage characteristic curve, and when at least one of the first cell current and the second cell current is greater than a corresponding reference current, outputting a data signal having a first logic value as data stored in the memory cell.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.

Abstract: A storage device includes nonvolatile memories and a device controller configured to store data being received from an external device in an internal RAM, according to a command and an address being received from the external device. The device controller controls the nonvolatile memories according to the data stored in the internal RAM, distinguishes whether phase bits received with the data and also stored in the internal RAM are valid, and processes the data stored in the internal RAM when the phase bits are valid.

Abstract: A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being parallel with the rows and including a couple of first selection lines connected to each of the local blocks, second selection lines disposed in parallel with the columns, and local block selectors disposed between the plurality of local blocks. Each of the local block selectors is disposed between a Qth wherein, “Q” is an odd number local block and a (Q+1)th local block among the local blocks to electrically connect unit cells disposed in any one of the Qth local block and the (Q+1)th local block to the second selection lines. The unit cells in the local blocks are disposed at cross points of the first selection lines and the second selection lines, respectively. Each of the unit cells includes a P-channel MOSFET.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.

Abstract: A display panel includes shift registers coupled in serial. At least one of the shift registers includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.

Abstract: Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.