Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.

Abstract: A semiconductor device includes: a semiconductor substrate; a heat sink mounted on an upper surface of the semiconductor substrate; wirings formed on a lower surface of the semiconductor substrate; and the like. The heat sink is mounted on the upper surface of the semiconductor substrate, and a planar size thereof is approximately the same as that of the semiconductor substrate. Moreover, the heat sink has a thickness of 500 ?m to 2 mm, and may be formed to be thicker than the semiconductor substrate. By using the heat sink to reinforce the substrate, a thickness of the semiconductor substrate can be reduced to, for example, about 50 ?m. As a result, a thickness of the entire semiconductor device can be reduced.

Abstract: A semiconductor wafer is provided with a substrate, a GaN type semiconductor film which is laminated on the substrate, a plurality of element regions which are provided on the GaN type semiconductor film, a dielectric film which is laminated on the GaN type semiconductor film, and a dicing region which has a dicing groove which is provided in a lattice form without passing through the dielectric film described above so as to partition the element regions described above. Then, an end on the element region side of the dicing groove is higher or lower than a central portion of the dicing groove in a width direction in a bottom surface of the dicing groove.

Abstract: A semiconductor substrate (1) is provided with integrated circuits. Dicing trenches (7) are formed in the substrate (1) between the integrated circuits, a polyimide layer (8) spanning the trenches (7) is applied above the integrated circuits, a tape layer (14) is applied above the polyimide layer (8), and a layer portion of the substrate (1) is removed from the substrate side (17) opposite the tape layer (14), until the trenches (7) are opened and dicing of the substrate (1) is thus effected. The polyimide layer (8) is severed in sections (18) above the trenches (7) when the tape layer (14) is removed. The semiconductor chip is provided with a cover layer (11) laterally confining the polyimide layer (8) near the trenches (7), in particular for forming breaking delimitations (9).

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and applying a pressure substantially uniformly along the second major surface to batch separate the layer of material in the singulation lines. In one embodiment, a fluid filled vessel can be used to apply the pressure.

Abstract: After forming source/drain contact structures within an interlevel dielectric (ILD) layer to contact source/drain regions of a field effect transistor (FET), the ILD layer is recessed to expose upper portions of the source/drain contact structures. A sacrificial layer is then formed on a remaining portion of the ILD layer to laterally surround the upper portions of the source/drain contact structures. An interconnect conductor portion is subsequently formed to contact the source/drain contact structures by subtractive patterning of a metal layer that is formed on the sacrificial layer. Next, the sacrificial layer is removed, leaving a void between the interconnect conductor portion and the remaining portion of the ILD layer. An interconnect liner layer is then formed on a top surface and sidewalls of the interconnect conductor portion and on the remaining portion of the ILD layer. The interconnect liner layer encloses an air gap surrounding the upper portions of the source/drain contact structures.

Abstract: Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion.

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.

Abstract: Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

Abstract: A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.

Abstract: The display element manufacturing apparatus has a transporting part, which transports a substrate in a first direction, a first alignment system, which detects fiducial marks, a second alignment system, which is arranged at a prescribed distance from the first alignment system in the first direction and detects fiducial marks, calculating parts, which detect the fiducial marks and calculate the expansion/contraction of the substrate in the first direction or the transport speed of the substrate, and a processing part, which processes a prescribed position of the substrate based on at least one of the expansion/contraction of the substrate in the first direction or the transport speed of the substrate and the fiducial marks.

Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.

Abstract: A printed wiring board includes a first circuit board having a first surface and a second surface, and a second circuit board having a third surface and a fourth surface and having a mounting area on the third surface of the second circuit board. The first circuit board is laminated on the third surface of the second circuit board such that the first surface of the first circuit board is in contact with the third surface of the second circuit board, the first circuit board includes reinforcing material and has an opening portion exposing the mounting area of the second circuit board, and the first circuit board and the second circuit board are formed such that a ratio H1/h1 is in a range that is greater than 0.75 and smaller than 2.4, where H1 represents a thickness of the first circuit board and h1 represents a thickness of the second circuit board.

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Abstract: A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.

Abstract: A temperature-controlled integrated circuit configured with a secure data processing element, and method of manufacture of same, is disclosed. Specifically, the temperature-controlled integrated circuit, comprising a secure data processing element operable within a nominal operating range, is configured with a heat-transfer element which allows the secure data processing element to operate in an extended operating range.

Abstract: Embodiments of the present invention provide a heat dissipater and relate to the communications field. The heat dissipater includes a sub heat dissipater, a connecting apparatus, and a shared bracket; the sub heat dissipater is connected to the shared bracket through the connecting apparatus; the sub heat dissipater includes a first heat conducting surface, and the sub heat dissipater contacts a first heat source through the first heat conducting surface to dissipate heat for the first heat source; the shared bracket includes a second heat conducting surface, and the shared bracket contacts a second heat source through the second heat conducting surface to dissipate heat for the second heat source; and the second heat conducting surface and the sub heat dissipater are disposed in different positions of the shared bracket respectively.

Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary semiconductor structure includes an insulation material layer having a top semiconductor layer having transistor regions formed on a top surface of the insulation material layer; isolation structures formed in the top semiconductor layer between adjacent transistor regions; a first dielectric layer formed over the top semiconductor layer; a first heat-conducting layer having a thermal conductivity higher than a thermal conductivity of the isolation structure and passing through the insulation material layer, the top semiconductor layer and the first dielectric layer; a second dielectric layer formed over the first dielectric layer; an interconnect structure formed in the second dielectric layer; and a bottom layer conductive via passing through the heat-conducting layer and a partial thickness of the second dielectric layer, and electrically connected with the interconnect structure.

Abstract: A semiconductor device includes an insulating substrate; a semiconductor element mounted on the insulating substrate; and a radiation block bonded to the semiconductor element. The radiation block includes a three-dimensional radiation portion and a base portion connected to the radiation portion. The radiation portion of the radiation block has a pin shape, a fin shape, or a porous shape.

Abstract: Thermal conductive compositions, methods for their preparation, and use are provided, which include, for example, as thermal sinks, heat transfer systems, and other uses.

Abstract: A heat sink comprises a base and a fin support larger in area than the base and supporting fins that may be positioned in a plurality of orientations relative to the base. The base is adapted for being connected to a heat-generating electronic component on a circuit board, and the heat sink dissipates heat generated by the heat-generating electronic device and conducted through the base and the fin support to the fins supported thereon. The heat sink dissipates heat from the heat-generating electronic device in a first operable position and in a second operable position. The heat sink may be moved from the first to the second operable position to facilitate access to electrical contacts proximal the heat-generating electronic component.

Abstract: A method and an apparatus for cooling a semiconductor device. The method comprises the steps of contacting a surface of the semiconductor device with respective end portions of an array of contact elements thermally coupled to a cooling fluid, and disposing a flexible, heat conductive sheet between the respective end portions of the contact elements and the surface of the semiconductor device for transferring heat generated in the semiconductor device to the cooling fluid via the sheet and the contact elements.

Abstract: A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.

Abstract: Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

Abstract: A semiconductor device PKG includes a semiconductor chip CP, a lead LD3, a wire BW5 electrically connecting a pad electrode PD2 of the semiconductor chip CP to the lead LD3, a wire BW3 electrically connecting a pad electrode PD3 of the semiconductor chip CP to the lead LD3, and a sealing body sealing them with a resin. The semiconductor chip CP includes internal circuits 5b and 5c, and a switch circuit unit SW. Signal transmission is possible between the internal circuit 5c and the pad electrode PD3. The switch circuit unit SW is a circuit capable of being set in a first state in which signal transmission is possible between the internal circuit 5b and the pad electrode PD2, and in a second state in which signal transmission is not possible between the internal circuit 5b and the pad electrode PD2. The switch circuit unit SW is fixed to the second state during operation of the semiconductor device PKG.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.

Abstract: A package is formed by a thermal base and a leadframe assembly. The thermal base includes a body of thermally conductive material having a top surface, wherein the top surface of the body includes a pedestal. An integrated circuit chip is mounted to the pedestal, the integrated circuit chip including bonding pads. The leadframe assembly includes leads and an encapsulant ring that partially embeds the leads. The leadframe assembly is mounted to the top surface of said body surrounding the pedestal. The pedestal is configured with a thickness that positions the bonding pad at a height substantially coplanar with the leads. Bonding wires extend from the bonding pads to the leads with a shortened length so as to provide for improved electrical characteristics of frequency response, impedance and inductance.

Abstract: A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets.

Abstract: A dielectric element has a plurality of contacts at a first surface and a plurality of first traces coupled thereto which extend in directions parallel to the first surface. A circuit structure made of a plurality of dielectric layers and electrically conductive features thereon includes a plurality of bumps at a first surface which face the contacts of the dielectric element and are joined thereto. Circuit structure contacts at a second surface opposite the first surface are electrically coupled with the bumps through second traces on the circuit structure, the circuit structure contacts configured for connection with a plurality of element contacts of each of a plurality of microelectronic elements, wherein the microelectronic elements can be assembled therewith such that element contacts thereof face and are joined with the circuit structure contacts.

Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

Abstract: Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers a surface of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed.

Abstract: A wiring board of the present disclosure includes a core substrate, insulating layers, signal wiring conductors, ground wiring conductors, power-supply wiring conductors, a first mounting portion on which a first semiconductor device is to be mounted, a second mounting portion on which a second semiconductor device is to be mounted, many first-semiconductor-device connection pads connectable to signal electrodes of the first semiconductor device, many second-semiconductor-device connection pads connectable to signal electrodes of the second semiconductor device, and many signal connection conductors that connect the first-semiconductor-device connection pads to the second-semiconductor-device connection pads.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Abstract: A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

Abstract: Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.

Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.

Abstract: A semiconductor device includes a semiconductor layer comprising an upper surface and a recess through the upper surface and including a lower part, an upper part, and a side surface, the side surface terminating at the upper surface at an upper edge, an insulating member in the lower part of the recess, an insulating film comprising a first portion on the upper edge of the recess, a second portion on the side surface of the recess in the upper part thereof, and a third portion on a portion of the semiconductor layer adjacent to the upper edge of the recess, and an electrode on the insulating member and the portion of the insulating film covering the upper edge of the recess. The first portion of the insulating film is thinner than thicknesses of each of the second and third portions thereof.

Abstract: As means for preventing a leakage of a fuse element cut by laser trimming due to a conductive residue or the like, an insulating film which has a high thermal conductivity and a relatively low adhesion is formed between an element isolation region and the fuse element in the case of forming the fuse element on the element isolation region in a groove on a main surface of an epitaxial substrate. When the fuse element is cut by performing the laser trimming, both of a part of the fuse element and the insulating film below the part of the fuse element are removed.

Abstract: A corrosion-resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. An array of intersecting metal lines forming windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent entry of moisture.

Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.