Abstract: Memristor-based adders using memristors-as-drivers (MAD) gates. As a result of employing MAD gates in memristor-based adders, such as ripple carry adders, carry select adders, conditional sum adders and carry lookahead adders, the number of delay steps may be less than half than the number of delay steps required in traditional CMOS implementations of adders. Furthermore, by using MAD gates, memristor-based adders can be implemented with less complexity (e.g., fewer memristors and drivers). As a result, by the memristor-based adders using MAD gates, the speed and complexity of a wide variety of arithmetic operations is improved.

Abstract: A method for scaling a cloud infrastructure, comprises receiving at least one of resource-level metrics and application-level metrics, estimating parameters of at least one application based on the received metrics, automatically and dynamically determining directives for scaling application deployment based on the estimated parameters, and providing the directives to a cloud service provider to execute the scaling.

Abstract: An object class (Class1) in a computer system is dynamically created by creating a global generic class (GenericClass) having two possible members, wherein at least one member is an instance of a generic class (GenericAttribute, GenericMethod), and by instantiating the global generic class.

Abstract: A multi-display system for management of a software development project having a graphical user interface including interactive user interface elements representing one or more tasks in the software project, first and second source code databases, first and second object code databases, a migration module configured to migrate source code from the first source code database to the second source code database and migrate object code from the first object code database to the second object code database in response to a user input to the graphical user interface, a first output module for executing the one or more blocks of object code and displaying an output of the executed object code stored in the first object code database, a second output module for executing the one or more blocks of object code and displaying an output of the executed object code stored in the second object code database.

Abstract: Embodiments of the present invention provide methods, program products, and systems for modifying source code by managing symbols indicating executable instructions. Embodiments of the present invention can be used to receive one or more symbols indicating executable instructions to be implemented via source code and generate a visual display comprising a dialog box supporting modification of source code that implements the executable instructions indicated by the one or more symbols. Responsive to receiving a user interaction with the dialog box resulting in modified source code, embodiments of the present invention can be used to generate modified source code or a representation of the modified source code that is shorter than the modified source code.

Abstract: A compiler 134 for compiling a first computer program 110 written in a first computer programming language into a second computer program written in a machine language, the compiler comprises a code generator to generate the second computer program by generating tables 142 and machine language code 144, the generated tables and the generated machine language code together forming the second computer program, wherein the generated machine language code references the tables and the generated machine language code does not contain arithmetic or logic machine instructions, the tables comprising pre-computed results of arithmetic and/or logic machine instructions.

Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.

Abstract: System and method for convergence analysis. One or more state variables of a first program may be determined based on dependencies of variables in a first program. A second program corresponding to the first program is created based on the state variables and their dependencies, and executed multiple times. Each execution may include recording values of the state variables, determining an execution count, comparing the values to corresponding values from previous executions of the second program, and terminating the executing in response to the values matching corresponding values from at least one previous execution of the second program. A convergence property for the first program is determined based on the execution count, and indicating a number of executions of the first program required to generate all possible values of the one or more variables. The convergence property is stored, and may be useable to optimize the first program.

Abstract: A computer-implemented method includes, in a code transformation system, identifying save-to-return code instructions, function call code instructions, comparison code instructions, and exceptional code instructions. The function call code instructions are associated with the save-to-return code instructions. The comparison code instructions are associated with the save-to-return code instructions. The exceptional code instructions are associated with the comparison code instructions. A predefined proximity range based on a predefined proximity value as well as a proximity eligibility indicator are determined. The proximity eligibility indicator denotes whether the save-to-return code instructions and the comparison code instructions are within the predefined proximity range.

Abstract: An application name modification method, said method comprising: selecting a target application and, by means of a preset application inlet, modifying the application name of the selected target application; obtaining original information regarding the selected target application, and linking together and storing the obtained original information regarding said target application and the modified new application name. Additionally disclosed are an application name modification device and a computer-readable storage medium.

Abstract: Disclosed are a method and an apparatus of downloading and installing a client. The method includes: upon receiving a request message of downloading client software that includes an identifier of the client software from a user terminal, a server obtaining account information of a user and installation information of the client software corresponding to the identifier of the client software, and sending the obtained account information and installation information of the client software to the user terminal.

Abstract: Embodiments of the disclosure are directed to a persistent enrollment of a device in a management system. Upon detection of a triggering event, detection of whether an activator application is installed is performed. Then, detection of whether an agent application is installed also performed. The agent application can then complete an enrollment of the device with a management system. Certain components of such a process can be bundled with the device operating system or as a system application.

Abstract: Techniques are described for standardizing software configuration levels across targets. In one embodiment, a subscription is maintained that identifies a group of targets that subscribe to a particular image, where the particular image represents a standard to follow for targets that belong to the group of targets. The particular image may further include a first image version having a first set of source components. In response to receiving an update to the particular image, a second image version is generated for the particular image, where the second image version includes a second set of source components that are different than the first set of source components. Two or more targets in the group of targets that subscribe to the particular image may be updated based on the second image version.

Abstract: Updating web resources includes downloading an application to a client device, extracting web resources from the application to local files, and querying an external server for web resource updates specific to at least one operating condition of the client device.

Abstract: A tool for creating and editing applications on a mobile device. The tool searches the mobile device for one or more exposed features of a plurality of currently installed applications on the mobile device. The tool exposes a workspace using a graphical programming language on the mobile device. The tool receives a plurality of selections in the workspace. The tool receives a configuration of the plurality of received selections in the workspace. The tool determines, based on the configuration of the received selections in the workspace, the application is complete. The tool prompts to save the completed application.

Abstract: An improved integrated avionics system having a plurality of line replacement units (LRUs) is disclosed. At least one LRU stores in its memory software and configuration data stored and used by another LRU in the system. Upon detecting a new LRU installation, the at least one LRU may be configured to copy to its internal memory the software and configuration data loaded to the new LRU. The LRU may also store a table in its internal memory identifying each LRU that has been installed in the system, when each LRU was installed, and a copy of configuration and software data loaded to each LRU. If one of the LRUs in the system needs to be replaced, the LRU may determine which software and configuration data is applicable to the replaced LRU and load the determined software and configuration data to the new LRU, thereby improving the loading and installation process.

Abstract: A software program is executed, the software program requiring one or more physical interactions with a user through an input/output (I/O) device, wherein each of the one or more physical interactions includes respective predefined dimensions indicating a proficiency in performing one of the one or more physical interactions. The one or more physical interactions are tracked. A familiarity profile for each of the one or more physical interactions is generated based on the respective predefined dimensions for each of the one or more physical interactions. The software program is customized based on the familiarity profile for each of the one or more physical interactions.

Abstract: The disclosed embodiments include methods and systems for providing predictive quality analysis. Consistent with disclosed embodiments, a system may receive input data associated with a software program and compare the input data with one or more predetermined analysis parameters. The system may further determine at least one risk rating based on the comparison, wherein each risk rating corresponds to a distinct software category. The system may perform additional operations, including determining at least one adjustment to the software program based on the determined at least one risk rating, and prioritizing the at least one adjustment based on a predetermined adjustment priority standard. Furthermore, the system may provide a report including at least an indication of the at least one prioritized adjustment, a timeline for implementing the at least one prioritized adjustment, and plan implementing the at least one prioritized adjustment.

Abstract: A system for visualizing a congruency of versions of an application across phases of a release pipeline includes a selecting engine to select a phase from a number of phases; a representing engine to represent, via a user interface (UI), a congruency for a number of versions of an application compared against a target version of the application across the phases of a release pipeline, the congruency for the number of versions of the application represented with identifiers; a differentiating engine to differentiate a latest-deployed version of the application against a planned version of the application in a particular environment; and a comparing engine to compare, based on a selection, properties of the versions of the application.

Abstract: Disclosed are various embodiments for developing versions of applications based on application fingerprinting. For example, an application may be ported from one operating system platform to another, or an application may be modified to be compatible with a specific device. In one embodiment, an application fingerprint is received for an application. The application fingerprint may be generated based at least in part on a static analysis of the application and a dynamic analysis of the application. A device that is incompatible with the application based at least in part on the application fingerprint may be determined. A modification to the application to make the application compatible with the device may be determined.

Abstract: Techniques for merging versions of an inclusion application that is incorporated in a master application are disclosed. One version of an application may be stored as an application that is incorporated into another application. An application that is incorporated into another application may be referred to as an “inclusion application.” An application incorporating another application may be referred to as a “master application.” Additionally, a different version of the application may be stored as an application that is executed independently, without reference to other applications. A merging engine applies a set of conflict resolution rules to the two versions of the application to obtain a merged version of the application. The merging engine incorporates the merged version of the application in the master application.

Abstract: Various embodiments synchronize comments in a source code file with text of a source code document. In one embodiment, a source code document is compared to a corresponding source code file. The source code document comprises a set of text corresponding to a set of source code comment text in the corresponding source code file. The source code document is configured to display the set of text in a stylized format when presented to a user. The set of text in the source code document is determined to be different than the set of source code comment text in the source code file based on the comparison. At least the set of source code comment text in the source code file is automatically changed based on the set of text from the source code document and in response to the determination.

Abstract: Data is received that includes at least a portion of a program. Thereafter, entry point locations and execution-relevant metadata of the program are identified and retrieved. Regions of code within the program are then identified using static disassembly and based on the identified entry point locations and metadata. In addition, entry points are determined for each of a plurality of functions. Thereafter, a set of possible call sequences are generated for each function based on the identified regions of code and the determined entry points for each of the plurality of functions. Related apparatus, systems, techniques and articles are also described.

Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

Abstract: A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a current element position being processed, the execution circuitry sequentially sets one or more data elements of the first vector register to a result, which is generated by the associative reduction operation applied to both a previous data element of the first vector register and a data clement of a third vector register. The previous data element is located more than one element position away from the current element position.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.

Abstract: Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.

Abstract: The present solution targets independent or inter-dependent resource management scenarios such as multi-sensor and other scenarios of possible process/component sharing, intended for individual or group synchronized core task management as part of a flexible long-term solution for monitoring, self-calibration, built-in self-testing, measurements and/or group synchronization dependant strategies. An extension to I2C compatible instruments is described. Disclosed is a module comprising an interpreter sub-module, for receiving and responding to I2C sequences and a register bank module comprising a plurality of registers for storing values. The disclosed module and method of operation can be used for initialization, measurement, and resource management through mixed-signal analog bus scheduling, synchronization and group addressing for built-in calibration strategies for example.

Abstract: Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.

Abstract: A processor is described having an instruction execution pipeline. The instruction execution pipeline includes an instruction fetch stage to fetch an instruction. The instruction identifies an input vector operand whose input elements specify one or the other of two states. The instruction execution pipeline also includes an instruction decoder to decode the instruction. The instruction execution pipeline also includes a functional unit to execute the instruction and provide a resultant output vector. The functional unit includes logic circuitry to produce an element in a specific element position of the resultant output vector by performing an operation on a value derived from a base value using a stride in response to one but not the other of the two states being present in a corresponding element position of the input vector operand.

Abstract: A method is presented for processing one or more instructions to be executed on multiple threads in a Single-Instruction-Multiple-Data (SIMD) computing system. The method includes the steps of analyzing the instructions to collect divergent threads among a plurality of thread groups of the multiple threads; obtaining a redirection array for thread-operand association adjustment among the divergent threads according to the analysis, where the redirection array is used for exchanging a first operand associated with a first divergent thread in a first thread group with a second operand associated with a second divergent thread in a second thread group; and generating compiled code corresponding to the instructions according to the redirection array.

Abstract: A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a list of index values in response to a single vector packed convert a mask register into a list of index values instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.

Abstract: A processor is described, including a fetch circuit to fetch an instruction, including a first source operand identifier, a second source operand identifier, and a destination operand identifier, a decode circuit to decode the instruction, a data retrieval circuit to retrieve data associated with the first source operand identifier and the second source operand identifier, and an execution circuit. In some embodiments, the execution circuit is configured to determine whether a first element of the data associated with the first source operand identifier is set, if the first element is set, to retrieve a destination index from a corresponding second element of the data associated with the second source operand identifier, and to use the destination index to select and set a destination element of data associated with the destination operand identifier.

Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, and building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch. The method further includes assembling a guest instruction block from the instruction sequence. The guest instruction block is translated to a corresponding native conversion block, wherein an at least one native far branch that corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch. Upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.

Abstract: Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained.

Abstract: This multi-user processor system for processing information, of the type including a data exchange engine (3) associated with multiple users (1) of shared resources (2), is characterized in that it includes means (4) for controlling data exchange in the processor, associated with each user, the exchange engine and the shared resources, in order to authorize transactions or not and in that the engine includes means (5) for breaking down authorized transactions into elementary sub-transactions, means (6) for interlacing the sub-transactions obtained from the breaking down of the authorized transactions of several users and the means (6) for distributing these interlaced sub-transactions among the different resources.

Abstract: A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.

Abstract: This disclosure includes a method for performing branch prediction by a processor having an instruction pipeline. The processor speculatively updates a global history register having fetch group history and branch history, fetches a fetch group of instructions, and assigns a global history vector to the instructions. The processor predicts any branches in the fetch group using the global history vector and a predictor, and evaluates whether the fetch group contains a predicted taken branch. If the fetch group contains a predicted taken branch, the processor flushes subsequently fetched instructions in the pipeline following the predicted taken branch, repairs the global history register to the global history vector, and updates the global history register based on branch prediction information. If the fetch group does not contain a predicted taken branch, the processor updates the global history register with a branch history value for each branch in the fetch group.

Abstract: In one embodiment of the present invention, a streaming multiprocessor (SM) uses a tree of nodes to manage threads. Each node specifies a set of active threads and a program counter. Upon encountering a conditional instruction that causes an execution path to diverge, the SM creates child nodes corresponding to each of the divergent execution paths. Based on the conditional instruction, the SM assigns each active thread included in the parent node to at most one child node, and the SM temporarily discontinues executing instructions specified by the parent node. Instead, the SM concurrently executes instructions specified by the child nodes. After all the divergent paths reconverge to the parent path, the SM resumes executing instructions specified by the parent node. Advantageously, the disclosed techniques enable the SM to execute divergent paths in parallel, thereby reducing undesirable program behavior associated with conventional techniques that serialize divergent paths across thread groups.

Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer implemented method for address adjustment in a configuration is provided. The configuration includes a core configurable between an ST mode and an MT mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The primary thread is accessed in the ST mode using a core address value. Switching from the ST mode to the MT mode is performed. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value. The expanded address value includes the core address value concatenated with a thread address value.

Abstract: A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.

Abstract: Apparatuses, methods, systems, and program products are disclosed for dynamically loading firmware based on workloads. A workload module determines a workload configured to be executed on a system. A firmware module determines a firmware configuration associated with the workload. A loading module dynamically accesses the firmware configuration associated with the workload from a remote data store, and loads the firmware configuration on the system prior to execution of the workload.

Abstract: In some implementations, network interface controller (NIC) configuration information can be obtained from a NIC prior to booting up an operating system. For example, a Basic Input Output System (BIOS) can obtain the NIC configuration information from the NIC during the execution of a system check (e.g., Power-On Self-Test). A system controller can receive the NIC configuration information from the BIOS. The system controller can store the NIC configuration information in memory associated with the system controller. A management system can request the NIC configuration information from the system controller using an out-of-band communication channel. For example, the management system can send the request for NIC configuration information to the system controller prior to powering on a server using a dedicated network interface of the system controller.

Abstract: Various features for a computer operating system include mechanisms for operating where a single native application, in the form of a Web browser, exists for an operating system, and all other applications run as Web apps of the browser application. A computer-implemented object tracking method includes instantiating, a first time, an operating system object on a computing device; automatically identifying contextual meta data that defines a state of objects that are open on the computing device, other than the instantiated operating system object, when the operating system object is instantiated; and storing the identifying contextual meta data in correlation with the operating system object, wherein the contextual meta data identifies one or more objects that are active in the operating system when the operating system object is instantiated.

Abstract: An application manager provides anonymized user profile information to third party adaptive software applications. As a result, a software developer may produce a single software application that is adapted to run in a first mode providing full-functionality for use by adults and a second mode providing appropriate privacy and content restrictions for use by children. The mode is selected at run-time based on the anonymized user profile information received from the application manager.

Abstract: Systems and methods are provided for generating interactive user interface pages from a data store. At least a portion of metadata is received from a data store, wherein the appearance and functionality of a plurality of interactive user interface pages is based on the metadata. The display and functionality of an interactive maintenance page is generated based on at least a portion of the metadata, wherein the interactive maintenance page is one of the plurality of interactive user interface pages, and wherein the interactive maintenance page maintains the plurality of interactive user interface pages. One or more instructions are received from the interactive maintenance page. The metadata is updated based upon the one or more instructions, and the appearance and functionality of at least one of the interactive user interface pages and/or the interactive maintenance page is modified based on the metadata.

Abstract: A method performed in a processing unit for finding settings to be used in relation to a sensor unit connected to the processing unit is disclosed. The method comprises inter alia receiving, from the sensor unit, a first identifier identifying a type of the sensor unit, and a second identifier identifying a group of at least one related type of sensor unit. If no settings associated with the first identifier are stored in the processing unit, but settings associated with the second identifier are stored in the processing unit, the processing unit uses the settings associated with the second identifier in relation to the sensor unit.

Abstract: A mechanism for correcting mistakes in error messages in a set of instructions is disclosed. A processing device may receive a set of instructions for a program. The processing device may generate a first table of key-value pairs for a first set of error messages that are within the set of instructions, where keys of the key-value pairs in the first table correspond to error messages and values of the key-value pairs represent symbols to insert into the error messages. A second table of key-value pairs for default error messages may be received. A determination may be made of a mistake for a key of the keys of the key-value pairs in the first table by identifying that the key of the key-value pairs in the first table is not in the second table. A fault message may be generated to indicate the mistake with the key.