Abstract: A method for performing a deferred system dump includes storing a preservation list referencing physical memory addresses allocated to pages by an initial operating system executing on a computer system. The method further includes identifying a subset of the pages that are at least partially allocated below a first physical memory address, relocating the subset to new physical memory addresses above the first physical memory address, and updating the preservation list with the new physical memory addresses. The method further includes transferring control of the computer system from the initial operating system to a subsequent operating system. The subsequent operating system accesses the preservation list to identify preserved pages. The method further includes assigning each of the preserved pages to an address segment in an address space of the subsequent operating system, storing a subset of the preserved pages, and freeing the preserved pages.

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.

Abstract: A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of a cache device, wherein the cache device comprises a plurality of cache units, each cache unit having a plurality of segments, calculating a score for each metadata set, and arranging the metadata sets in a list in ascending order from lowest score to highest score. The exemplary method further includes in response to determining that a cache eviction is to be performed, selecting a cache unit corresponding to the metadata set in the list having the lowest score, without recalculating a score for any of the metadata set, and evicting the selected cache unit. The metadata nay include, for example, segment count metadata, validity metadata, last access time (LAT) metadata, and hotness metadata.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: A computer system processor of a multi-processor computer system having cache subsystem, executes a demote instruction to cause a cache line exclusively owned by the computer system processor to become shared or read-only in the cache subsystem.

Abstract: The present application is directed to employing prefetch to reduce write overhead. A device may comprise a processor and a cache memory. The processor may determine if data to be written to the cache memory comprises multiple cache lines wherein at least one of the cache lines will be fully written. If the data comprises at least one cache line to be fully written, then the processor may perform a “prefetch” wherein the processor may write dummy data to sections of the cache memory corresponding to the data to be written in full cache lines. The processor may then write actual data to the sections containing the dummy data without the processor first having to verify ownership of the sections. Any remaining data that will not be written in full cache lines may then be written to the cache memory utilizing a standard write transaction.

Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

Abstract: Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N?G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N?G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N?G) bits.

Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.

Abstract: A method, medium, and system to receive a request to add a resource to a cache, the resource including a data object and a context item key associated with the resource and uniquely identifying a context of use referenced by the context item key; determine whether the resource is stored in the cache; store, in response to the determination that the resource is not stored in the cache, the resource in the cache; and add the context item key of the resource stored in the cache to a record of reference list of resources.

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

Abstract: In one embodiment, a cache manager releases a list lock during a scan when a track has been identified as a track for cache removal processing such as demoting the track, for example. By releasing the list lock, other processors have access to the list while the identified track is processed for cache removal. In one aspect, the position of the previous entry in the list may be stored in a cursor or pointer so that the pointer value points to the prior entry in the list. Once the cache removal processing of the identified track is completed, the list lock may be reacquired and the scan may be resumed at the list entry identified by the pointer. Other features and aspects may be realized, depending upon the particular application.

Abstract: Provided are a computer program product, system, and method for assigning cache control blocks and cache lists to multiple processors to cache and demote tracks in a storage system. Cache control blocks are assigned to processors. A track added to the cache for one of the processors is assigned one of the cache control blocks assigned to the processor. There are a plurality of lists one list for each of the processors and the cache control blocks assigned to the processor. A track to add to cache for a request is received from an initiating processor comprising one of the processors. One of the cache control blocks assigned to the initiating processor is allocated for the track to add to the cache. The track to add to the cache is indicated on the list for the initiating processor.

Abstract: A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of th

Abstract: Data security access and management may require a server dedicated to monitoring document access requests and enforcing rules and policies to limit access to those who are not specifically identified as having access to the data. One example of operation may include selecting data to access via a user device, identifying a user profile associated with the user device, retrieving at least one user policy associated with the user profile, determining whether the user policy permits the user device to access the data, matching the user policy to a data policy associated with the data, receiving an encryption key at the user device, applying the encryption key to the data, and unwrapping the data from a wrapped data format to access the data.

Abstract: A method for privilege based memory pinning is provided. The method includes receiving a request to pin an amount of address space memory from a process executing on an operating system. The operating system includes a configurable mode of operation. In mandatory mode, the operating system executes the request to pin address space memory based on the role hierarchy-based privilege level of the requestor process. When the requested amount is greater than the operating system's amount of memory that can be used to pin memory, the operating system fails the request. However, when the operating can satisfy the request from processes having a lower privilege level relative to the requestor process, memory is unpinned from one or more of these processes.

Abstract: A storage device features a processor and a random number generation which are communicatively coupled to a memory.

Abstract: Methods, systems, and computer program products for executing a protected function are provided. A computer-implemented method may include storing a first virtual machine function instruction as the last instruction on the first trampoline page that is executable to configure access privileges according to a trampoline view, storing a page table setup instruction on the second trampoline page, and storing a second virtual machine function instruction as a last instruction on the second trampoline page that is executable to configure access privileges according to a protected view.

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

Abstract: An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device has an output. Furthermore, a housing with a plurality of assignable external pins and a protected pin ownership logic for each assignable external pin is provided and configured to be programmable to assign an output function of an associated assignable external pin to only one of the plurality of processor cores.

Abstract: Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation.

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.

Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.

Abstract: Systems and methods described herein facilitate configuration changes to an NIC teaming device while enabling multiple I/O threads continue to run through the NIC teaming device concurrently without interruption. At a given time, multiple configurations of the NIC teaming device, e.g., one for a current configuration of the NIC teaming device and one for a new configuration of the NIC teaming device, can co-exist. For the duration of one iteration, the current configuration of the NIC teaming device used by a specific I/O thread does not change and the new configuration of the NIC teaming device is not adopted by the I/O thread until the start of the next iteration. Once all of the I/O threads finish their current iteration, the configuration of the NIC teaming device is flipped from the current configuration to the new configuration and the current configuration is deleted.

Abstract: A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

Abstract: Memory circuit configuration schemes on multi-drop buses are disclosed. In aspects disclosed herein, an on-die mapping logic is provided in a memory circuit. A memory controller communicates with the on-die mapping logic over a multi-drop bus. The on-die mapping logic is configured to receive a predetermined on-die termination (ODT) value from the memory controller prior to being accessed. In response to receiving the predetermined ODT value, the memory circuit sets on-die termination to the predetermined ODT value and instructs an on-die reference signal generator to generate a predetermined reference signal associated with the predetermined ODT value. The predetermined reference signal provides an optimal reference voltage for implementing a desired equalization setting at the memory circuit, thus aiding in preserving signal integrity. Such improved signal integrity reduces errors in accessing the memory circuit, thus leading to improved efficiency and data throughput on the multi-drop bus.

Abstract: Apparatuses and techniques for dynamic credit control in the context of a multi-traffic class communication system are described. Dynamic credit control is provided through the use of central-controlled, traffic class receiver buffers for multiple traffic classes. The size of the traffic class receiver buffers can be modified on-the-fly, during operation of the system. This provides a high degree of flexibility, particularly in the context of heavy traffic class packet traffic which, in turn, greatly facilitates operation of today's advanced applications.

Abstract: In a case where a changeover request indicating to change over setting of an end point is received from an external apparatus, an information processing apparatus decides whether or not data is being transferred from the end point to a memory of the information processing apparatus. Then, in a case where it is decided that the data is being transferred from the end point to the memory, the information processing apparatus does not change over the setting of the end point.

Abstract: This invention relates to a method to obtain an image from the perspective of a pacifier user. The method involves the steps of: providing a digital camera mounted on pacifier apparatus 90 and capturing the image. This can be accomplished in one embodiment by providing an apparatus made of a perpendicular mounting member 30 or linear mounting member 35 that has a plurality of grooved prongs shaped to secure the ring 20 of a pacifier; and a digital camera 40 attached to the perpendicular mounting member 30.

Abstract: A mechanism for PCIe cable topology discovery in a Rack Scale Architecture (RSA) and associated methods, apparatus, and systems. Pooled system drawers installed in rack are interconnected via multiple PCIe cables coupled to PCIe ports on the pooled system drawers. The PCIe ports are associated with host ports connections between server nodes and host ports in respective pooled system drawers are automatically detected, with corresponding PCIe connection information being automatically generated and aggregated to determine the PCIe cable topology for the rack. In one aspect, PCIe devices are emulated for each host port in a pooled storage drawer including pooled PCIe storage devices. Server nodes in a pooled compute drawer send PCIe configuration messages over the PCIe cables, with returned reply messages generated by the emulated PCIe devices identifying the host ports. Information pertaining to the host ports, pooled system drawers, and server nodes is used to determine the PCIe cable topology.

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

Abstract: An electronic device includes a display unit and a processor. The processor performs an input process to receive an input of a first mathematical expression including a left side member, an equality sign or inequality sign, and a right side member expressed in this order; a first mathematical expression display process to display, on the display unit, the input first mathematical expression; a verification process to verify whether the input first mathematical expression is true or false; and a second mathematical expression display process to display, on the display unit, the right side member of the verified first mathematical expression as a left side member of a second mathematical expression to be newly verified, if the first mathematical expression is determined to be true as a result of verification by the verification process.

Abstract: A write queue, for queuing a packet in a traffic manager coupled to a memory device, is selected from among a preemptable write queue configured to queue packets that are candidates for being retrieved from the traffic manager before the packets are written to the memory device and a non-preemptable write queue configured to queue packets that are not candidates for being retrieved from the traffic manager before the packets are written to the memory device. The packet is written to the selected write queue. A read request is generated for retrieving the packet from the memory device, and it is determined whether the packet is queued in the preemptable write queue. If the packet is queued in the preemptable write queue, the packet is extracted from the preemptable write queue for retrieving the packet from the traffic manager before the packet is written to the memory device.

Abstract: Systems, methods, and devices for providing hour-of-service (“HOS”) calculations via a web based host server instead of on an onboard mobile device. In the various embodiments, an onboard vehicle recording device and driver-carried mobile devices may operate independently. The onboard vehicle recording device and driver-carried mobile device(s) may exchange information independently with a host server rather than exchanging information together onboard the vehicle.

Abstract: One embodiment of the present invention provides a computing system. The computing system includes a processor and a computer-readable storage medium. The computer-readable storage medium stores instructions which when executed by the processor cause the processor to perform a method. The method comprises obtaining from a first data structure one or more pointers to corresponding elements in a second data structure. A respective vertex of a graph corresponds to an element in the first data structure and the graph supports multiple edge types between respective vertex pairs. The method further comprises obtaining from the second data structure a respective edge type associated with a respective vertex and a respective successor vertex of the edge type and enumerating a respective successor vertex of an edge type of a vertex from the second data structure based on a pointer in an element in the first data structure associated with the vertex.

Abstract: A method for locating a pulse in detector output data, comprising fitting one or more functions to the detector output data; and determining a location and an amplitude of a peak of said pulse from said one or more functions. The one or more functions may be are a function of time.

Abstract: In a method for dynamically highlighting repetitive text in electronic documents, obtaining one or more user preferences related to a user reading an electronic document. The method further includes determining whether the electronic document contains one or more repetitive text associations, wherein a repetitive text association is data that provides one or more indications of repetitive text segments interspersed within a document. In response to determining that the electronic document contains one or more repetitive text associations, the method further includes identifying one or more repetitive text segments in the electronic document corresponding to the one or more repetitive text associations and determining a time duration expended by the user reading an instance of the identified one or more repetitive text segments within the electronic document.

Abstract: The technology described relates to animated transitions between consecutive sets of search engine results.

Abstract: Techniques are described for promoting content items in a page to load in a different order than the order in which they were initially designated to load in the page source. A page may include critical content items designated to load earlier than non-critical content items. In instances where there is a delay due to latency in generating or retrieving the critical content items, one or more non-critical content items may be promoted to load earlier than initially designated. Promotion may include incorporating metadata based priority indicators, such as attributes, into the tags for content items to suggest an order in which the content items may be requested by a user device. By promoting non-critical content items to load during the period in which the loading of the page may otherwise be stalled, overall page load times may be reduced.

Abstract: An intermediary system operates as an intermediary between content servers and user devices, and provides services for improving page load times as seen by end users. One such service involves converting a retrieved content page (e.g., web page) into a number of encoded layers that can be decoded and rendered by the user device. The intermediary system determines a suitable encoding technique for each of the layers. The intermediary system sends the encoded layers to a browser component running on the user device for rendering by the GPU.

Abstract: A method of creating a dynamically adaptable tutorial, comprising: selecting at least one web document having a plurality of separate objects; providing by a user a plurality of descriptive elements; separately associating between each of said plurality of descriptive elements and each of said plurality of separate objects according to a user input; associating a plurality of calling scripts with said plurality of separate objects; making said at least web document available so that a loading thereof by a browser includes triggering said plurality of calling scripts for a retrieval of each of said plurality of descriptive elements; wherein said web document enables a browsing user who uses said browser to initiate a tutorial session during which at least a group of said plurality of descriptive elements are sequentially presented in accordance with a current layout of a respective group from said plurality of separate objects.

Abstract: The present application discloses a network media information display system, method, apparatus and server.