Patents Issued in July 3, 2018
  • Patent number: 10013314
    Abstract: A media agent is configured to perform substantially autonomously to initiate, continue, and manage information management operations such as a backup job of a certain client's primary data, manage the operations, and generate and store resultant system-level metadata from the operations, etc. The media agent is configured to do this even when out of communication with the storage manager that manages the information management system. When communications are restored, the media agent reports the relevant metadata to the storage manager. The storage manager comprises corresponding enhancements, including specialized logic for identifying the media agent as an intelligent media agent capable of some autonomous functionality, for transmitting management parameters thereto, and for seamlessly integrating the received metadata into the storage manager's associated management infrastructure such as a management database.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 3, 2018
    Assignee: COMMVAULT SYSTEMS, INC.
    Inventor: Michael Frank Klose
  • Patent number: 10013315
    Abstract: Embodiments described herein relate to an improved technique for maintaining a consistent state during data migration operations in an active database system. Data can be copied from database table(s) of the active database system into a corresponding database table(s) in the shadow system. Snapshots of the active system can be taken at a specified point in time and used to establish a point of consistency. Later, the snapshot data can be compared with the data in the shadow database system. If the data matches, then the active and shadow database systems are at a consistent state and the data migration process completes. If the data does not match, embodiments are configured to restore the consistent state at the specified point in time by copying the snapshot data into the shadow database table(s).
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: July 3, 2018
    Assignee: SAP SE
    Inventor: Lars-Eric Biewald
  • Patent number: 10013316
    Abstract: Provided are a computer program product, system, and method for replicating a source data set to a target data store. A point-in-time copy of the source data set is generated having a data structure identifying the data in the source data set as of a point-in-time. A restore operation is initiated to copy the source data set represented by the point-in-time copy to a restored copy of the source data set consistent with the source data set. The source data set records are transferred from the restored copy to the target data store in the target storage.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Cadarette, Robert S. Gensler, Jr., Joseph L. Kidd, Robert D. Love, Terri A. Menendez, Austin J. Willoughby
  • Patent number: 10013317
    Abstract: A system and method for performing search optimization operations. In order to optimize lookups for received data requests, a storage controller attempts to collapse the medium graph, thus reducing the number of mediums in which the storage controller must look to find a given block. One technique for collapsing the medium graph involves promoting individual mappings from a lower-level medium to a higher-level medium. Another technique for collapsing the medium graph involves pushing medium range pointers higher up in the medium mapping table to reduce the number of mediums that must be searched.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 3, 2018
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Ethan Miller, John Hayes, Cary Sandvig, Christopher Golden, Jianting Cao
  • Patent number: 10013318
    Abstract: According to an example, a master node is to divide an event field in events into partitions including ordered contiguous blocks of values for the event field. Each partition may be assigned to a pair of cluster nodes. A partition map is determined from the partitions and may identify for each partition, the block of the event field values for the partition, a primary cluster node, and a failover cluster node for the primary cluster node.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: July 3, 2018
    Assignee: EntIT Software LLC
    Inventors: Robert Block, Anurag Singla
  • Patent number: 10013319
    Abstract: A server board includes first and second devices. A first service processor of the first device operates as a master baseboard management controller of the server board, and monitors a communication channel for alive messages from a plurality service processors. A second service processor operates as a secondary baseboard management controller, and sets a second timer to a first value. In response to a determination that the second timer has expired based on a first value: the second service processor to start a switchover process, and to set the second timer to a second value based on an alive message period. In response to a primary alive message not being received from the first service processor prior to the second timer expiring based on the second value, the second service processor to reset first service processor and to operate as the master baseboard management controller.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: Avishay Moskowiz, Amitay Beler, Ira Kalman
  • Patent number: 10013320
    Abstract: Aspects of the present disclosure involve systems and methods for removes and/or adding log and/or cache devices to storage pools of a storage appliance. Users, via a graphical-user interface, identify the log and/or cache devices for removal or addition. Subsequently, the log and/or cache devices are moved, according to a data profile corresponding to the devices, from a first storage appliance to a second storage appliance.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 3, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Apoorva Vennavaram Gade, Juan Carlos Zuluaga
  • Patent number: 10013321
    Abstract: A method of minimizing rebuild times within a large-scale data storage system, such as a RAID array by: maintaining a spare disk for a plurality of disks within a disk array; monitoring the plurality of disks for occurrence of one or more pre-failure indicators; maintaining, for each disk, a count of the occurrences of the pre-failure indicators; comparing the count for each disk to a defined threshold value; and copying the first disk and mirroring write operations to the first disk to the spare disk if the count for the first disk exceeds the threshold. The method switches the copying to the spare disk from the first disk to a second disk if the count for the second disk exceeds the count for the first disk. In this manner, certain predictive information can be used to use the spare disk to reduce RAID rebuild times to near instantaneous periods.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: July 3, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Richard M Stern
  • Patent number: 10013322
    Abstract: A storage controller stores, for each of a plurality of storage devices, a usable capacity, which is a capacity usable by the storage controller in a logical storage area, configures a first RAID group using a first storage device group among the plurality of storage devices, and allocates, on the basis of a request from a host computer, one of a plurality of pages of the logical storage area in the first RAID group to a virtual volume. The storage controller reduces, when receiving first failure information indicating a failure in a first storage device in the first storage device group from the first storage device, a usable capacity of the first storage device on the basis of the first failure information.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: July 3, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Go Uehara, Shigeo Homma, Koji Sonoda
  • Patent number: 10013323
    Abstract: A technique is directed to providing resiliency to a redundant array of independent disk (RAID) group which includes multiple storage devices. The technique involves operating the RAID group in a normal state in which each storage device is (i) initially online to perform write and read operations and (ii) configured to go offline in response to a respective media error count for that storage device reaching an initial take-offline threshold. The technique further involves receiving a notification that a storage device of the RAID group has encountered a particular error situation. The technique further involves transitioning, in response to the notification, the RAID group to a high resiliency state in which each storage device that is operable is (i) still online to perform write and read operations and (ii) configured to stay online even when the respective media error count for that storage device reaches the initial take-offline threshold.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 3, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Peter Puhov, Ronald D. Proulx, Wayne E. Garrett, Ashok Tamilarasan, Eric Petsching
  • Patent number: 10013324
    Abstract: In one general embodiment, a computer-implemented method includes using a supplemental data storage volume at a secondary location to track a first set of data updates to a primary data storage volume at a primary location in response to a failure event at the primary location. A second set of tracked data updates, which are updates to the primary data storage volume stored in a secondary data storage volume at the secondary location, are retrieved. The second set of tracked data updates is merged into the first set of tracked data updates in the supplemental data storage volume. The merged data updates are transitioned from the supplemental data storage volume at the secondary location to the primary data storage volume at the primary location. The secondary data storage volume is used to track further data updates to the primary data storage volume made at the primary location.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: David R. Blea, Theresa M. Brown, Gregory E. McBride, Carol S. Mellgren, Warren K. Stanley, Matthew J. Ward
  • Patent number: 10013325
    Abstract: Technique provides resiliency to RAID group including storage devices. Technique involves operating RAID group in normal state in which each storage device is initially online to perform write and read operations and configured to go offline in response to a media error count for that storage device reaching an end-of-life threshold and other storage devices in RAID group being healthy. Technique involves receiving a notification that a storage device of RAID group has encountered an error situation. Technique involves determining whether other storage devices of RAID group are healthy. Technique involves transitioning, in response to receiving notification and determining that other storage devices are healthy, RAID group from normal state to high resiliency degraded state in which the storage device is taken offline and the other storage devices are configured to remain online for facilitating the reconstruction of data associated with the storage device.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 3, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Wayne E. Garrett, Jr., Ronald D. Proulx, Ashok Tamilarasan, Eric Petsching
  • Patent number: 10013326
    Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Polychronis Xekalakis, Georgios Tournavitis, Kyriakos A. Stavrou, Demos Pavlou, Daniel Ortega, Alejandro Martinez Vicente, Pedro Marcuello, Grigorios Magklis, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos Kotselidis, Fernando Latorre, Marc Lupon, Carlos Madriles
  • Patent number: 10013327
    Abstract: The present invention provides a monitor, especially a wake up monitor, for monitoring an integrated circuit, the monitor comprising a first monitoring unit configured to monitor at least one input of the integrated circuit, a second monitoring unit configured to monitor at least one output of the integrated circuit, a measurement unit configured to measure the time elapsed between an event on the at least one input and a reaction to the event on the at least one output and configured to output an alert signal if the elapsed time exceeds a predetermined first time limit. The present invention furthermore discloses an integrated circuit and a method for monitoring an integrated circuit.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: July 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: Alistair Paul Roberston, Andrew Edward Birnie, Thomas Henry Luedeke
  • Patent number: 10013328
    Abstract: A method is provided for indicating to a user that a sink device is incorrectly connected to a High Definition Multimedia Interface (HDMI) In port. In accordance with the method, a proxy voltage is applied from an HDMI In port over an HDMI cable. The proxy voltage is sufficient to cause a hot plug event to occur. A hot plug event condition is detected at the HDMI In port from a device that is connected to the HDMI In port via the HDMI cable. Extended Display Identification Data (EDID) is read from the device at the HDMI In port over the HDMI cable. In response to receipt of the EDID, a determination is made that the device is a sink device and an error message is generated in response to the determination.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 3, 2018
    Assignee: ARRIS Enterprises LLC
    Inventors: Charles Hardt, John P. Eck
  • Patent number: 10013329
    Abstract: Method, computer program product, and system for dynamic tracing, including monitoring a log file, wherein the log file comprises events, wherein an event comprises an event code and an event time stamp, receiving a ranking and rating table (“table”), wherein the table comprises one or more error codes and a ranking for each of the one or more error codes, matching the event code with an error code of the one or more error codes, calculating a rating for the error code, comparing the calculated rating to a rating threshold, enabling an information capture level based on the rating threshold of the calculated rating, in response to enabling the information capture level, copying events from the log file into an abbreviated log file, wherein the copied events include the error code for the calculated rating, creating an alert indicating a changed information capture level, and resetting the dynamic tracing.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Javed Iqbal Abdul, Jose Peter
  • Patent number: 10013330
    Abstract: Disclosed are various embodiments for automatically testing and verifying applications. A user input profile is generated for an application by performing a static analysis on the application. Simulated user input for the application is generated based at least in part on the user input profile. Execution of the application is initiated in a computing device. The simulated user input is provided to the application executed in the computing device. It is verified whether the application meets performance criteria in the computing device.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: July 3, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Calvin Y. Kuo, Zahur A. Peracha
  • Patent number: 10013331
    Abstract: Provided are techniques for invoking with a processor executing on a computer a source code parser to obtain source information that includes a first location of an Application Programming Interface (API) call and parameters of the API call in source code of a client application, where the parameters the API call do not include query text for a query that is to be used to access a database; examining a stack trace to determine a second location of the API call in the stack trace; and deriving the query of the API call and a third location of the query in the source code by identifying the query in the stack trace at the location of the API call in the stack trace.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen A. Brodsky, Zeus O. Courtois, Tom W. Jacopi, Michael Y. Kwong, Tony K. Leung, Sonali Surange
  • Patent number: 10013332
    Abstract: Aspects of the subject disclosure are directed towards monitoring application performance during actual use, particularly mobile application performance. Described is instrumenting mobile application binaries to automatically identify a critical path in user transactions, including across asynchronous-call boundaries. Trace data is logged by the instrumented application to capture UI manipulations, thread execution, asynchronous calls and callbacks, UI updates and/or thread synchronization. The trace data is analyzed to assist developers in improving application performance.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 3, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Lenin Ravindranath Sivalingam, Jitendra D. Padhye, Sharad Agarwal, Ratul Mahajan, Ian Obermiller, Shahin Shayandeh
  • Patent number: 10013333
    Abstract: A scalable continuous integration (CI) system and/or method may be provided to manage and implement a plurality of code changes submitted in a code base. The scalable CI system and/or method may implement an automated failure analysis. In particular, a defect search technique, a machine learning technique, or both, may be implemented to identify failing change sets in a queue of change sets. The machine learning algorithm may first be applied to see if failing change sets may be identified, then the system may fall back to the defect search algorithm when the machine learning technique is not adequate. In the machine learning technique, the system may use an artificial neural network (ANN) to determine failure risks of change sets. The identified failing change sets may be removed from the queue.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 3, 2018
    Assignee: PayPal, Inc.
    Inventors: Zachary Paul Wood, Justin Vincent Montoya
  • Patent number: 10013334
    Abstract: In an approach to identifying program bugs, one or more computer processor detect a first crash in a try block. The one or more computer processors determine a catch block executed in response to the crash. The one or more computer processors collect a first set of environment information based on the catch block. The one or more computer processors create a first breakpoint where the first crash occurs. The one or more computer processors detect a second crash in the try block using a first pattern associated with the first crash based on the first set of environment information. The one or more computer processors collect a second set of environment information based on the catch block. The one or more computer processors create a second breakpoint where the second crash occurs.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: James E. Carey, Jim C. Chen, John M. Santosuosso
  • Patent number: 10013335
    Abstract: A program control flow trace is obtained from a processor trace module, which may be hardware based, and is used, in combination with debug information and information from dissassembly of basic blocks, to identify candidate store instruction(s) which produced a memory corruption. The candidate store instruction(s) and links to a software program may be used to further debug the memory corruption and/or to instrument the software program to identify basic block(s) which produced the memory corruption in future executions of the compiled software program and/or to track debugging of the software program.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventor: Andreas Kleen
  • Patent number: 10013336
    Abstract: A testing and extract, transform and load (TETL) system is operable to interface with test platforms testing hardware or software components of information technology systems. The TETL system can execute extract, transform and load operations to load test data into a data warehouse and facilitates evaluating the test data across projects, entities and domains.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: July 3, 2018
    Assignee: ACCENTURE GLOBAL SERVICES LIMITED
    Inventor: Yashpal Shah
  • Patent number: 10013337
    Abstract: A set of features is received. A feature from the set of features includes a feature setting. The feature setting is adjusted based on a user input. A source code portion that corresponds to the adjusted feature setting is transported to a test system. The source code portion is implemented at the test system and evaluated based on the adjusted feature setting. Log data from the test system is analyzed in a feature evaluation UI. The evaluated feature with the implemented source code portion is submitted for deployment from the test system to a production system.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 3, 2018
    Assignee: SAP SE
    Inventors: Peter Eberlein, Volker Driesen
  • Patent number: 10013338
    Abstract: Described are techniques for testing an application. A test script including one or more instructions is received to test an application. A user interaction with a user interface of the application is emulated. Emulating includes executing a first portion of instructions in the test script. An output is received including information displayed using the user interface in response to the user interaction. Verification processing is performed for the output. The verification processing includes executing a second portion of instructions in the test script. A first instruction in the test script references a user interface data element without specifying a complete path for the user interface data element.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 3, 2018
    Assignee: WATERS TECHNOLOGIES CORPORATION
    Inventors: Steven Leclair, Enrique Ramirez, Dana Yurach, Laura Turner, Allen Caswell, Mark Robinson
  • Patent number: 10013339
    Abstract: A system and computer-implemented method for automating end-to end testing is provided. The system comprises a connection settings module to receive information for connecting with one or more external systems. The system further comprises a test setup module to create test workflows, wherein creating the test workflows comprise selecting one or more pre-stored source files and corresponding one or more pre-stored target files and mapping input and output of each of the one or more selected pre-stored source files with the corresponding one or more selected pre-stored target files for testing additional source files associated with the one or more external systems. Furthermore, the system comprises a workflow execution module to connect with the one or more external systems using the received information to retrieve the additional source files and execute the created test workflows corresponding to the retrieved one or more additional source files.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 3, 2018
    Assignee: COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD.
    Inventor: Suganthakumar Athinathan
  • Patent number: 10013340
    Abstract: Technology is described for selecting parameter combinations corresponding to virtual instance configurations to be tested in a virtual computing environment and for performing tests in a plurality of parallel test pipelines. Throttling constraints can be applied so that resources used by the test pipelines in the testing process do not exceed predefined limits.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: July 3, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Kevin Lester Quadros, Sivaprasad Venkata Padisetty
  • Patent number: 10013341
    Abstract: A semiconductor memory device includes a first memory area in the semiconductor memory device, and a second memory area in the semiconductor memory device. The second memory area is accessed independently of the first memory area based on a usage selecting signal. The first and second memory areas share command and address lines, and perform a rank interleaving operation based on the usage selecting signal.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Oh-Seong Kwon, Jinhyun Kim, Won-Hyung Song, Jihyun Choi
  • Patent number: 10013342
    Abstract: A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 3, 2018
    Assignees: MEMRAY CORPORATION, YONSEI UNIVERSITY, UNIVERSITY—INDUSTRY FOUNDATION (UIF)
    Inventor: Myoungsoo Jung
  • Patent number: 10013343
    Abstract: A method for performing a refresh of a first memory area of a non-volatile memory unit includes overwriting at least one additional memory area of the non-volatile memory unit with a memory content from the first memory area, adding a reference to the at least one additional memory area to a memory address area corresponding to the memory content and removing a reference to the first memory area from the memory address area corresponding to the memory content, overwriting the first memory area with the memory content from the at least one additional memory area, and subsequently replacing the reference in the memory address area with the reference to the first memory area.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: July 3, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Axel Aue
  • Patent number: 10013344
    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an input/output (I/O) operation directed to a file system. The controller may perform a read-fill based on a hint value when there is a read miss in the cache. The hint value may be based on the application access pattern. The hint value may be passed to a caching layer with a corresponding I/O.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: July 3, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Luca Bert, Anant Baderdinni, Saugata Das Purkayastha, Philip K. Wong
  • Patent number: 10013345
    Abstract: A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains a count of time slots over a period of time. The period of time corresponds to an amount of time between periodic power peaks of a memory operation. For each time slot, the storage module determines whether to commence a memory operation on one or more of the plurality of memory dies based on whether a power peak generated in the time slot by the memory operation would exceed a power threshold allowed for the time slot. Other embodiments are provided.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 3, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Erez, Cynthia Hsu
  • Patent number: 10013346
    Abstract: A journaling approach is used to distribute data of different sizes between areas of a segment's log on a physical NAND flash erase block. The Main area contains large, contiguous extents of data, and the Journal area contains logical blocks of small data. An Updates area also contains updates that are pending. One disclosed embodiment includes storing a first file fragment associated with a file in a journal area of a log, where a size of the file fragment is less than a physical NAND flash page size limit, receiving a second file fragment associated with the file, combining the first file fragment and the second file fragment when a combined size of the fragments is equal to the physical NAND flash page size limit, storing the combined fragments in a main area of a second log, receiving an update associated with the combined fragments, and storing the update in an updates area of a third log.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: July 3, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Anatolyevich Dubeyko, Cyril Guyot
  • Patent number: 10013347
    Abstract: A transaction descriptor associated with a vertical chain of row versions is received. The vertical chain of row versions is traversed. The vertical chain is part of a grid structure formed by a number of vertical chains intersected with a number of horizontal chains. A link to a current row version is terminated. A link from the current row version to an older row version in a horizontal chain is locally stored and terminated. The older row version is set as ready for garbage collection. The current row version is set as ready for garbage collection. A link from the current row version to a next row version in the horizontal chain is locally stored and terminated. The next row version is appointed as current.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 3, 2018
    Assignee: SYBASE, INC.
    Inventors: Rahul Mittal, Amit Pathak, Jay Sudrik, Simhachala Sasikanth Gottapu
  • Patent number: 10013348
    Abstract: A liveness-based memory allocation module operating so that a program thread invoking the memory allocation module is provided with an allocation of memory including a reserve of free heap slots beyond the immediate requirements of the invoking thread. The module receives a parameter representing a thread execution window from an invoking thread; calculates a liveness metric based upon the parameter; calculates a reserve of memory to be passed to the invoking thread based upon the parameter; returns a block of memory corresponding to the calculated reserve of memory. Equations, algorithms, and sampling strategies for calculating liveness metrics are disclosed, as well as a method for adaptive control of the module to achieve a balance between memory efficiency and potential contention as specified by a single control parameter.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 3, 2018
    Assignee: UNIVERSITY OF ROCHESTER
    Inventors: Pengcheng Li, Chen Ding
  • Patent number: 10013349
    Abstract: A method for operating a memory controller is provided. The method includes generating a pseudo random number by using a seed included in a stored seed group corresponding to a page to be currently programmed, wherein the stored seed group is stored among a plurality of seed groups. Data to be programmed into the current page is randomizing by using the pseudo random number and the memory controller outputs the randomized data. A solid state drive (SSD) or other memory storage device such as a memory card includes the memory controller and includes a read only memory (ROM) storing the plurality of seed groups. The memory controller includes a micro-processor and a read only memory (ROM) storing executable code for causing the micro-processor to access the plurality of stored seed groups and to select a seed therefrom corresponding to a page to be currently programmed.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kui-Yon Mun, Hwa Seok Oh
  • Patent number: 10013350
    Abstract: A data storage device includes a plurality of logical regions that form n number of logical zones, each including k number of logical regions, wherein the plurality of logical regions are grouped into k number of logical region groups based on their offset values; and a processor suitable for, when receiving a write request for a target logical region, increasing a first access count stored in a first entry of a first table, corresponding to a logical zone including the target logical region, and increasing a second access count stored in a second entry of a second table, corresponding to a logical region group including the target logical region.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 3, 2018
    Assignee: SK Hynix Inc.
    Inventor: Se Hyun Kim
  • Patent number: 10013351
    Abstract: A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The higher level cache is shared with two or more processors. A processor may have a corresponding accelerator that performs operations on behalf of the processor. Transaction indicators are set in the higher level cache corresponding to the cache lines being accessed. The transaction aborts if a memory conflict with the transaction's cache lines from another transaction is detected, and the corresponding cache lines are invalidated. For a successfully completing transaction, the corresponding cache lines are committed and the data from store operations is stored.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum
  • Patent number: 10013352
    Abstract: Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Sreenivas Subramoney, Jayesh Gaur, Mukesh Agrawal, Mainak Chaudhuri
  • Patent number: 10013353
    Abstract: Adaptive optimization of second level cache is disclosed. In an example embodiment, a system includes a database server and an enterprise application server, which includes an enterprise application execution module, a first level cache, a second level cache, and a cache optimizer. The enterprise application server iteratively executes an executable module, which causes receiving entity data from a database, with a plurality of different attributes, storing the entity data in a first level cache, and accessing an attribute in the entity data from the first level cache. The enterprise application server collects statistical data representing a quantity of accesses of attributes, determines an attribute to omit from a second level cache based on the statistical data, transfers a subset of the entity data from the first level cache, and stores, in the second level cache, the subset of the entity data with the at least one attribute omitted.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: July 3, 2018
    Assignee: Red Hat, Inc.
    Inventors: Pavel Slavicek, Rostislav Svoboda
  • Patent number: 10013354
    Abstract: A storage layer (SL) for a non-volatile storage device presents a logical address space of a non-volatile storage device to storage clients. Storage metadata assigns logical identifiers in the logical address space to physical storage locations on the non-volatile storage device. Data is stored on the non-volatile storage device in a sequential log-based format. Data on the non-volatile storage device comprises an event log of the storage operations performed on the non-volatile storage device. The SL presents an interface for requesting atomic storage operations. Previous versions of data overwritten by the atomic storage device are maintained until the atomic storage operation is successfully completed. Data pertaining to a failed atomic storage operation may be identified using a persistent metadata flag stored with the data on the non-volatile storage device. Data pertaining to failed or incomplete atomic storage requests may be invalidated and removed from the non-volatile storage device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 3, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: David Flynn, Stephan Uphoff, Xiangyong Ouyang, David Nellans, Robert Wipfel
  • Patent number: 10013355
    Abstract: Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by a plurality of processing elements which operate on the set of many-core hardware processors. The stream of tuples to be processed by the plurality of processing elements which operate on the set of many-core hardware processors may be received. A tuple-processing hardware-route on the set of many-core hardware processors may be determined based on a cache factor associated with the set of many-core hardware processors. The stream of tuples may be routed based on the tuple-processing hardware-route on the set of many-core hardware processors. The stream of tuples may be processed by the plurality of processing elements which operate on the set of many-core hardware processors.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, Cory J. Kleinheksel, David M. Koster, Jason A. Nikolai
  • Patent number: 10013356
    Abstract: The disclosed embodiments relate to a system that generates prefetches for a stream of data accesses with multiple strides. During operation, while a processor is generating the stream of data accesses, the system examines a sequence of strides associated with the stream of data accesses. Next, upon detecting a pattern having a single constant stride in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the single constant stride. Similarly, upon detecting a recurring pattern having two or more different strides in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the recurring pattern having two or more different strides.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 3, 2018
    Assignee: ORACLE INTERNAIONAL CORPORATION
    Inventor: Yuan C. Chou
  • Patent number: 10013357
    Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 3, 2018
    Assignee: Cavium, Inc.
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Srilatha Manne
  • Patent number: 10013358
    Abstract: A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource is allocated; and a cache state management mechanism that manages a cache state of the virtual computer. The virtualization mechanism provides a first virtual computer and a second virtual computer. The cache state management mechanism manages the cache state of each of the first virtual computer and the second virtual computer. When the cache state management mechanism detects transition of the cache state in a state where a memory area allocated to a cache of the first virtual computer and a memory area allocated to a cache of the second virtual computer include duplicated areas storing same data, the virtualization mechanism releases the duplicated area in one of the first virtual computer and the second virtual computer.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: July 3, 2018
    Assignee: HITACHI, LTD.
    Inventors: Sachie Tajima, Tadashi Takeuchi
  • Patent number: 10013359
    Abstract: A redundant disk array method includes allocating identically sized logical blocks of storage units together to form a stripe on each of several data storage devices, at least two of the logical blocks in the stripe being located on different data storage devices, generating a lookup table representing a mapping between a logical location of each logical block in the stripe and a physical location of the respective logical block on the corresponding data storage device, and writing data to the physical locations of each logical block in the stripe, the physical locations being obtained from the lookup table. In some cases, at least two of the data storage devices are heterogeneous, and at least two of the data storage devices have a different total number of logical blocks.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 3, 2018
    Assignee: University of New Hampshire
    Inventors: András Krisztián Fekete, Elizabeth Varki
  • Patent number: 10013360
    Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. The managing includes: at the second access level, translating from virtual addresses to intermediate physical; at the second access level, determining reuse information for ranges of virtual addresses based on estimated reuse of data stored within a virtual address space; at the first access level, translating from the intermediate physical addresses to physical addresses; at the first access level, determining reuse information for ranges of intermediate physical addresses based on estimated reuse of data stored within an intermediate physical address space; and processing reuse information determined at different access levels to store cache lines in selected portions of a first cache.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: July 3, 2018
    Assignee: Cavium, Inc.
    Inventor: Shubhendu Sekhar Mukherjee
  • Patent number: 10013361
    Abstract: A method of managing data in a cache upon a cache write operation includes determining a number of non-contiguously written sectors on a track in the cache and comparing the number with a threshold number. If the number exceeds the threshold number, a full background stage operation is issued to fill the non-contiguously written sectors with unmodified data from a storage medium and the full track is then destaged. A corresponding system includes a cache manager module operating on the storage subsystem. Upon a determination that a cache write operation on a track has taken place, the cache manager module determines a number of non-contiguously written sectors on the track, compares the number with a predetermined threshold number, issues a background stage operation to fill the non-contiguously written sectors with unmodified data from a storage medium if the number exceeds the threshold number, and then destages the full track.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Mannenbach, Karl A. Nielsen
  • Patent number: 10013362
    Abstract: Some embodiments modify caching server operation to evict cached content based on a deterministic and multifactor modeling of the cached content. The modeling produces eviction scores for the cached items. The eviction scores are derived from two or more factors of age, size, cost, and content type. The eviction scores determine what content is to be evicted based on the two or more factors included in the eviction score derivation. The eviction scores modify caching server eviction operation for specific traffic or content patterns. The eviction scores further modify caching server eviction operation for granular control over an item's lifetime on cache.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 3, 2018
    Assignee: Verizon Digital Media Services Inc.
    Inventors: Harkeerat Bedi, Amir Reza Khakpour, Robert J. Peters
  • Patent number: 10013363
    Abstract: A system may encrypt the contents of a memory using an encryption key that is generated based on an entropy-based key derivation function. The system may generate a random value as a key split associated with an instance of writing data to memory. The system may generate an encryption key for encrypting the data using an entropy-based key derivation function based at least in part on the key split. The system may encrypt the data using the encryption key. The system may store the encrypted data and the key split to the memory.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 3, 2018
    Assignee: Honeywell International Inc.
    Inventors: James L. Tucker, Thomas Cordella, John D. Profumo