Abstract: The present embodiments relate to an address generator circuit for addressing a storage circuit. The address generator circuit may generate address signals for read and write access operations at the storage circuit. The write access operation may store a two-dimensional array in the storage circuit and the read access operation may retrieve a transpose of the two-dimensional array from the storage circuit. The address generator circuit may include a status flag generation circuit that generates status flag signals, a modulo adder circuit that receives first and second signals and computes a modulo adder output signal, and an address processing circuit. The address processing circuit may receive the modulo adder output signal from the modulo adder circuit and the plurality of status flag signals from the status flag generation circuit and provide the first and second signals to the modulo adder circuit.

Abstract: A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node indicator whose value determines the side of the tree structure to which a next memory element replacement operation is directed, and circuitry to cause, responsive to a miss in the associative memory while the decision node indicator points to the minority side of the tree structure, the decision node indicator to point a majority side of the tree structure, and to determine, responsive to a miss while the decision node indicator points to the majority side of the tree structure, whether or not to cause the decision node indicator to point to the minority side of the tree structure, the determination being dependent on a current replacement weight value. The replacement weight value may be counter-based or a probabilistic weight value.

Abstract: A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Abstract: Data can be stored in a multi-level cache hierarchy memory system by, for example, storing valid data associated with a cacheline in a primary location in a first cache memory location. The first cache memory also stores location information about an alternative location in a second cache memory associated with the cacheline. Space is allocated in the alternative location of the second cache memory to store data associated with the cacheline.

Abstract: A data storage device includes a controller, a non-volatile memory, and a buffer accessible to the controller. The buffer is configured to store data retrieved from the non-volatile memory to be accessible to a host device in response to receiving from the host device one or more requests for read access to the non-volatile memory while the data storage device is operatively coupled to the host device. The controller is configured to read an indicator of cached data in response to receiving a request for read access to the non-volatile memory. The request includes a data identifier. In response to the indicator of cached data not indicating that data corresponding to the data identifier is in the buffer, the controller is configured to retrieve data corresponding to the data identifier as well as additional data from the non-volatile memory and to write the data corresponding to the data identifier and the additional data to the buffer.

Abstract: A computing system includes: an instruction dispatch module module configured to receive a program instruction; and an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

Abstract: An arithmetic processing apparatus includes a prefetch unit configured to send a prefetch request to a subordinate cache memory for prefetching data of a main storage device into a primary cache memory. The arithmetic processing apparatus further includes a count unit configured to count a hit count of how many times it is detected that prefetch request target data is retained in the subordinate cache memory when executing a response process to respond to the prefetch request sent from the prefetch unit. The arithmetic processing apparatus yet further includes an inhibition unit configured to inhibit the prefetch unit from sending the prefetch request when the counted hit count reaches a threshold value.

Abstract: In-memory caching can include providing, in a data node, a pinned memory space for caching data in a distributed file system. The data that is cached in the pinned memory space is prevented from being swapped out. A virtual address is assigned to the data. The virtual address is mapped to a memory address of the data in the pinned memory space for accessing the data by an application.

Abstract: A memory system has a non-volatile memory used as a first cache memory to be accessed at a higher speed than a main memory, a first translation lookaside buffer that stores address conversion information indicating the conversion of a virtual address issued by a processor into a physical address, and a first control circuitry that stores the address conversion information stored in the first translation lookaside buffer in the non-volatile memory during a power off.

Abstract: A method and system for fast file initialization is provided. An initialization request to create or extend a file is received. The initialization request comprises or identifies file template metadata. A set of allocation units are allocated, the set of allocation units comprising at least one allocation unit for the file on a primary storage medium without initializing at least a portion of the file on the primary storage medium. The file template metadata is stored in a cache. The cache resides in at least one of volatile memory and persistent flash storage. A second request is received corresponding to a particular allocation unit of the set of allocation units. Particular file template metadata associated with the particular allocation unit is obtained. In response to the second request, at least a portion of a new allocation unit is generated.

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.

Abstract: Methods to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.

Abstract: A method and apparatus of a device that reads and writes a plurality of counters is described. In an exemplary embodiment, a device receives plurality labels that correspond to the plurality of counters. The plurality of counters is stored in a shared memory table in the shared memory of the device. In addition, a writer writes counter data for each of the plurality of counters to the shared memory table. For each of the plurality of labels, the device performs a lookup of that label for a memory reference to a corresponding counter that is one of the plurality of counters and retrieves the memory reference for the corresponding counter. The device further reads the counter data for plurality of counters using the plurality of memory references. The device additionally sends the counter data to the client.

Abstract: Herein are data storage devices to transfer a data object between memory regions during a storage operation. These data storage devices include a host controller configured to identify an object stored in a host region of a memory system for writing to a storage media controlled by a drive controller. The host controller initiates a memory transfer operation to transfer an object from the host region of the memory system to a drive region of the memory system. The host controller transfers a storage command to the drive controller to write the object to the storage media. The drive controller may be configured to transfer an object from the drive region to the host region when reading the object.

Abstract: A server, processing device and/or processor includes a processing core and a memory controller, operatively coupled to the processing core, to access data in an off-chip memory. A memory encryption engine (MEE) may be operatively coupled to the memory controller and the off-chip memory. The MEE may store non-MEE metadata bits within a modified version line corresponding to ones of a plurality of data lines stored in a protected region of the off-chip memory, compute an embedded message authentication code (eMAC) using the modified version line, and detect an attempt to modify one of the non-MEE metadata bits by using the eMAC within a MEE tree walk to authenticate access to the plurality of data lines. The non-MEE metadata bits may store coherence bits that track changes to a cache line in a remote socket, poison bits that track error containment within the data lines, and possibly other metadata bits.

Abstract: A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.

Abstract: A first component associated with an access controlled memory region receives a transaction request including a protocol header from a second component. The first component sends, to the second component, a negative acknowledgment in response to determining that the second component is not authorized to access the access controlled memory region, based on information in the protocol header.

Abstract: A single device that provides computing system-level functionality with non-volatile storage controller functionality. These functionalities can share the same electronics.

Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Abstract: It is made possible for a user to set whether to download data used by a program without waiting for the acceptance of a download permission or download the data in response to the acceptance of the download permission via a screen that allows for making the setting for a plurality of programs. An input/output control section (90) accepts, from the user, a setting as to whether to select an automatic download state or a manual download state via a screen that allows for doing so for a plurality of programs. If the setting of selecting the automatic download state is accepted, an item management section (96) downloads the data from a server without waiting for the acceptance of the download permission from the user when a predetermined condition is satisfied. If the setting of selecting the manual download state is accepted, the item management section (96) downloads the data from the server in response to the acceptance of the download permission from the user when the predetermined condition is satisfied.

Abstract: A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is operable to generate a sequence of pulses, each sequential pulse to be simultaneously received by the plurality of latches. A pulse is generated for each edge of a clock signal. A first latch of the plurality of latches is operable to pass on a first data sample while a first pulse is received by the first latch of the plurality of latches. A second latch of the plurality of latches is operable to pass on a second data sample towards the first latch of the plurality of latches while the first pulse is simultaneously received by the first and second latches of the plurality of latches.

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.

Abstract: According to one aspect, a module 11_1 includes a communication circuit 111 that performs data communication with an externally-provided control device 12 through a communication bus 13, and an interrupt signal generation circuit 113 that, when an interrupt instruction signal I1 output from the communication circuit 111 becomes an active state, generates an interrupt signal and outputs the generated interrupt signal to the communication bus 13, the interrupt signal being defined by using a bus potential undefined in a data communication standard.

Abstract: A direct memory access (DMA) control device including: a basic-function setting register used to perform DMA operation; and a scatter-gather setting register in which a value indicating that a task is executed through setting of a directly defined value for data to be written to the basic-function setting register without reading the data from a memory through a bus is set.

Abstract: A method for data storage includes, in a system that includes multiple servers, multiple multi-queue storage devices and at least one storage controller that communicate over a network, running, in a server among the servers, multiple data-path instances (DPs) that operate independently of one another and issue storage commands for execution in the multi-queue storage devices. The storage commands, issued by the multiple DPs running in the server, are multiplexed using an Input-Output Multiplexer (I/O MUX) process. The multiplexed storage commands are executed in the multi-queue storage devices.

Abstract: Boardroom table systems are provided that include a plurality of USB Type-C receptacles that can provide power and/or data transfer functionality to one or more devices attached thereto. Power transferred by the boardroom table system may be managed by USB Power Delivery, and may come from a source of wall power, or from a device coupled to one of the USB Type-C receptacles. Data transferred by the boardroom table system may include USB data, Ethernet data, video data, and/or any other type of data transmittable via a USB Type-C receptacle. In some embodiments, boardroom table systems also include presentation devices. In such embodiments, a device coupled to a USB Type-C receptacle could both transmit or receive power, exchange data, and transmit video to the presentation device via the same USB Type-C receptacle of the boardroom table system, thus eliminating the need for multiple sockets and cables.

Abstract: A universal input/output circuit for building automation is provided that may avoid issues related to capacitor soakage, thereby giving more accurate measurements of electric resistance. To mitigate capacitor soakage, the voltage between the input/output terminals is held constant. A programmable source drives a current through a resistor that connects to the input/output terminals. The circuit then measures a value of electrical resistance. The measurement yields a voltage signal which is transferred from the input of an analog-to-digital converter to the input of a digital-to-analog converter. A unity gain amplifier applies the output voltage of the digital-to-analog converter D/A to one of terminals. The circuit is configured such that the voltage signal at the output of the amplifier matches or substantially matches the voltage obtained from the resistance measurement.

Abstract: A switch monitoring system is provides information on sensor readings and contact closures over a one-wire network or a loop.

Abstract: In a server system and a management method thereof, the management method includes generating at least one virtual device for transmitting option read-only memory (ROM) data that is necessary for using a target physical device of at least one physical device, allocating the at least one virtual device to at least one host to correspond to the at least one host, and transmitting the option ROM data to a host corresponding to the at least one virtual device. The switch device may comprise a peripheral component interconnect express (PCIe) switch device.

Abstract: Including control data in a serial audio stream is presented herein. A device can include a clock component that is configured to send, via a clock pin of the device, a bit clock signal directed to a slave device. A frame component can send, via a frame pin of the device, a frame clock signal directed to the slave device. A control component can receive, via a data pin of the device during a first portion of a phase of a period of the frame clock signal, slave data from the slave device on a bit-by-bit basis based on the bit clock signal according to an integrated interchip sound (I2S) based protocol; and send, via the data pin during a second portion of the phase after the first portion, a set of control bits directed to the slave device on the bit-by-bit basis based on the bit clock signal.

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.

Abstract: In various embodiments, a hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy and/or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. Other embodiments are discussed.

Abstract: The application provides a network device, which includes: a main control board and a service board, where the main control board includes a processor and a switching chip, and the service board includes a physical layer component. The switching chip is connected to the physical layer component by using a system bus. The system bus consists of a SerDes link, and is configured to transmit service data and control information of a port of the physical layer component. The processor controls the port of the physical layer component by using the control information of the port of the physical layer component. The network device transmits the service data and the control information by using the system bus, so that the service board does not need to set a CPU processing the control information, thereby expanding an interface flexibly, and reducing device complexity and hardware costs.

Abstract: A USB controller with automatic clock generation comprising: an oscillating generator is used for generating an initial clock; a first phase locked loop is used for receiving the initial clock and outputting a controller operating clock having a first frequency; a controller is used for detecting at least one universal serial bus device and outputting an initial frame signal having a second frequency; a second phase lock loop is used for receiving the initial frame signal and outputting a sync frame signal having the first frequency; a third phase lock loop for receiving the sync frame signal and outputting a stabilizing frame signal having the first frequency; and a multiplexer is used for receiving the controller operating clock and the stabilizing frame signal and transmitting the controller operating clock or the stabilizing frame signals to the controller.

Abstract: Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

Abstract: A cache management system performs cache management in a Remote Direct Memory Access (RDMA) key value data store. The cache management system receives a request from at least one client configured to access a data item stored in a data location of a remote server, and determines a popularity of the data item based on a frequency at which the data location is accessed by the at least one client. The system is further configured to determine a lease period of the data item based on the frequency and assigning the lease period to the data location.

Abstract: A storage device, method for processing a plurality of pieces of client data, and a chipset are provided. The storage device includes a first stage storage unit configured to receive the plurality of pieces of client data generated in bursts from a plurality of clients and store the received plurality of pieces of client data; a second stage storage unit configured to receive the plurality of pieces of client data from the first stage storage unit and store the received plurality of pieces of client data in a plurality of memory banks shared by the plurality of clients, respectively, in bursts; and a third stage storage unit configured to receive each of the plurality of pieces of client data from the second stage storage unit and store data of a transaction unit corresponding to a transmission unit for data processing.

Abstract: A wireless network performance management system and method. The system includes at least one collection agent for collecting data related to at least one of service coverage; service quality; and usage of public and/or private data networks for enterprise clients, and a reporting unit to graphically represent the collected data to at least one of track, troubleshoot, and analyze the one of the service coverage; the service quality; and the usage of public and/or private data networks for the enterprise clients.

Abstract: Described herein are methods of transferring arrays of data information by remote data memory access (RDMA). According to the method, data information in data arrays in a local place identified. The intended data and garbage data are identified. Contiguous intended data and garbage data are copied to a remote place when the amount of garbage data is below a threshold garbage data criteria, and only intended data is copied to the remote place when the amount of garbage data is above the threshold garbage data criteria amount. Copying relies on scatter/gather input/output of RDMA. The garbage data transferred to the remote place is forwarded to a free list of the remote place.

Abstract: Techniques for improving the performance of a quantum processor are described. The techniques include reading out a fraction of the qubits in a quantum processor and utilizing one or more post-processing operations to reconstruct qubits of the quantum processor that are not read. The reconstructed qubits may be determined using a perfect sampler to provide results that are strictly better than reading all of the qubits directly from the quantum processor. The composite sample that includes read qubits and reconstructed qubits may be obtained faster than if all qubits of the quantum processor are read directly.

Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.

Abstract: A device and method of precise distance measurement of a transmission line to any object below it is disclosed, along with a network of such devices. The technique employs ultrasonic or laser sensor technology to measure the distance to the nearest object, be it vegetation or a crossing conductor below, and reports that distance wirelessly to the system operator or transmission asset owner. The ultrasonic measurement package may be part of a Transmission Line Security Monitor, which mounts to a transmission line conductor and is powered by the transmission line, transmitting the data by radio links. The technology is equally applicable to encroachment of objects from the side (for example, other transmission lines), as well as to other electrical lines, such as distribution lines, or to other sensing. A built-in transceiver allows the device to communicate with other devices and forward alerts from these devices in a daisy-chain fashion to the intended recipient.

Abstract: A method truncates text entered via a text box user interface element. The method includes displaying a user interface on a display device of a client computing device, where the user interface includes first and second text entry fields within a collapsible text entry box. The method further includes receiving a first stream of characters into the first text entry field, initially displaying all characters of the first stream as the first text entry field receives the first stream, truncating the displayed characters of the first stream, resolving the truncated displayed characters of the first stream to a first object displayed within the collapsible text entry box, receiving a second stream of characters into the second text entry field, and further truncating the displayed characters of the first stream while receiving the second stream of characters into the second text entry field.

Abstract: A system and process are disclosed for providing users with page previews during page loading events, such that the delay experienced before the display of page content is reduced. The previews may include screenshots of the pages or of portions thereof, and may be generated periodically and cached by the system for delivery to user devices. The process of generating and delivering the previews via the Internet or some other network may be implemented partly or wholly within an intermediary system that sits logically between the user devices and content servers. The process may be used with existing browsers without the need for any browser modifications, or may be used with a “preview-aware” browser that includes special program code for providing page previews.

Abstract: A method for arranging graphical objects in an electronic document displayed on a screen of a computing device includes calculating a plurality of positions of the graphical objects displayed on a display area of the screen, grouping the graphical objects whose calculated positions are located within a predetermined area of the display area, calculating a reference point of the group based on each position of the grouped graphical objects, reflowing the grouped graphical objects in response to a variation in display of the electronic document, calculating potential energies for the reflowed graphical objects, and displaying the electronic document with the reflowed graphical objects in a layout having the minimum potential energy among the calculated potential energies.

Abstract: Concepts and technologies are described herein for transforming data to create layouts. In accordance with the concepts and technologies disclosed herein, a computing device can execute a layout generator. The computing device can be configured to receive or retrieve data that includes visual content such as an image and other content such as text. The computing device can analyze the visual content to identify a salient region and/or an invariant region within the visual content. The computing device can access designs for laying out visual content and other content based upon an identified salient region and/or invariant region. The computing device can evaluate the designs to determine if a design matches the data. The computing device can load the data into the selected design to generate the layout.

Abstract: A method and an apparatus of building an intermediate character library are provided. The method comprises: acquiring an original character library which stores contour information of characters therein; dividing the characters in the original character library into character components, so as to acquire contour information of character components after division; and storing the contour information of the character components into the original character library so as to build an intermediate character library on the original character library. With the intermediate character library constructed by the method of the present invention, the font creation person can perform selecting and processing simultaneously on multiple single-contour components of a single character during creating of fonts, so that the operation process is simplified and the operation efficiency is improved.

Abstract: Methods, systems, and apparatus for tracking user clicks on result links in a search result webpage disclosed. In one aspect, a method includes generating one or more webpages each including a link to a destination document; specifying a style for the link in each webpage according to a style sheet language, the style including a behavior trigger indicating user selection of the link and a display property that causes retrieval of a resource from a remote server when the behavior trigger is activated; providing the webpages with the specified style to a plurality of clients; receiving at the remote server one or more requests from at least one of the plurality of clients for the resource; and in response to the receiving, recording a count for user selection of the destination document based on a number of received requests for the resource.