Abstract: According to one aspect of the present disclosure, a process for analyzing components related to a software application in a software development environment is disclosed. The process includes obtaining metadata information for each of a plurality of components from the software development environment, and generating an entry including extracting attribute information from the obtained metadata information for each component for use by a developer of the software application.

Abstract: The present disclosure relates to system(s) and method(s) for registration of a custom component on a Stream Analytics Platform. The system is configured to receive a program file and one or more registration instructions corresponding to the custom component, from a primary user of the Stream Analytics Platform. Further, a program code may be extracted from the program file by parsing the program file. Further, the system is configured to register the program code as a registered custom component, on the Stream Analytics Platform based on the one or more registration instructions. Once registered, the registered custom component is available over a Graphical User Interface (GUI) of the Stream Analytics Platform. The system enables at least the primary user or a set of secondary users of the Stream Analytics platform to use the registered custom component, based on the one or more registration instructions, for designing a distributed processing pipeline.

Abstract: An interrelated set of tools and methods are disclosed for recording the identity of software components responsible for creating files, recording the identity of software components that access software files, reasoning about the dependency relationships between software components, identifying and reporting undesirable dependencies between them, and reporting other useful information about a large-scale software architecture by instrumenting a software build process or test process.

Abstract: Methods of generating a help files are presented including: accessing a user model, where the user model defines a number of objects and a number of relationships between the number of objects; selecting an object of the user model; receiving a text file corresponding with the object; creating a component of the help file from the text file; selecting an additional object of the user model, the additional object having a relationship with the object, the relationship corresponding with the number of relationships; and creating an additional component of the help file corresponding with the additional object. In some embodiments, methods further include: detecting a change to the user model; and regenerating the help file to incorporate the change. In some embodiments, methods are presented where the additional component includes: a link to the additional object, and a link to a respective text file of the additional object.

Abstract: A cognitive container includes a set of managers for monitoring and controlling a computational element based on context, constraints and computing resources available to that computational element. Collectively, the set of managers may be regarded as a service regulator that specifies the algorithm context, constraints, connections, communication abstractions and control commands which are used to monitor and control the algorithm execution at run-time. The computational element is the algorithm executable module that can be loaded and run. The managers may communicate with external agents using a signaling channel that is separate from a data path used by the computational element for inputs and outputs, thereby providing external agents the ability to influence the computation in progress.

Abstract: A processing device includes an instruction control unit outputting an instruction fetch request; a primary cache having a request port for the instruction fetch request and a cache processing unit that outputs instruction data for the instruction fetch request; and a secondary cache returning the instruction data to the primary cache. The request port has a primary port provided in common to threads and storing information on the instruction fetch requests of the threads, secondary ports provided for each threads, and each storing entry numbers of the primary port, and a request determination unit determining, from among the entered instruction fetch requests, an instruction fetch request to be input to the primary cache, with priority on an instruction fetch request waiting for being input to the primary cache, in an order of the instruction fetch requests of the respective threads that are output from the instruction control unit.

Abstract: The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point addition operations, and fixed-point addition operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block may efficiently perform a single-precision floating-point addition operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point addition operation. In some embodiments, four specialized processing blocks that are arranged in a one-way cascade chain may compute the sum of two double-precision floating-point number. If desired, two specialized processing blocks that are arranged in a two-way cascade chain may compute the sum of two double-precision floating-point numbers.

Abstract: In a pipelined element configured to execute multiple contexts and including an instruction pipeline and a plurality of context modules each having a register file and a functional unit, a method includes scheduling a first context for execution in the instruction pipeline. The instruction pipeline includes an execution unit having a plurality of functional units. Each functional unit of the plurality of functional units is configured to execute instructions of a scheduled context of the plurality of contexts. A first instruction of the first context which precedes an instruction loop of the first context is executed. In response to executing the first instruction, the first context is released from being scheduled for execution in the instruction pipeline and execution of the first context is continued using a first context module. The first context module includes a context-specific functional unit configured to execute the instruction loop.

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Such a multi-slice processor includes a plurality of execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Operation of such a multi-slice processor includes, storing, in one or more logical units of a plurality of logical units of an age array, a logical value representing a relative age between instructions; propagating, in response to a current instruction being in a hang state, a hang signal to the plurality of logical units of the age array; in response to the hang signal, generating, from the plurality of logical units, a plurality of logical output values indicating a next instruction ready for execution; and issuing the next instruction for execution.

Abstract: A dispatcher circuit receives sets of instructions from an instructing entity. Instructions of the set of a first type are put into a first queue circuit, instructions of the set of a second type are put into a second queue circuit, and so forth. The first queue circuit dispatches instructions of the first type to one or more processing engines and records when the instructions of the set are completed. When all the instructions of the set of the first type have been completed, then the first queue circuit sends the second queue circuit a go signal, which causes the second queue circuit to dispatch instructions of the second type and to record when they have been completed. This process proceeds from queue circuit to queue circuit. When all the instructions of the set have been completed, then the dispatcher circuit returns an “instructions done” to the original instructing entity.

Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.

Abstract: Managing an accelerator may include responsive to determining a first container including a first configuration file and a second configuration file, caching, using a host processor, the second configuration file within a local memory of the host processor. The first configuration file may be provided, using the host processor, to a device of the accelerator. Responsive to a configuration event, the host processor may provide the cached second configuration file from the local memory to the device of the accelerator.

Abstract: A pluggable cloud enablement boot device (PCEBD) is a bootable device that includes all information needed to automatically provision hardware and software to create a computing solution that meets customer requirements. This allows for quickly deploying a computing solution in a manner that eliminates many manual steps that are typically performed today. The PCEBD uses firmware to verify a given platform has sufficient resources to deploy the PCEBD. The computing solution, once provisioned and running, can be modified, and these modifications may be reflected in the definition of the PCEBD. In addition, a computing solution may include multiple resources provisioned from multiple PCEBDs, which can be packaged into a PCEBD that will include other PCEBDs. The result is a way to deploy computing solutions that is much more efficient than the manual methods used in the prior art.

Abstract: A pluggable cloud enablement boot device (PCEBD) is a bootable device that includes all information needed to automatically provision hardware and software to create a computing solution that meets customer requirements. This allows for quickly deploying a computing solution in a manner that eliminates many manual steps that are typically performed today. The PCEBD uses firmware to verify a given platform has sufficient resources to deploy the PCEBD. The computing solution, once provisioned and running, can be modified, and these modifications may be reflected in the definition of the PCEBD. In addition, a computing solution may include multiple resources provisioned from multiple PCEBDs, which can be packaged into a PCEBD that will include other PCEBDs. The result is a way to deploy computing solutions that is much more efficient than the manual methods used in the prior art.

Abstract: A network switch can be configured using a boot loader after a reset of a controller within the network switch. The boot loader configures switching logic within the network switch prior to an operating system becoming operational. By allowing the boot loader to configure the switching logic, the network switch can become operational as fast as possible.

Abstract: Executable files are managed. A determination is made as to whether in a second executable file there exists a function that is the same as a function called in a first executable file. A data package is generated on a portion other than the function in the first executable file and the second executable file, and the function is stored in relation to the data package. The data package includes a first address of the function in the first executable file and a second address of the function in the second executable file.

Abstract: A processor includes a core within a package and layers of programmable fabric within the same package as the core. The core includes logic to execute an instruction by loading a configuration file to one of the layers of programmable fabric. The configuration is to program an identified execution functionality. The execution functionality is to execute at least part of the instruction.

Abstract: A method for dynamically loading one or more Extensible Mark-up Language (XML) schema definition (XSD) files into a JAVA™ Virtual Machine (JVM) during runtime is provided. The method includes generating JAVA™ objects from one or more initial XSD files. The method further includes grouping the JAVA™ objects by namespaces. The method also includes creating new XSD files for the namespaces. The new XSD file includes references to the initial XSD files that include a same namespace. The method further includes generating JAVA™ classes from the new XSD files. The method also includes compiling the new JAVA™ classes into bytecode. The bytecode is loaded into a ClassLoader, wherein the ClassLoader is available to the JVM during runtime.

Abstract: A system and method for providing dynamic information virtualization (DIV) is disclosed. According to one embodiment, a device includes a dynamic optimization manager (DOM), a process and memory manager (PMM), a memory, and a host device driver. The device starts virtual functions after booting to allow a virtual machine (VM) running a guest operating system to identify the virtual functions and load virtual drivers of the virtual functions. The PMM allocates a unified cache from the memory to facilitate coherent access to information from storage and network resources by the VM. The host device driver enables a guess process in the VM to access the information stored in the unified cache in a secure and isolated manner.

Abstract: The current document is directed to methods for aggregating host computers into distributed computing systems and to distributed computing systems created by the methods. In a described implementation, host computers are aggregated into two or more clusters, at a first distributed-computing-system level, each managed by a second-level management server. The two or more clusters are then, in turn, aggregated into a hierarchical distributed computing system managed by a top-level management server. The top-level management server is interconnected to, and accesses, the second-level management servers through a host-gateway appliance that includes host-gateway control logic implemented within a server computer. In order to achieve scalability and efficiency, the top-level management server provides a subset of the native management commands to system administrators and other users who access a management interface provided by the top-level management server.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: Systems, articles, and methods of context switching include requesting a transition context switch deferrable until a state to be saved is smaller than at the time the request is made, and forcing a context switch to occur if a condition is met before the request is carried out.

Abstract: A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.

Abstract: A method for managing a background application is provided. The method includes determining whether an operating feature of the background application satisfies a preset condition, and when it is determined that the operating feature of the background application satisfies the preset condition, displaying an operating interface in a foreground interface of a mobile device for a user to close the background application.

Abstract: Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. The order of transfer between the processor core is based upon a programmable indicator. During a context restore operation information is concurrently provided to data bus from both the accelerator and the processor core.

Abstract: An implementation of the disclosure provides a scheduler for scheduling multi-phase computing jobs where each phase utilizes different amount of resources for executing the jobs in that phase. To schedule the jobs, the scheduler receives a profile for a computing job describing the execution phases associated with one more complied executable modules. The profile includes a plurality of job phase definitions. Each job phase definition includes an estimated amount of computing resources utilized by executing a respective job phase. An identifier of the computing job is appended to a job queue. A combination of one or more computing jobs is selected from the job queue. Thereupon, this combination is scheduled for execution, if it is determined that a total of the estimated amount of computing resources for executing computing jobs in each of one or more of the respective jobs phases satisfies a threshold resource amount associated with the combination.

Abstract: Backfill scheduling for embarrassingly parallel jobs. A disclosed method includes: receiving an initial schedule having a plurality of jobs scheduled over time on a plurality of nodes, determining that a first job can be split into a plurality of sub-tasks that can respectively be performed in parallel on different nodes, splitting the first job into the plurality of sub-tasks, and moving a first sub-task from its position in the initial schedule to a new position to yield a first revised schedule.

Abstract: A method of scheduling jobs includes receiving a plurality of jobs that require execution, identifying a plurality of agents that are configured to execute at least one of the plurality of jobs, identifying a plurality of time windows in which the plurality of agents are, available to execute the plurality of jobs, identifying a constraint rule on the execution of the plurality of jobs, and identifying a plurality of possible execution paths. Execution paths that do not comply with the constraint;rule are removed from the plurality of possible execution paths to provide a preferred set of execution paths. The method further includes calculating a metric for each of the preferred set of execution paths, selecting an execution path in response to the metric, and causing the plurality of jobs to be executed by at least one of the agents according to the selected execution path.

Abstract: A method for scheduling virtual machines in a virtual machine cluster includes obtaining a filename of a target virtual machine when a user requests to start the target virtual machine; inquiring, based on the filename of the target virtual machine, a storage module or a database to acquire one or more nodes where copies of the target virtual machine are located; selecting, from the acquired one or more nodes, a node with a highest score as a target node having a copy of the target virtual machine; and running the copy of the target virtual machine on the selected target node with the highest score.

Abstract: An example method is described to provide fault tolerance in a virtualized computing environment with a first fault domain and a second fault domain. The method may comprise determining whether a first primary virtualized computing instance and a first secondary virtualized computing instance are both in the first fault domain. The method may comprise: in response to determination that the first primary virtualized computing instance and first secondary virtualized computing instance are both in the first fault domain, selecting a second secondary virtualized computing instance from the second fault domain; migrating the first secondary virtualized computing instance from a first host to a second host; and migrating the second secondary virtualized computing instance from the second host to the first host, thereby swapping the first secondary virtualized computing instance in the first fault domain with the second secondary virtualized computing instance in the second fault domain.

Abstract: A method of managing computing resources and reducing execution time. The method includes: receiving, by a computing resource scheduler, a request to calculate a first value based on a first input data set; initiating, by the computing resource scheduler and on a plurality of computing resources, parallel execution of a plurality of processes to calculate the first value, where each of the plurality of processes is configured to independently calculate the first value based on the first data set; receiving, by the computing resource scheduler, the first value from a first winning process of the plurality of processes; and freeing the plurality of computing resources by aborting a losing process of the plurality of processes in response to receiving the first value from the first winning process.

Abstract: Resource provisioning information links to resource provisioning information of at least one reusable component resource that satisfies at least a portion of user-specified resource development constraints of a new resource under development are identified within a resource provisioning-link registry. Using the identified resource provisioning information links, the resource provisioning information of the at least one reusable component resource is programmatically collected from at least one data provider repository that stores reusable resources and that publishes the resource provisioning information links to the resource provisioning-link registry. The programmatically-collected resource provisioning information of the at least one reusable component resource is analyzed.

Abstract: A method for estimating job start times on a system may include: performing a first simulation of the system by a first process to generate a first estimate of the start time based a first snapshot of the computing system; and performing a second simulation of the system to generate a second estimate of the start time. The first and second estimates may each be either a distinct time estimate or a range of time estimate, depending on whether the simulations dispatches the job before the respective first and second processes end. The method may then include generating a fifth estimate of the time that the computing job will start by a third process based on estimates respectively generated by the first and second processes.

Abstract: Techniques are described for distributing network device tasks across virtual machines executing in a computing cloud. A network device includes a network interface to send and receive messages, a routing unit comprising one or more processors configured to execute a version of a network operating system, and a virtual machine agent. The virtual machine agent is configured to identify a virtual machine executing at a computing cloud communicatively coupled to the network device, wherein the identified virtual machine executes an instance of the version of the network operating system, to send, using the at least one network interface and to the virtual machine, a request to perform a task, and to receive, using the at least one network interface and from the virtual machine, a task response that includes a result of performing the task. The routing unit is configured to update the network device based on the result.

Abstract: A deployment system orchestrates execution of deployment plan in coordination with nodes participating in deployment of a multi-tier application in a cloud infrastructure. The deployment system distributes local deployment plans to each node and maintains a centralized state of deployment time dependencies between tasks in different local deployment plans. Prior to execution of each task, deployment agents executing on each node communicates with the centralized deployment system to check whether any deployment time dependencies need to be resolved. Additionally, the deployment system utilizes a node task timer that triggers a heartbeat mechanism for monitoring failure of deployment agents.

Abstract: A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.

Abstract: For predictive computing resource allocation in a distributed environment, a model module generating a model of computing resource usage in a distributed computer system having a plurality of geographically distributed nodes organized into a plurality of clusters, a demand module predicting future demand for computing resources, a cost module calculating an operation cost for each computing resource, an available resource module identifying a set of available computing resources in the computer system, a resource set module that determines a minimum cost set of computer resources capable of meeting the predicted demand based on the set of available computing resources and on operating costs, and an activation module that determines whether to activate or deactivate each of the plurality of nodes based on the set of computer resources capable of meeting the predicted demand.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include identifying a first number of processors in a computer, and identifying a second number of interrupt request (IRQ) lines on a hardware acceleration device in the computer and coupled to the processors, the second number greater than or equal to the first number. Each of the IRQ lines is associated with one of the processors, and upon selecting a given IRQ line for an application thread, a given processor associated with the given IRQ line is identified. Execution of the application thread is initiated on the given processor, and using the given IRQ line, a completion queue is configured for the application thread. If the thread is executing on a different processor than the one managing the completion queue, then the management of the completion queue can be migrated to the processor executing the thread.

Abstract: According to some embodiments, a method includes running a first application program on a computer system, running a second application program on the computer system, and running a data availability manager (DAM) program on the computer system. The first application program is operative to indicate to the DAM program that a first data item processed by the first application program is available for further processing. The DAM program is operative to determine a second data item that is dependent for processing upon availability of the first data item and to indicate to the second application program that the second data item is ready for processing.

Abstract: Methods and systems for profiling requests include generating request units based on collected kernel events that include complete request units and half-open request units. The generated request units are sequenced based on a causality relationship set that describes causality relationships between kernel events.

Abstract: Generic Distributed Processing Unit (DPU) for Multi-Agent Systems (MAS) provides a Machine to Machine (M2M) interface that is fast, flexible, redundant and scalable. It allows the handling of unlikely edge cases that Human Machine Interfaces (HMI) cannot. It also allows the processing of excessive amounts of ancillary data that are not processed easily with an HMI arrangement. In the digital ecosystem, any like DPU can back up any other, making the system exceedingly robust.

Abstract: A system, method and computer program product are provided for receiving information associated with a message, issuing a storage resource request in connection with a storage resource and determining whether the storage resource is available. In use, the information is capable of being shared in less than one second, utilizing an automotive electronic control unit which includes a plurality of interfaces.

Abstract: Systems and methods for executing a quantum computation comprising a plurality gates on a quantum information processor are provided. An initial quantum-logic gate sequence comprising the plurality of gates is received. Then, for each instance in a plurality of instances, a procedure is performed. In each instance of the procedure a respective modified quantum-logic gate sequence is generated by applying a virtual random gate to a first single-qubit gate in the plurality of gates. The respective modified quantum-logic gate sequence is then executed on the quantum device to obtain a respective outcome. The respective outcome across the plurality of instances of the procedure is averaged to obtain a noise-tailored outcome for the initial quantum-logic gate sequence.

Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs.

Abstract: An apparatus-implemented method according to one embodiment includes detecting an error while writing data to a tape volume on a tape and repositioning the tape in response to detecting the error. A determination whether a rewrite of data associated with the error to the tape volume is allowed is made based on a current position of the tape after the repositioning. The data is rewritten to the tape volume in response to determining that the rewrite of data associated with the error to the tape volume is allowed. A computer program product for protecting overwrite of a tape volume according to another embodiment includes a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a controller to cause the controller to perform the foregoing method.

Abstract: A method, computer program product, and computing system for monitoring the availability of multiple redundant data sources within a high-availability data environment. The inaccessibility of at least one of the multiple redundant data sources is detected, thus defining at least one inaccessible data source. Which software applications are impacted by the at least one inaccessible data source is determined, thus defining at least one impacted software application. A notification is provided to one or more parties associated with the at least one impacted software application concerning the inaccessibility of the at least one inaccessible data source.

Abstract: In a general aspect, a conversion scheme is used in a public key cryptosystem. In some aspects, a plaintext value is generated based on a message value, a constant value, and a random value. An error vector derivation function is applied to the plaintext value to produce an error vector. The plaintext value and the error vector are used in an encryption function to produce a ciphertext component, and the ciphertext component is provided for transmission in a communication network.