Abstract: A method and apparatus are disclosed for detecting a user selection of a positioning tag; retrieving directional information and timestamp information relating to the selected tag; comparing directional information relating to the selected tag with directional information of an array of cameras arranged to capture video content from a recording area; identifying video content captured by one or more cameras from an array of cameras arranged to capture video content from a recording area, wherein the video content captured by the one or more cameras is identified if the one or more cameras have captured video content from a section of the recording area relevant to the location of the selected tag over a time period relevant to the timestamp information relating to the selected tag; and selecting the identified video content obtained from the one or more cameras for display.

Abstract: A communication apparatus configured to transmit information about content stored in an external apparatus is enabled to autonomously perform control based on a state based on reproduction processing of the content in a destination to which the information is transmitted. Another communication apparatus configured to receive related information about the content from the communication apparatus and perform the reproduction processing on the content based on the related information transmits information about the state related to the reproduction processing of the content. The communication apparatus receives the information about the state related to the reproduction processing of the content, and performs control based on the received information.

Abstract: This application discloses a video recording method and apparatus of a mobile terminal. The video recording method includes obtaining a target video that is played online, controlling to display a video recording page in which the target video is played, and receiving, via the video recording page that is displayed, a recording instruction for recording the target video. The video recording method further includes entering a recording mode to record the target video, in response to the recording instruction being received, to obtain a first video clip corresponding to video data of the target video, and generating a recorded video of the target video, based on the first video clip.

Abstract: A method of servicing a data storage library having at least one access opening and at least one access door to permit access to an interior of the data storage library, the method including providing at least one barrier configured to at least partially surround the at least one library access opening when the at least one access door is opened, wherein the at least one barrier is configured to resist environmental conditions from exterior the barrier and data storage library from intruding into the interior of data storage library when the barrier is deployed. The method also includes deploying the at least one barrier when the at least one access door is opened to form an interior working space, accessing the interior space formed by the at least one barrier, and accessing the interior of the data storage library via the at least one library access opening.

Abstract: A data storage library system includes at least one data storage library, the at least one data storage library comprising at least one library frame, wherein the at least one library frame has at least one environmental conditioning unit configured to control one or more environmental conditions within the at least one library frame. The system also includes at least one access door for providing access to an interior portion of the at least one library frame, a library controller, and at least one louver, where the louver may be selectively moveable to control a communication pathway for external air to enter the at least one library frame. In one embodiment, the at least one louver may be controlled by the library controller to automatically open when it is detected that the one or more access doors are opened, and to close the louver when the one or more access doors are closed.

Abstract: A method of controlling at least one environmental condition within a data storage library, including providing at least one enclosure configured to surround at least one ventilation opening of the data storage library and to form a chamber around at least the at least one ventilation opening, and providing at least one enclosure environmental conditioning unit fluidly connected to the at least one enclosure to provide conditioned air into the chamber. The method may also include providing air from the at least one enclosure environmental conditioning unit into the chamber such that air provided into the chamber enters the data storage library through the at least one ventilation opening.

Abstract: A data storage library includes at least a first library portion and at least a second library portion, with the second library portion including an environmental conditioning unit configured to control environmental conditions within the second library portion. The data storage library also includes at least one acclimation chamber formed within the first library portion, which permits transition of environmental condition(s) within the at least one acclimation chamber toward at least one of the corresponding environmental condition(s) external and internal to the second library portion. At least one deployable environmental barrier is configured to extend at least partially between the first library portion and the second library portion to insulate the at least one environmental condition within the at least one acclimation chamber from the at least one environmental condition within the second library portion.

Abstract: A disk drive includes a metal base that has a rectangular bottom wall and side walls formed on each side of the rectangular bottom wall, the side walls including a first side wall on a shorter side, a metal cover that is fixed to the metal base with a plurality of metal screws, including two screws disposed at opposite ends of the side wall, a gap being formed between an upper end of the first side wall and the metal cover, a magnetic disk disposed on the metal base, at a position offset from a center of the metal base in a longitudinal direction towards the first side wall, and a head. The first side wall and the metal cover are electrically connected at an intermediate position of the first side wall between said opposite ends of the first side wall.

Abstract: Apparatuses and methods for transmitting die state information between a plurality of dies are described. An example apparatus includes: a plurality of dies, wherein each die of the plurality of dies includes a first through electrode and a second through electrode; a first path including the first electrodes of the plurality of dies in series; and a second path including the first electrodes of the plurality of dies in series. The first path transmits first internal state information related to a first state of at least one die of the plurality of dies. The second path transmits second internal state information related to a second state of at least one die of the plurality of dies.

Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.

Abstract: A variable resistance non-volatile semiconductor memory device comprises a memory cell having variable resistance element connected in series with a selection transistor. The selection transistor has a control terminal connected to a word line. A first end of the memory cell is connected to a bit line. A second end of the memory cell is connected to a first power supply line. An additional resistor is connected between a second power supply line and the bit line. The first power supply line is a low potential and the second power supply line is a high potential. During a reading operation of the memory cell, a read current flows through the first resistor and the memory cell.

Abstract: A semiconductor device includes a data output selection circuit suitable for outputting first pattern data as selection data in the case where a training operation is performed, outputting information data as the selection data in the case where a mode register read operation is performed, and outputting second pattern data in the case where the training operation is performed; and a data pad circuit including a first data pad and a second data pad, wherein the first data pad outputs the selection data and the second data pad outputs the second pattern data.

Abstract: A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.

Abstract: A semiconductor device may be provided. The semiconductor device may include a period code generation circuit configured to generate a period code having a logic level combination corresponding to a first command or a second command. The semiconductor device may include a code synthesis circuit configured to add the period code to a previous synthesis code to generate a synthesis code. The semiconductor device may include a buffer control circuit configured to compare the synthesis code with a selection control code to generate a buffer inactivation signal for controlling input of a data strobe signal.

Abstract: A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states;a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines;and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.

Abstract: A magnetic memory of an embodiment includes: first through third terminals; a conductive layer including first through third portions, the first portion being located between the second and third portions, the second and third portions being electrically connected to the first and second terminals respectively; and a magnetoresistive element including: a first magnetic layer electrically connected to the third terminal; a second magnetic layer disposed between the first magnetic layer and the first portion; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third magnetic layer disposed between the first nonmagnetic layer and the second magnetic layer; and a second nonmagnetic layer disposed between the second magnetic layer and the third magnetic layer, a sign of a spin Hall angle of the second nonmagnetic layer being different from a sign of a spin Hall angle of the conductive layer.

Abstract: A magnetoresistive element according to an embodiment includes: a first nonmagnetic layer; a first magnetic layer; a second magnetic layer disposed between the first nonmagnetic layer and the first magnetic layer; a second nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third nonmagnetic layer disposed between the second nonmagnetic layer and the second magnetic layer; and a third magnetic layer disposed between the second nonmagnetic layer and the third nonmagnetic layer, wherein elements constituting the second magnetic layer at least partially differ from elements constituting the third magnetic layer, a relative permittivity of the first nonmagnetic layer is at least 10, and the third nonmagnetic layer contains at least one element selected from the group consisting of Nb, Ta, Mo, W, Hf, Zr, Ti, Sc, V, Cr, Mn, Fe, Co, Ni, Mg, Al, Ru, Ir, Rh, Pd, Pt, Cu, Ag, and Au.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, and a controller. The conductive layer includes a first portion, a second portion, and a third portion. The first magnetic layer is separated from the third portion. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer that is electrically connected with the third portion. The first nonmagnetic layer is curved. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation. The controller in the first operation supplies a first current to the conductive layer from the first portion toward the second portion. The controller in the second operation supplies a second current to the conductive layer from the second portion toward the first portion.

Abstract: A magnetic memory device includes a magnetic element and a write circuit electrically connected to two nodes of the magnetic element and configured to provide a write current to the magnetic element, wherein the write current includes a first current having a first peak applied for a first time period and a second current having a second peak applied for a second time period, where the second peak is smaller than the first peak and the second period is longer than the first time period.

Abstract: Memory latch comprising: a TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the TFET; a control circuit configured to supply a first electric potential on a second terminal of the capacitor, a second electric potential on the gate of the TFET and a third electric potential on a second electrode of the TFET, such that: when the stored potential is low, the TFET is reverse biased with a conduction current obtained by band-to-band tunneling with a value higher than a capacitor leakage current; when the stored potential is high, the TFET is reverse biased with an OFF state current value less than the capacitor leakage current.

Abstract: A semiconductor memory device includes a memory cell transistor, a word line coupled to the memory cell transistor, a temperature detection element configured to detect a temperature, and a control unit. The control unit is configured to determine, responsive to receiving a first command from a controller, a compensation value for a read voltage designated by the controller according to the detected temperature, and to lock updating of the compensation value.

Abstract: A semiconductor memory device includes a memory cell array and a row decoder disposed in a first direction over a substrate and a plurality of coupling lines for electrically coupling the memory cell array and the row decoder. Each of the coupling lines includes a first conductive line disposed in the first direction; a second conductive line disposed parallel to the first conductive line; and a pad coupling the first conductive line and the second conductive line, and coupled to the memory cell array or the row decoder through a contact plug. The coupling lines are routed from both sides of the pad in the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.

Abstract: The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.

Abstract: A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors connected in parallel between a first node connected to the memory cell and a second node connected to the sense amplifier. The first transistor has a size that is different from the second transistor. Each of the first and second transistors has a gate that is connected to a first voltage source. A switch circuit controls a conduction state between the first and second nodes via separate paths through the first transistor and the second transistor. The sense amplifier compares a first current supplied to the memory cell via the first path at a first timing and a second current supplied to the memory cell via the second path at a second timing different from the first timing.

Abstract: A non-volatile semiconductor memory device includes a current source providing a reference current to a first node and a clamp circuit. The clamp circuit includes a transistor having a current path between the first node and a second node, and an amplifier circuit having a first input port at which a cell reference voltage can be received, a second input port connected to the second node, and an output port connected to a control terminal of the transistor. The amplifier circuit is configured to output a differentially amplified signal from the output port. A memory cell is connected between a bit line and a word line and includes a variable resistance element. The bit line can be connected to the second node. A sense amplifier is connected to the first node to detect data stored in the memory cell.

Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

Abstract: A preferred data storage with in-situ string-searching capabilities comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional vertical one-time-programmable memory (3D-OTPV) array vertically stacked above a pattern-processing circuit. The 3D-OTPV array stores at least a portion of big data. A search string from the input is sent to all SPUs, which perform string searching simultaneously.

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

Abstract: A storage device includes a circuit on a substrate, electrode layers stacked on the circuit, a channel layer penetrating the electrode layers in a stacking direction, a plate-shaped first wire between the electrode layers and the circuit and electrically connected to the channel layer, a second wire at a level between the circuit and the first wire, a third wire between the circuit and the second wire, a contact plug penetrating the electrode layers and the first wire in the stacking direction and electrically connected to the second wire, and a columnar support body penetrating the electrode layers and the first wire in the stacking direction. The columnar support body has a lower end in contact with the second wire or the third wire. The first wire has a through-via-hole above the second wire, and the contact plug and the columnar support body are disposed inside the through-via-hole.

Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.

Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Abstract: According to one embodiment, a memory system includes a storage medium including a first cell transistor, a first data latch, and a second data latch; and a first controller. The first controller is configured to instruct to the storage medium to, after instructing the storage medium to write data into the first cell transistor and before completion of the writing of the data into the first cell transistor, suspend a process being performed to the first cell transistor, read data from the first data latch, read data from the second data latch, and read data from the first cell transistor.

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Abstract: A memory card is provided to include a substrate having two pairs of edges facing each other, a plurality of first row terminals that are arranged adjacent to an edge at an insertion side of the substrate and include a first voltage power terminal for applying a first voltage and a first ground terminal, a plurality of second row terminals that are spaced farther apart from the edge at the insertion side than the plurality of first row terminals and include a second voltage power terminal for applying a second voltage and first data terminals, and a plurality of third row terminals that are spaced farther apart from the edge at the insertion side than the plurality of second row terminals and include second data terminals.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.

Abstract: The embodiments of the present disclosure provide a shift register, a gate driving circuit and a display apparatus. The shift register comprises an input unit, a first reset unit, a node control unit, a gate-shaping unit, a first output unit and a second output unit. The shift register is configured to change a potential of a scan signal outputted from a driving signal output terminal, so as to produce a scan signal having a gate-shaped waveform.

Abstract: Embodiments are generally directed to board level leakage testing for a memory interface. An embodiment of an apparatus includes multiple logic cells for testing of a memory interface, each logic cell being connected to an interconnect for a respective memory element. Each logic cell includes a driver to drive a signal onto the interconnect with the respective memory element, an element to generate a value for the logic cell by comparing a signal with a reference voltage, a flip-flop to capture a cell value for the logic cell, and a drive control element to control the value driven on the interconnect by the driver. The apparatus further includes a processor to identify failure conditions based at least in part on testing using the logic cells.

Abstract: A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.

Abstract: A test method for a memory device may include: performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit; performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region; performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit; and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.