Abstract: A fault tolerant computer system having two virtual machines (VMs), each running on a separate host device, is connected over a network to one or more I/O devices. The system operates to monitor the health of one or more operational characteristics associated with each VM, and in the event that the health of both virtual machines dictates that one or the other of the VMs should be downgraded, but the system is not able to determine which VM should be downgraded and there is an imbalance in a monitored system operational characteristic, the system can defer downgrading one VM for a selected period of time during which the operational characteristic that is in imbalance is monitored. If the imbalance is resolved, the downgrade is cancelled, if an operational fault is confirmed prior to the expiration of the deferral period or if the deferral period expires, then one host is downgraded.

Abstract: Disclosed herein is a test circuit for a 3D semiconductor device for detecting soft errors and a method for testing thereof. The test circuit includes a first Multiple Input Signature Register (MISR) disposed in a first semiconductor chip, the first MISR compressing a first test result signal corresponding to a test pattern, a second MISR disposed in a second semiconductor chip stacked on or under the first semiconductor chip, the second MISR compressing a second test result signal corresponding to the test pattern, and a first error detector to detect a soft error by comparing a first output signal output from the first MISR with a second output signal output from the second MISR.

Abstract: A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a second device, a transaction processing packet, where the transaction processing packet includes processing information about access of a host to a peripheral component interconnect express (PCIe) device, the processing information is used to describe information required for resuming a transaction when the transaction is interrupted, the second device further stores topology information of the PCIe device, and a driver for the PCIe device is loaded to the second device, and when detecting that the first device fails, continuing to process, by the second device according to the topology information, the driver, and the processing information, the transaction that is about the access of the host to the PCIe device and is being processed when a first device fails.

Abstract: A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. Application software may be run on top of a virtual environment such as a virtual machine and/or a virtual disk environment. Should a software component fail, the virtual environment will “crash” but the ATM hardware and operating system will remain intact. If the software is fatally flawed—e.g., due to a faulty “upgrade” the older version may be “rolled back” from a previously stored virtual environment.

Abstract: Methods and apparatus to implement communications via a remote terminal unit are disclosed. An example apparatus includes a first central processing unit module to be in communication with a host of a process control system. The example apparatus also includes a first rack including a backplane and a plurality of slots. The plurality of slots includes a master slot to receive the first central processing unit module. The backplane communicatively couples the first central processing unit module to at least one of a first communication module or a first input/output (I/O) module inserted in a second one of the slots. The backplane includes a first communication bus for communication of I/O data and a second communication bus for communication of at least one of maintenance data, pass-through data, product information data, archival data, diagnostic data, or setup data. The first communication bus is independent of the second communication bus.

Abstract: In one embodiment, a system includes a cache storage device, a back-end storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive indication of failure of a primary cache server at a secondary cache server, the primary and secondary cache servers being configured to manage read requests and write requests for the back-end storage device. The logic is also configured to set the secondary cache server to a by-pass mode for read requests directed to any portions of the back-end storage device managed by the primary cache server prior to the failure. Moreover, the logic is configured to read an index of cache block descriptors (CBDs) managed by the primary cache server prior to the failure into a memory of the secondary cache server.

Abstract: A software testing framework provides functionality for utilizing pre-existing tests to load and performance test a network service. Methods can be tagged with annotations indicating that they are tests, such as integration tests. The methods implementing the integration tests can also be tagged with other types of annotations that can be used to select individual tests for use in testing, such as annotations indicating whether a test is a positive or negative test, annotations specifying dependencies upon other tests, or annotations indicating that a test is a member of a test suite. The annotations can be utilized in conjunction with test selection criteria to select individual integration tests for use in load and performance testing of the network service. The selected integration tests can be deployed to and executed upon load-generating instances to execute the integration tests and generate requests to the network service at high throughput.

Abstract: Disclosed aspects include managing a set of wear-leveling data with respect to a set of physical cores of a set of compute nodes. A set of physical cores of the set of compute nodes may be monitored using a set of processor utilization resource registers (PURRs) to identify the set of wear-leveling data. By monitoring the set of physical cores of the set of compute nodes, a set of thread events with respect to the set of physical cores of the set of compute nodes may be detected. Based on the set of thread events, the set of wear-leveling data may be determined. The set of wear-leveling data may then be established in a data store. The wear leveling data may be used to manage asset placement with respect to a shared pool of configurable computing resources.

Abstract: Embodiments of the present invention provide a method, system and computer program product for predicting transaction server performance failure in a transaction processing environment. In an embodiment of the invention, a method for predicting transaction server performance failure in a transaction processing environment is provided. The method includes receiving a performance metric for a transaction server during nominal operation of the transaction server in memory of a computing system and comparing the performance metric to a benchmark of performance metrics for the transaction server. Thereafter, in response to the performance metric falling outside a threshold variance from the benchmark, an alert is generated of a potential impending failure of the transaction server.

Abstract: This disclosure provides a computer-implemented method for monitoring an application at runtime. The method comprises building up a calling relationship graph for at least one type of system method called at runtime, by checking a stack trace generated when the application is running. An application method of the application that directly or indirectly calls this type of system method is represented as a node in the calling relationship graph. The method further comprises determining one or more target nodes in the calling relationship graph by analyzing the structure of the calling relationship graph. The method further comprises inserting callback methods into application method(s) of the application corresponding to the one or more target nodes only in a calling side. The method further comprises monitoring the application at runtime by using said callback methods.

Abstract: Technical solutions are described for verifying translatability compliance of a new code for a computer program product includes receiving a notification about a check-in request for the new code, and in response determining whether to verify the translatability compliance of the new code. The method further includes, in response to the translatability compliance being verified, determining whether the new code includes a hardcoded message. Further, in response to identifying the hardcoded message, the method includes sending a warning notification to a developer of the new code. Also, the method includes enabling the check-in of the new code in response to the translatability compliance not being verified.

Abstract: A computer implemented method of detecting a fault in a system comprises the steps of executing at least three virtual machines, each virtual machine executing a same application software, in separated and isolated memory segments and in a dedicated core of a multi-core processor; the virtual machines being synchronized and concurrently executed by a common hypervisor; wherein non-faulty virtual machines provide an identical output message within a predefined time-interval; detecting a fault in an output of a virtual machine, the fault corresponding to a different output message of the faulty virtual machine. Developments include a distributed vote mechanism, pull/push mechanisms, association of output vote messages with a safety extension comprising identification information, virtual machine recovery using data context.

Abstract: A system for analyzing source code may include a computer including a memory and a processor. A discoverer may be stored on the memory and may be configured to automatically identify applications of an infrastructure and extract at least one input source code file corresponding to the identified applications. A file reader may be stored on the memory and may be configured to read the input source code file containing source code written in at least one computer programming language. A metrics accumulator may be stored on the memory and may be configured to analyze the source code components according to one or more rules to generate application metadata. A reporting engine may be stored on the memory and configured to generate a report based on the generated application metadata.

Abstract: A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the breakpoint triggers pre-fetching of disassembly code associated with the breakpoint. The pre-fetched disassembly code is retained in a store local to a debug analysis system. When runtime processing of the AUT reaches the breakpoint, the debug analysis system retrieves the disassembly code from the local store.

Abstract: Creating additional trace entries by dynamically processing recently captured output data, working data, and input data to diagnose a software error. Integrating additional trace entries in chronological order with conventional trace entries into a single trace dataset for analysis.

Abstract: Methods, systems, and computer program products are included for executing one or more instructions of a program in a debugging session; receiving a command at a debugger, the command comprising an expression for the debugger to evaluate in the debugging session; evaluating the expression, at least in part by the debugger, the evaluating including attempting to perform a write operation to write a data value to a target; preventing the data value from being written to the target; and outputting, by the debugger, a result of the evaluating.

Abstract: A system and methods are disclosed for testing guest firmware in virtualized computer systems. In accordance with one embodiment, a hypervisor executed by a processing device infers that firmware has created a system table in a portion of memory of a virtual machine. In response to the inferring, the hypervisor locates the system table and executes one or more commands to test the system table.

Abstract: A condition determination device includes an acquiring unit, a specifying unit, a classifying unit, and a condition determining unit. The acquiring unit acquires a total execution history, which is an execution count for each component included in a program, when a test is performed by supplying a plurality of input data to a target device which executes the program. The specifying unit specifies a shortage component of which the execution count indicated by the total execution history does not satisfy test criteria among components included in the program. The classifying unit classifies each of the input data into first data, which causes the target device to execute the shortage component, and second data, which does not cause the target device to execute the shortage component. The condition determining unit determines a condition of input data having a common characteristic with the first data.

Abstract: An application for testing is determined. A test script associated with the application for testing is determined. The application is tested using the test script. The testing requires transferring data form the application to an out-of-band channel.

Abstract: A test device may include an application that accesses online content. In some examples, a test intermediary and/or a test user interface (UI) are downloaded to the test device in response to a request by the application for obtaining the content from a network location. The test intermediary may be positioned to receive communications between the application and the content during testing of the content and/or the application. For example, the test intermediary may intercept metrics and other callbacks passed between the content and the application during manual or automated testing. In some instances, the test intermediary may provide the metrics and/or other test outputs for display in the test user UI rendered on the test device. The content may be rendered to be functional within the test UI, and the existence of the test intermediary and/or the test UI may be transparent to the application and the content.

Abstract: A system and method are provided for testing the performance of applications. By way of example only, the method may include training a neural network with documents containing text elements that are arranged in accordance with a defined format and using the neural network to determine the predictability of the value of individual text elements within a test document. When the neural network indicates that the value of a text element is unlikely, the value may be modified and the modified document may be used to test an application that processes documents in accordance with the defined format.

Abstract: Disclosures herein describe a record and replay regression and unit test automation framework for simulating any hardware on a virtual machine to achieve thorough, affordable and efficient software testing. According to the disclosures herein, the test automation framework includes a recording stage where input and output messages for all the interfaces for a process (e.g., an embedded system or any software system or process) running on the original hardware may be recorded along with metadata in a space-optimized and efficient manner. The testing framework also includes a replay stage using innovative thread synchronization approaches that leverage the metadata to simulate the environment for the recorded embedded process in isolation, which may be done on an inexpensive machine or hardware. Thus, the original custom hardware, which may be expensive and costly to run, is not needed for the replay phase of testing.

Abstract: One embodiment of the present invention provides a system for managing storage space in a mobile device. During operation, the system detects a decrease in available disk space in a host file system, wherein an image file for a guest system is stored in the host file system. In response to the detected decrease, the system increases a size of a balloon file in a storage of a guest system. The system then receives an indication of a TRIM or discard communication and intercepts the TRIM or discard communication. Next, the system determines that at least one block is free based on the intercepted TRIM or discard communication. Subsequently, the system frees a physical block corresponding to the at least one block in a storage of the host system and reduces a size of the image file for the guest system in accordance with the intercepted TRIM or discard communication.

Abstract: A data storage device which exchanges multi-stream data with a host includes a nonvolatile memory device; a buffer memory configured to temporarily store data to be stored in the nonvolatile memory device or data read from the nonvolatile memory device; and a storage controller configured to receive from the host an access command for accessing segments of the multi-stream data, the accessing including reading the segments of the multi-stream data from or writing the segments of the multi-stream data to the nonvolatile memory device, wherein the storage controller is configured to store the access-requested segments in the buffer memory, the access-requested segments being the segments of data for which access is requested in the access command, the multi-stream data including a plurality of data streams that correspond respectively to a plurality of multi-stream indexes, the first multi-stream index being one of a plurality of multi-stream indexes.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

Abstract: A method includes selectively controlling, at a computing device having a memory, initiation of a full garbage collection operation based on a total resource usage metric and a managed object metric. The managed object metric is based on objects managed by a runtime application.

Abstract: Embodiments disclosed herein provide systems and methods for performing garbage collection in virtual environments. In a particular embodiment, a method provides performing a garbage collection process to identify at least a portion of a secondary storage volume located within a primary storage volume. The method further provides triggering a data block release process on at least a portion of the primary storage volume corresponding to the at least a portion of the secondary storage volume.

Abstract: A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

Abstract: Techniques for universal cache management are described. In an example embodiment, a plurality of caches are allocated, in volatile memory of a computing device, to a plurality of data-processing instances, where each one of the plurality of caches is exclusively allocated to a separate one of the plurality of data-processing instances. A common cache is allocated in the volatile memory of the computing device, where the common cache is shared by the plurality of data-processing instances. Each instance of the plurality of data-processing instances is configured to: identify a data block in the particular cache allocated to that instance, where the data block has not been changed since the data block was last persistently written to one or more storage devices; cause the data block to be stored in the common cache; and remove the data block from the particular cache. Data blocks in the common cache are maintained without being persistently written to the one or more storage devices.

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

Abstract: A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least one application as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application, allocating a cache partition, a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application, defining a threshold value including a number of cache misses per time unit, determining a reduction of cache misses per time unit, in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, assigning a priority of scheduling memory request including a medium priority level, and assigning a memory channel to the at least one application to avoid memory channel contention.

Abstract: Embodiments of systems, method, and apparatuses for remote monitoring are described. In some embodiments, an apparatus includes at least one monitoring circuit to monitor for memory accesses to an address space; at least one a monitoring table to store an identifier of the address space; and a tag directory per core used by the core to track entities that have access to the address space.

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract: An intelligent cache pre-fetch system includes a pre-fetch throttling scheme to monitor a cache hit rate context. Pre-fetch reads of additional data are only launched when the context is below a given threshold. A pre-fetch read of additional data can be selectively initiated after determining that references to neighboring segments related to a compression region already in memory are not yet present in the cache. Additional throttling of pre-fetch reads can be accomplished by only initiating the selective pre-fetch of additional data after determining whether the compression region to which the neighboring segments are related is a hot region, where a hot region is characterized as a compression region having data that is accessed frequently as compared to data in other compression regions.

Abstract: When one of a plurality of storage apparatuses receives an input/output (IO) request in which the address of a logical volume is designated, a cache destination storage device in which I/O data conforming to the received I/O request is to be cached is determined on the basis of a target I/O pattern and/or a coupling mode. The I/O data is cached in the CM area of the cache destination storage device. The target I/O pattern is the one among a plurality of I/O patterns to which an I/O conforming to the received I/O request belongs. Each of the plurality of I/O patterns pertains to whether an I/O destination address in the logical volume is random or sequential. The coupling mode indicates whether or not a storage device that receives an I/O request in which the same address as that designated in the received I/O request is designated has been determined.

Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.

Abstract: A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.

Abstract: Provided are a computer program product, system, and method for considering a density of tracks to destage in groups of tracks to select groups of tracks to destage. Groups of tracks in the cache are scanned to determine whether they are ready to destage. A determination is made as to whether the tracks in one of the groups are ready to destage in response to scanning the tracks in the group. A density for the group is increased in response to determining that the group is not ready to destage. The group is destaged in response to determining that the density of the group exceeds a density threshold.

Abstract: Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.

Abstract: Systems and methods enable initializing and accessing page metadata stored in the last level of a multi-level page table, wherein an effort is made to reduce the number of metadata initializations and the number of page table walks for sequential accesses in comparison with a naïve method realized by a sequence of random accesses.

Abstract: A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.

Abstract: Disclosed aspects relate to memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA). An access relationship is monitored between a set of hardware memory components and a set of software assets. A set of memory affinity data is stored. The set of memory affinity data indicates the access relationship between the set of software assets and the set of hardware memory components. Using the set of memory affinity data, a NUMA utilization configuration with respect to the set of software assets is determined. Based on the NUMA utilization configuration, a set of accesses pertaining to the set of software assets and the set of hardware memory components is executed.

Abstract: A web server cache performs verification of cached computational results by storing a computed function result as a cached value in a cache, and upon receiving a subsequent invocation of the function, examining a duration of the value in the cache. The web server compares, if the duration exceeds a staleness detection threshold, a result of a subsequent execution of the function to the cached value in response to the subsequent invocation by recomputing, a result from execution of the function for validating the cached value, and flags an error if the duration exceeds the staleness detection threshold and the result differs from the cached value. Alternatively, the method returns, if the duration of the cache value is within the staleness detection threshold, the cache value as the result of the subsequent invocation.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, an IVN transceiver is disclosed. The IVN transceiver includes an IVN bus interface, a microcontroller communications interface, and a security module connected between the IVN bus interface and the microcontroller communications interface and configured to perform a security function.

Abstract: Apparatus and method for data security in a data storage environment. In some embodiments, input data from a host is received into a buffer memory. Data compression is applied to the input data to provide compressed data. Encryption is applied to the compressed data to generate encrypted data, and the encrypted data are stored in a main memory of a data storage device. A system parameter value associated with the storage of the encrypted data is generated and stored in a memory, such as the main memory of the storage device. The system parameter value may include information relating to the compression of the data. A trusted relationship is established to authenticate the host responsive to a request for the updated system parameter value. The system parameter value is transferred to the host responsive to the established trusted relationship.

Abstract: Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.

Abstract: Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. These instructions thus do not have to wait for the lock instruction to complete before retiring. In the event that the processor detects a violation of the atomic or fencing properties of the lock instruction prior to committing the value of the lock instruction, the processor rolls back state and executes the lock instruction in a slow mode in which younger instructions are not allowed to retire until the stored value of the lock instruction is committed. Speculative retirement of these instructions results in increased processing speed, as instructions no longer need to wait to retire after execution of a lock instruction.

Abstract: According to one embodiment, a memory controller allows access to a first non-volatile memory from a host device when a wireless communication unit is communicable or communicating with any one of wireless communication devices, and denies access to the first non-volatile memory from the host device when the wireless communication unit is not communicable or communicating with any one of the wireless communication devices. The memory controller does not allow the host device to access information in the first non-volatile memory after the access field specification information is updated.

Abstract: A switch includes a PCI bus. A line card processor is coupled to a line card memory system and includes a line card processor port connected to the PCI bus. A management processor is coupled to a management memory system and includes a management processor port connected to the PCI bus and associated with a register. The management processor retrieves an OS image and stores the OS image in the management memory system. The management processor then configures the register with a mapping between the management memory system and the line card memory system. The management processor then provides a write instruction to write the OS image to an address range included in the management memory system, and the management processor port converts the write instruction using the address mapping such that the OS image is written over the PCI bus to the line card memory system.