Patents Issued in December 11, 2018
-
Patent number: 10152308Abstract: A test interface generator accesses metadata defining a user interface display. The test interface generator generates a strongly typed application programming interface (API) for the user interface display, during compile time, based on the metadata defining the user interface display. A static type checker performs a static type check of each API during compilation of the application. A test system programmatically interacts with the user interface display through the strongly typed API.Type: GrantFiled: May 1, 2015Date of Patent: December 11, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Alexandru Prodan, Jesse S. Bangs, Leo A. Dignan, David S. Froslie, Simon K. Ejsing
-
Patent number: 10152309Abstract: API (application program interface) features defined by a set of APIs provide a different cross-sectional view of an application or framework than the view provided by sectioning along class or library boundaries, or binding units, for example. An API feature includes a proper subset of a library of a framework used by an application, and/or APIs which collectively reside in different libraries. A functionality feature API set provides an exposed surface area of a functionality feature of an application. Upon receiving a compilation request and determining that an API feature is to be excluded, an attempt is made to produce a compiled version of the application without the feature's APIs. In some cases, the functionality feature is independent of a baseline functionality of the application. Developers can obtain smaller but fully functional binaries. Framework architects can identify dependencies between API implementations when creating or modifying a software framework's architecture.Type: GrantFiled: July 27, 2016Date of Patent: December 11, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Mircea Trofin, Krzysztof J. Cwalina, Patrick H. Dussud, John Duffy
-
Patent number: 10152310Abstract: A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.Type: GrantFiled: May 27, 2015Date of Patent: December 11, 2018Assignee: Nvidia CorporationInventors: Mahesh Ravishankar, Paulius Micikevicius, Vinod Grover
-
Patent number: 10152311Abstract: A method for compiling software code comprises scanning call sites within the code to identify a function that is called with at least one constant argument and creating a list of each call site associated with the function and sets of constant arguments passed to the function. If any common subsets of the constant arguments are shared across a plurality of call sites, a size of the function is estimated. selecting any sets of constant arguments that are used only in one call site. The sizes of specialized functions covering sets of constant arguments that are used in only one call site is estimated. The method comprises creating a first set of specialized versions of the function covering one or more sets of constant arguments that are used in only one call site, and if any common subsets of the constant arguments exist, creating a second set of specialized versions of the function.Type: GrantFiled: September 16, 2016Date of Patent: December 11, 2018Assignee: QUALCOMM Innovation Center, Inc.Inventor: Tobias Edler Von Koch
-
Patent number: 10152312Abstract: Compiler techniques for inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.Type: GrantFiled: January 21, 2015Date of Patent: December 11, 2018Assignee: NVIDIA CorporationInventors: Vinod Grover, Thibaut Lutz
-
Patent number: 10152313Abstract: The invention relates to a method for transforming a shared library between two operating systems with different application binary interfaces (ABIs) on a predetermined instruction set architecture. The shared library is implemented by a source object file comprising at least a source memory image, source symbol information, and absolute source relocation information. The method comprises: creating a target object header compliant to the target ABI and comprising information descriptive of the shared library and/or a target object file; creating a target memory image compliant to the target ABI from the source memory image; creating target symbol information compliant to the target ABI from the source symbol information; creating target relocation information compliant to the target ABI from the source relocation information; and writing the target object header, memory image, symbol information, and relocation information to the target object file to implement the transformed shared library.Type: GrantFiled: December 19, 2017Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Frederik J. Hartmann, Ulrich Weigand
-
Patent number: 10152314Abstract: Systems and methods are disclosed for provisioning software in computing networks. For example, methods may include invoking one or more discovery probes; retrieving software usage data based at least on the one or more discovery probes; determining software usage predictions based on the software usage data; allocating, based on the software usage predictions, per user software entitlements and per device software entitlements to obtain an allocation of software entitlements; and invoking installation or uninstallation of software responsive to the allocation of software entitlements.Type: GrantFiled: March 29, 2018Date of Patent: December 11, 2018Assignee: ServiceNow, Inc.Inventors: Apolak Borthakur, Manish Srivastava, Yu Xia
-
Patent number: 10152315Abstract: The invention relates to a method for live rule deployment with a deployment log. The method includes executing rules of a first rules package in response to one or more requests from applications. Also, the method includes receiving an identifier. The identifier is received from a configuration service, and the identifier identifies a location from which a latest rules package can be obtained. The method further includes determining, using the identifier, that a new rules package is available for deployment. Still yet, the method includes, in response to determining that the new rules package is available, requesting, using the location, a second rules package from a rules package manager. Further, the method includes receiving the second rules package from the rules package manager, and replacing the first rules package with the second rules package by deploying the second rules package.Type: GrantFiled: July 27, 2016Date of Patent: December 11, 2018Assignee: Intuit Inc.Inventors: Craig Alan Olague, Ross H. Mills, Gautam Saggar, Nikolas Terani, William Quach
-
Patent number: 10152316Abstract: Embodiments of the present application relate to a method, apparatus, and system for processing an app. The method includes obtaining a plugin identifier, obtaining an app plugin installation package from a server, wherein the app plugin installation package is associated with the plugin identifier, installing the app plugin installation package, obtaining an app plugin lookup instruction associated with an app plugin, and determining the app plugin according to the app plugin lookup instruction, wherein the app plugin implements a specific function of a corresponding app in response to the app plugin being invoked.Type: GrantFiled: December 20, 2016Date of Patent: December 11, 2018Assignee: Alibaba Group Holding LimitedInventors: Chao Xi, Yue Zhang, Huan Zeng
-
Patent number: 10152317Abstract: A method and system are described updating software packages in a storage system. The method includes receiving software packages for upgradation of the software packages of storage arrays from the plurality of storage arrays. Each of the received software packages correspond to a storage array of the plurality of storage arrays. A time window for updating software packages of the one or more storage arrays is identified, based on an average count of input/output operations per second (IOPS) associated with each storage array. Virtual memories are allocated, within the identified time window, to a set of storage arrays from one or more storage arrays, for uploading each of the software packages. The software packages are uploaded in the allocated virtual memories. The software packages of each storage array of the set are simultaneously updated, by receiving each of the software package from the allocated virtual memory of corresponding storage array.Type: GrantFiled: May 30, 2017Date of Patent: December 11, 2018Assignee: WIPRO LIMITEDInventors: Rishav Das, Karanjit Singh
-
Patent number: 10152318Abstract: Systems, methods, and other embodiments associated with introducing a new data structure to an executing application are described. In one embodiment, a method includes executing an application as an executing application to process data of a data structure maintained according to a data model. The example method may also include receiving a new data structure definition of a new data structure to define for the data model. The example method may also include performing impact analysis to determine whether the executing application is capable of processing data of the new data structure. The example method may also include updating the data model to include the new data structure definition to create an updated data model. The example method may also include generating control instructions to instruct the executing application to utilize data from the new data structure according to the updated data model.Type: GrantFiled: January 31, 2017Date of Patent: December 11, 2018Assignee: ORACLE FINANCIAL SERVICES SOFTWARE LIMITEDInventors: Rajaram N. Vadapandeshwara, Seema M. Monteiro, Jesna Jacob, Tara Kant
-
Patent number: 10152319Abstract: Supplemental functionalities may be provided for an executable program via an ontology instance. In some embodiments, a computer program (e.g., an executable program or other computer program) associated with an ontology may be caused to be run. The ontology may include information indicating attributes for a set of applications. An instance of the ontology may be obtained, which may correspond to an application of the set of applications. Based on the ontology instance, supplemental information may be generated for the computer program. The supplemental information may be related to one or more functionalities of the application to be added to the executable program. The supplemental information may be provided as input to the computer program. The supplemental information, at least in part, may cause the one or more functionalities of the application to be made available via the executable program.Type: GrantFiled: June 19, 2017Date of Patent: December 11, 2018Assignee: ReactiveCore LLPInventor: Michel Dufresne
-
Patent number: 10152320Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the processed results to the external memory.Type: GrantFiled: August 1, 2016Date of Patent: December 11, 2018Assignee: Scientia Sol Mentis AGInventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel
-
Patent number: 10152321Abstract: A processor includes a core to execute an instruction and logic to determine that the instruction will require strided data converted from source data in memory. The strided data is to include corresponding indexed elements from structures in the source data to be loaded into a same register to be used to execute the instruction. The core also includes logic to load source data into preliminary vector registers. The source data is to be unaligned as resident in the vector registers. The core includes logic to apply blend instructions to contents of the preliminary vector registers to cause corresponding indexed elements from the plurality of structures to be loaded into respective interim vector registers, and to apply further blend instructions to contents of the interim vector registers to cause additional indexed elements from the structures to be loaded into respective source vector registers.Type: GrantFiled: December 18, 2015Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Joonmoo Huh
-
Patent number: 10152322Abstract: A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.Type: GrantFiled: August 22, 2016Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Bradly G. Frey, Sanjeev Ghai, Guy L. Guthrie, Cathy May, William J. Starke, Derek E. Williams
-
Patent number: 10152323Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.Type: GrantFiled: October 21, 2016Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Patrice L. Roussel, William W. Macy, Jr., Huy V. Nguyen, Eric L. Debes
-
Patent number: 10152324Abstract: Embodiments of methods and computer program products disclosed herein relate to processor architecture. One such method includes the processor obtaining an instruction. The instruction specifies an operation, and also specifies one of the registers as a source register and one of the registers as a destination register. The method also includes the processor obtaining an endian mode and determining that the instruction is an element-ordering-sensitive instruction. Based on the determination that the instruction is an element-ordering-sensitive instruction, the processor executes the instruction by performing the operation on the elements of the source register in accordance with the endian mode and writing a result of the operation to the destination register.Type: GrantFiled: September 5, 2014Date of Patent: December 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Brett Olsson
-
Patent number: 10152325Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.Type: GrantFiled: February 7, 2017Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Christopher J. Hughes, Changkyu Kim, Daehyun Kim, Victor W. Lee, Jong Soo Park
-
Patent number: 10152326Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.Type: GrantFiled: December 31, 2016Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Kirk S. Yap, Gilbert M. Wolrich, James D. Guilford, Vinodh Gopal, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
-
Patent number: 10152327Abstract: An apparatus for gating a load operation is presented. The apparatus comprises a memory resident data structure, wherein the memory resident data structure is a prediction table comprising a plurality of entries, wherein a matching entry corresponding to the load operation within the prediction table comprises a prediction regarding a dependence of the load operation on a prior aliasing store instruction, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to the prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table, wherein the prediction strength influences a gating of the load operation.Type: GrantFiled: October 25, 2013Date of Patent: December 11, 2018Assignee: INTEL CORPORATIONInventor: Hui Zeng
-
Patent number: 10152328Abstract: One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.Type: GrantFiled: May 31, 2012Date of Patent: December 11, 2018Assignee: NVIDIA CORPORATIONInventors: John R. Nickolls, Lars Nyland, Peter C. Mills, Jeremy Sugerman, Timothy Foley, Brian Fahs, Michael Garland, David P. Luebke
-
Patent number: 10152329Abstract: One embodiment of the present disclosure sets forth an optimized way to execute pre-scheduled replay operations for divergent operations in a parallel processing subsystem. Specifically, a streaming multiprocessor (SM) includes a multi-stage pipeline configured to insert pre-scheduled replay operations into a multi-stage pipeline. A pre-scheduled replay unit detects whether the operation associated with the current instruction is accessing a common resource. If the threads are accessing data which are distributed across multiple cache lines, then the pre-scheduled replay unit inserts pre-scheduled replay operations behind the current instruction. The multi-stage pipeline executes the instruction and the associated pre-scheduled replay operations sequentially. If additional threads remain unserviced after execution of the instruction and the pre-scheduled replay operations, then additional replay operations are inserted via the replay loop, until all threads are serviced.Type: GrantFiled: February 9, 2012Date of Patent: December 11, 2018Assignee: NVIDIA CORPORATIONInventors: Michael Fetterman, Stewart Glenn Carlton, Jack Hilaire Choquette, Shirish Gadre, Olivier Giroux, Douglas J. Hahn, Steven James Heinrich, Eric Lyell Hill, Charles McCarver, Omkar Paranjape, Anjana Rajendran, Rajeshwaran Selvanesan
-
Patent number: 10152330Abstract: The system and method of memory protection using a tagged architecture. The system of memory protection provides a unique tag for each field, within a structure, thus preventing access beyond the structure. The system compares the unique tag, e.g. color, of each field within the structure to the color of the pointer that is used to access the respective structure field. Freed memory is tagged as uninitialized.Type: GrantFiled: September 19, 2016Date of Patent: December 11, 2018Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Silviu S. Chiricescu, Howard B. Reubenstein, Arun Thomas
-
Patent number: 10152331Abstract: A non-transitory computer-readable storage medium storing a set of instructions executable by a processor, the set of instructions, when executed by the processor, causing the processor to perform operations including mapping a memory area storing a segment of code for a kernel of the system during an initialization time of a system. The operations also include executing the segment of code during the initialization time. The operations also include unmapping a portion of the memory area for the kernel after the segment of code has been executed.Type: GrantFiled: May 16, 2014Date of Patent: December 11, 2018Assignee: WIND RIVER SYSTEMS, INC.Inventors: Surya Satyavolu, Thierry Preyssler
-
Patent number: 10152332Abstract: A printer driver and an advanced UI application are associated with each other during installation, and the advanced UI application is activated in a different process using a COM when the printer driver is called.Type: GrantFiled: September 7, 2017Date of Patent: December 11, 2018Assignee: CANON KABUSHIKI KAISHAInventor: Akihiro Mitsui
-
Patent number: 10152333Abstract: [SUBJECTS] In a network boot system having a read cache mechanism, the subject is to suppress a decreased boot time of a terminal due to an access with respect to a local disk. [SOLVING MEANS] Network boot system 100 includes server 10 and terminal 20 having recording device 22a connecting each other through network 30. The terminal includes a read cache mechanism that stores a cache in a read cache region by a read cache driver. The read cache mechanism includes a mapping table that indicates an address of the read cache region corresponding to an address of data that was at a reading time from the server, a means that sequentially and in order stores the data that was at the reading time from the server from a top side, a means that stores the address with respect to the cache, and when using the cache data, the read cache mechanism accesses the address of the read cache region based on the mapping table.Type: GrantFiled: February 26, 2013Date of Patent: December 11, 2018Assignee: CO-CONV, CORP.Inventor: Shin Maruyama
-
Patent number: 10152334Abstract: In a network boot system 100, a network boot server and a terminal 20a are connected through a network 30, the network boot server providing a disk image as a virtual disk 22a that includes an operating system operating on the terminal, the terminal 20a being provided with a physical storage device 21a. The operating system is provided with a read cache mechanism that stores data read from the server as cache data in the storage device. Further, the read cache mechanism is provided with generation management data for generation-managing a transition of revision that represents revise information of the virtual disk. The generation management data is divided for each transition of the revision and stored in the server and a copy of at least one division of the divided generation management data is also stored in the storage device.Type: GrantFiled: July 8, 2013Date of Patent: December 11, 2018Assignee: CO-CONV, CORP.Inventor: Shin Maruyama
-
Patent number: 10152335Abstract: Methods and apparatus relating to seamless host system gesture experience for guest applications on touch based devices are described. In an embodiment, Host Gesture Capture (HGC) logic detects a gesture in response to a touch event. The HGC logic forwards the gesture to Host Gesture Emulator (HGE) logic in response to a determination that the gesture is unrelated to an operation of a host system. The HGE logic operates in accordance with a guest operating system of the host system. Other embodiments are also claimed and described.Type: GrantFiled: November 15, 2013Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Yihua Jin, Jianhui Li, Tingtao Li, Xiaodong Lin
-
Patent number: 10152336Abstract: Technologies for managing sensor conflicts in a compute system include determining an implication of stimuli sensed by two or more sensors of the compute system and determining whether a conflict exists between the determined implications. If a conflict does exist, an amount of discomfort is applied to the compute device. For example, a performance characteristic of the compute device may be adversely impacted based on the determined conflict. In some embodiments, the level of applied discomfort is based on a magnitude, importance, and/or duration of the implication conflict.Type: GrantFiled: December 26, 2015Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Tobias M. Kohlenberg, Brian D. Johnson, John C. Weast
-
Patent number: 10152337Abstract: Embodiments relate to data shuffling by logically rotating processing nodes. The nodes are logically arranged in a two or three dimensional matrix. Every time two of the nodes in adjacent rows of the matrix are aligned, adjacent nodes exchange data. The positional alignment is a logical alignment of the nodes. The nodes are logically arranged and rotated, and data is exchanged in response to the logical rotation.Type: GrantFiled: August 12, 2016Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Ronald J. Barber, Robert S. Germain, Guy M. Lohman, Rene Mueller, Ippokratis Pandis, Vijayshankar Raman
-
Patent number: 10152338Abstract: Optimizations are provided for sibling calls. A sibling caller is marked to indicate that it may call a sibling routine or that it may call an external sibling routine. Based on the marking, certain processing is performed to facilitate use of sibling calls, particularly when the sibling routine being called is external to the caller.Type: GrantFiled: December 14, 2016Date of Patent: December 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Michael K. Gschwind
-
Patent number: 10152339Abstract: Methods and apparatus for receiving a selection of disks in a storage system for simulation in a simulator of a server cache application, receiving simulation parameters, running a simulation for the disk selection, and examining results of the simulation. After examination of the results, simulation parameters can be adjusted and the simulation re-run for a disk selection.Type: GrantFiled: June 25, 2014Date of Patent: December 11, 2018Assignee: EMC IP HOLDING COMPANY LLCInventors: Xin Dong, Gerald Cotter
-
Patent number: 10152340Abstract: In a computer-implemented method for configuring flash cache for input/output operations to a storage device by a plurality of virtual machines an input/output trace log for each of a plurality of virtual machines is accessed. Performance of each of the plurality of virtual machines based on a plurality of configurations of the flash cache is simulated in real-time. A recommendation of the plurality of configurations of the flash cache for the each of the plurality of virtual machines utilizing results from the simulation is generated.Type: GrantFiled: March 7, 2014Date of Patent: December 11, 2018Assignee: VMware, Inc.Inventors: Sankaran Sivathanu, Niti Khadapkar, Yifan Wang, Tariq Magdon-Ismail, Dilip Patharachalam
-
Patent number: 10152341Abstract: A system and method for hyper-threading based host-guest communication includes storing, by a guest, at least one request on a shared memory. A physical processor, in communication with the shared memory, includes a first hyper-thread and a second hyper-thread. The method also includes starting, by a hypervisor, execution of a VCPU on the first hyper-thread and sending a first interrupt to the second hyper-thread to signal a request to execute a slave task on the second hyper-thread. The slave task includes an instruction to poll the shared memory. The method further includes executing, by the second hyper-thread, the slave task on the second hyper-thread and executing the at least one request stored on the shared memory.Type: GrantFiled: August 30, 2016Date of Patent: December 11, 2018Assignee: Red Hat Israel, Ltd.Inventor: Michael Tsirkin
-
Patent number: 10152342Abstract: Techniques are disclosed for allowing a virtual application and a virtual desktop to interact. In one embodiment, the virtual application is moved inside the virtual desktop to eliminate the need to switch between user interfaces for the virtual desktop and for the virtual application. In response to a user dragging the user interface of a first virtual desktop interface (VDI) client connected to the virtual application into the user interface of a second VDI client connected to the virtual desktop, information is collected about a first virtual machine (VM) in which the virtual application runs, and the information is transmitted to the second VDI client. The second VDI client passes such information via a virtual channel to a second VM in which the virtual desktop runs, and a remote launcher in the second VM launches a third VDI client that connects to the first VM based on the information.Type: GrantFiled: June 30, 2015Date of Patent: December 11, 2018Assignee: VMware, Inc.Inventors: Jinxing Hu, Jian Mu
-
Patent number: 10152343Abstract: In example implementations, when a management program deploys new virtual machines, the management program may identify candidate virtual machines for replacement, score the possibilities of replacement and relate the new virtual machines to candidate virtual machines if it determines the probability of replacement is high. The management program may also migrate virtual machines and storage volumes used by the virtual machines to other physical servers and storage arrays by related pairs of virtual machines. The management program may also inherit management policies from existing virtual machines being replaced and leverage them to manage new virtual machines, which replace the existing virtual machines.Type: GrantFiled: August 13, 2014Date of Patent: December 11, 2018Assignee: HITACHI, LTD.Inventor: Yasutaka Kono
-
Patent number: 10152344Abstract: A mechanism for managing virtual machines in a virtualization system is disclosed. A method of implementation of the disclosure includes receiving a request from a client system to route network traffic from a first network interface card (NIC) of a first host system to a virtual machine. A determination may be made as to whether network traffic to another virtual machine is routed through the first NIC of the first host system. A notification may be sent to the client system indicating that the network traffic to the other virtual machine is routed through the first NIC and identifying a second NIC of a second host system that is available. The second NIC may be associated with the virtual machine to route network traffic from the second NIC to the virtual machine.Type: GrantFiled: August 18, 2016Date of Patent: December 11, 2018Assignee: Red Hat Israel, Ltd.Inventors: Alona Kaplan, Michael Kolesnik
-
Patent number: 10152345Abstract: Examples perform creation of a non-persistent virtual machine with a persistent machine identity associated with the user of the virtual machine, to provide consistent virtual desktop sessions to the user. Some examples contemplate that the machine identity is inserted into a virtual machine created through cloning, forking, or from a virtual machine pool.Type: GrantFiled: November 21, 2016Date of Patent: December 11, 2018Assignee: VMware, Inc.Inventor: Daniel James Beveridge
-
Patent number: 10152346Abstract: A computer located outside of an organizational computing environment is remotely prepared and configured to work in the organizational computing environment. A hypervisor operating system is installed and replaces the primary operating system of the computer, and the primary operating system, virtual software appliances (VSA) and virtual machines (VM) can execute as processes of the hypervisor. The hypervisor is configured to establish secure connection with organizational computing environment and to receive from it organization-configured image software for configuring the compute to work in the organizational computing environment. The secure connection can also be used for remote maintenance of the computer even when the computer operating system is faulty or inactive.Type: GrantFiled: January 20, 2017Date of Patent: December 11, 2018Assignee: INTEL CORPORATIONInventor: Etay Bogner
-
Patent number: 10152347Abstract: Managing a cloud computing environment including a plurality of resources adapted to host at least one virtual machine includes, in a virtual machine, determining a period of inactivity of the operating system for a user of the virtual machine and comparing, using a processor, the period with a defined threshold. From the virtual machine, a virtual machine termination request is sent to the cloud computing environment responsive to the period exceeding the defined threshold.Type: GrantFiled: November 25, 2017Date of Patent: December 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Jean-Yves B. Rigolet
-
Patent number: 10152348Abstract: A job for which execution is requested is classified as one of classes. The amount of data to be written into a non-volatile storage device by execution of the job for which execution is requested is acquired. The efficiency index is calculated for each of the classes based on an execution evaluation value of the class and the amount of data to be written into the non-volatile storage device by execution of at least one job that has been already classified as the class. From among the classes, a class having an efficiency index of no greater than an efficiency threshold value is determined as the execution suspending class. When the job for which execution is requested belongs to the execution suspending class, execution of the job is suspended.Type: GrantFiled: November 21, 2016Date of Patent: December 11, 2018Assignee: KYOCERA Document Solutions Inc.Inventor: Tomoki Oyasato
-
Patent number: 10152349Abstract: A device may receive information that identifies a set of tasks to be executed and precedence constraints associated with the set of tasks. The device may store the set of tasks in a data structure including a directed acyclic graph, and may determine a set of paths based on the information that identifies the set of tasks and the precedence constraints associated with the set of tasks. Each path, of the set of paths, may include particular tasks of the set of tasks. The device may determine a set of path execution times, for the set of paths, based on an artificial intelligence technique. The device may determine a critical path, of the set of paths, based on the set of path execution times. The device may determine an execution priority of the set of tasks based on the critical path. The device may provide the set of tasks for execution based on the execution priority.Type: GrantFiled: September 27, 2016Date of Patent: December 11, 2018Assignee: Juniper Networks, Inc.Inventor: Ajay Anand
-
Patent number: 10152350Abstract: Particular embodiments described herein provide for an electronic device that can be configured to determine that a secure domain has been created on a device, where keys are required to access the secure domain, obtain the keys that are required to access the secure domain from a network element, and encrypt the keys and store the encrypted keys on the device. In an example, only the secure domain can decrypt the encrypted keys and the device is a virtual machine.Type: GrantFiled: July 1, 2016Date of Patent: December 11, 2018Assignee: Intel CorporationInventors: Somnath Chakrabarti, Mona Vij, Carlos V. Rozas, Brandon Baker, Vincent R. Scarlata, Francis X. McKeen, Simon P. Johnson
-
Patent number: 10152351Abstract: In various embodiments, methods and systems, for implementing proxy objects are provided. A task request directed to a driver component is intercepted at a proxy object component. The task request is an Input/Output or a session task. A proxy object is generated for the task request at the proxy object component. The task request is communicated from the proxy object component to the driver component. A modification indication to modify the driver component is received. A standby mode is initiated at the proxy object component and the driver component, the standby mode comprises processing task requests and proxy objects based on standby operations. A determination that the driver component has been modified to a modified version of the driver component is made. A recovery mode is initiated at the proxy object component and the driver component, the recovery mode comprises processing task requests and proxy objects based on recovery operations.Type: GrantFiled: February 1, 2016Date of Patent: December 11, 2018Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventor: Forrest Curtis Foltz
-
Patent number: 10152352Abstract: Devices, systems and methods are provided for writing, by a plurality of computing resources, to contiguous memory addresses of memory that supports random access, without having to specify actual write addresses of the memory.Type: GrantFiled: November 17, 2015Date of Patent: December 11, 2018Assignee: Friday Harbor LLCInventors: Andy White, Doug Meyer
-
Patent number: 10152353Abstract: The present disclosure discloses system resource allocating method and device based on account activity level, wherein the method includes: acquiring an account activity level parameter of a user and calculating an account activity level of each user according to the account activity level parameter of the user; determining an account activity level rank of each user according to the account activity level of the user and a preset account activity level rank dividing manner; establishing an account activity level index of each user according to a user number, the account activity level and the account activity level rank of the user; allocating the system resource for performing the information processing to a target user according to the account activity level index of the target user, where the information processing is to be performed on the target user.Type: GrantFiled: December 22, 2016Date of Patent: December 11, 2018Assignee: China Construction Bank CorporationInventors: Jinxin Zhao, Kezun Liang, Wei Wang, Shunhua Zhang, Liqiang Hu, Xiaoyu Xie, Yinghui Lu, Nan Wang, Ran Tao, Shusheng Chen
-
Patent number: 10152354Abstract: To schedule a software thread for execution on a CPU in a multiprocessor system, a scheduler uses both software and hardware utilization information. For a thread, resource demands (including software and hardware resource demands) are determined based on measuring resource usage while the thread executes on the multiprocessor system without being isolated from any other threads that may run concurrently. For at least two processor cores, resource usage is calculated based on any threads already running on it. The software thread is assigned to a strand in the processor core with optimum available resources given the thread's resource demands.Type: GrantFiled: February 28, 2017Date of Patent: December 11, 2018Assignee: Oracle International CorporationInventors: Jonathan Chew, Nicolas Michael, Junsang Cho
-
Patent number: 10152355Abstract: A system and method for managing licensed and non-licensed resources in a grid network is provided. A license server receives and processes requests for a license and determines whether a license is available and, if necessary, causes a new configuration to be created on a server for satisfying the request. A new grid node may also be created and configured to be added to the grid for creating additional capacity for grid processing. The configuration may be performed at a time prior to an actual need by the grid, perhaps due to a faulted node, and quickly brought on-line with a simple configuration update. The new grid node may also have a virtual IP address reassigned to quickly redirect processing from the faulted node to the newly configured node. Also, an external resource dispatcher may add new resources such as storage or processing capacity to the grid and may coordinate the new resources with the license server.Type: GrantFiled: October 5, 2010Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Matthew B. Trevathan, Seth Chisamore, Christopher E. Holladay, Michael P. Outlaw
-
Patent number: 10152356Abstract: Methods and apparatus to customize deployment using metaproperties are disclosed. An example deployment metaproperty manager can generate a first metaproperty payload including an initial application component metaproperty of an application component that provides a logical template of an application. A deployment event broker can reply-back to the deployment metaproperty manager with a second metaproperty payload that includes a processed application component metaproperty.Type: GrantFiled: December 7, 2016Date of Patent: December 11, 2018Assignee: VMware, Inc.Inventors: Ventsyslav Raikov, Lazarin Lazarov, Boris Savov, Rostislav Georgiev
-
Patent number: 10152357Abstract: A method includes selecting a given hardware configuration for a given application workload based on aligning an application workload specification template with a first hardware configuration template in a repository comprising a plurality of hardware configuration templates, the application workload specification template being generated by parsing and interpreting hardware-agnostic service level objective expressions of an application request.Type: GrantFiled: July 27, 2016Date of Patent: December 11, 2018Assignee: EMC IP Holding Company LLCInventors: James Espy, Robert A. Lincourt, Jr., Susan Young