Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

Abstract: A mechanism is provided for managing memory of a runtime environment executing on a virtual machine. A balloon agent that is part of a runtime environment is configured to coordinate inflations of a memory balloon within a heap of” the runtime environment and an out-of-heap overflow balloon, particularly in situations where a hypervisor needs to reclaim more memory from the runtime environment than the runtime environment is able to give up. The balloon agent may slowly free out-of-heap balloon memory, which may cause an increase of a target size for the balloon agent, which in turn inflates the memory balloon inside the heap of the runtime environment.

Abstract: Technologies are generally described manage MRAM cache writes in processors. In some examples, when a write request is received with data to be stored in an MRAM cache, the data may be evaluated to determine whether the data is to be further processed. In response to a determination that the data is to be further processed, the data may be stored in a write cache associated with the MRAM cache. In response to a determination that the data is not to be further processed, the data may be stored in the MRAM cache.

Abstract: In a method for allocating data to multiple disks for storage, a capability value of each of the multiple disks is obtained. The capability value is ratio of a performance indicator value of a disk to a maximum capacity value of the disk. A greatest capability value is identified from multiple capability value. Based on the greatest capability value and a maximum capacity value of each of the multiple disks, allocation shares of the multiple disks are determined. Based on the determined allocation shares, data is allocated for the multiple disks. Through the method, the overall storage performance of a storage system is improved.

Abstract: Techniques herein are for chaining nonvolatile storage devices to achieve high availability. A method involves a storage server receiving a write request to store data blocks in a first nonvolatile memory device. The storage server comprises a plurality of nonvolatile memory devices that cache data blocks stored on primary storage. The plurality of nonvolatile memory devices comprises the first nonvolatile memory device. The storage server maintains a cache index of data blocks that reside in the plurality of nonvolatile memory devices. Based on one or more criteria, the storage server reroutes the write request to a second nonvolatile memory device of the plurality of nonvolatile memory devices and stores an identifier of the second nonvolatile memory device in the cache index.

Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.

Abstract: Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a termination device during a memory device operation on a memory device of the plurality of memory devices corresponding to a particular address of the memory system, wherein appointing the particular memory device to act as a termination device comprises storing termination information in the particular memory device corresponding to the particular address.

Abstract: Techniques for backing up application-consistent data using asynchronous replication are disclosed. In one particular embodiment, the techniques may be realized as a method for backing up application-consistent data comprising receiving a backup request to backup application data and storing the application data in a volume of storage space. The method may also comprise taking a snapshot of the application data stored in the volume of storage space and quiescing, via a quiescing module comprising at least one computer processor, the snapshot of the application data stored in the volume of storage space. The method further comprise transmitting application-consistent data, wherein the application-consistent data may comprise the application data stored in the volume of storage space and the quiesced snapshot of the application data stored in the volume of storage space.

Abstract: Disclosed herein are a buffer cache apparatus, a journaling file system, and a journaling method capable of incorporating journaling features based on nonvolatile memory. The buffer cache apparatus provides a data buffering function between a central processing unit (CPU) and storage. The buffer cache apparatus includes a plurality of cache blocks and a journal management unit. The plurality of cache blocks are configured as volatile or nonvolatile memory devices. The journal management unit maintains states of freezing for write-protecting dirty up-to-date cache blocks among the plurality of cache blocks.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric. In response to a first cache memory snooping on the interconnect fabric a request of an interconnect operation of a second cache memory, the first cache memory allocates a snoop machine to service the request. Responsive to the snoop machine completing its processing of the request and prior to the first cache memory receiving a systemwide coherence response of the interconnect operation, the first cache memory allocates an entry in a data structure to handle completion of processing for the interconnection operation and deallocates the snoop machine. The entry of the data structure protects transfer of coherence ownership of a target cache line from the first cache memory to the second cache memory during a protection window extending at least until the systemwide coherence response is received.

Abstract: Throttling instruction execution in a transaction operating in a processor configured to execute memory instructions out-of-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory is provided. Included is executing, by the processor, instructions of a transaction comprising determining whether the transaction is in throttling mode and based on the transaction being in throttling mode, executing memory instructions in-program-order. Also included is based on the transaction not-being in throttling mode, executing memory instructions out-of-program order.

Abstract: Preventing a prefetch memory operation from causing a transaction to abort by receiving by a local processor a prefetch request from a remote processor. Determining whether the prefetch request conflicts with a transaction of the local processor. Responding to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction of the local processor, by providing a requested prefetch data. Responding to a determination that the prefetch request conflicts with a transaction of the local processor by determining an evaluation of the prefetch request. Performing at least one of i) an abort of the prefetch request, ii) a quiesce the prefetch request, iii) a delay in the processing of the prefetch request for a delay period, and iv) an execution of the prefetch request based on the evaluation the prefetch request.

Abstract: A multi-way set associative cache and a processing method thereof, where the cache includes M pipelines, a controller, and a data memory, where any one of the pipelines includes an arbitration circuit, a tag memory, and a determining circuit, where the arbitration circuit receives at least one lookup request at an Nth moment, and determines a first lookup request among the at least one lookup request, the tag memory looks up locally stored tag information according to a first index address in order to acquire at least one target tag address corresponding to the first index address, the determining circuit determines whether an address that matches a first tag address exists in the at least one target tag address, and the controller sends the first lookup request to a next-level device or other pipelines for processing when the address that matches the first tag address does not exist.

Abstract: In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.

Abstract: A method of adjusting asynchronous cache operations on a cache device includes accessing the cache device each cache window having a plurality of cache blocks, and each cache block having corresponding metadata indicating a status of the cache block. The method also includes receiving, at a first cache block, a first input/output operation and updating a first metadata of the first cache block, the first metadata being marked as dirty. The method also includes receiving, at a second cache block, a second input/output operation and updating a second metadata of the second cache block, the second metadata being marked as dirty. The method also includes grouping, in a page, the first and second input/output operations and updating, in a single operation according to the page, the first and second cache blocks according to the first and second input/output operations. The first and second metadata are then marked as non-dirty.

Abstract: The population of data to be admitted into secondary data storage cache of a data storage system is controlled by determining heat metrics of data of the data storage system. If candidate data is submitted for admission into the secondary cache, data is selected to tentatively be evicted from the secondary cache; candidate data provided to the secondary data storage cache is rejected if its heat metric is less than the heat metric of the tentatively evicted data; and candidate data submitted for admission to the secondary data storage cache is admitted if its heat metric is equal to or greater than the heat metric of the tentatively evicted data.

Abstract: A method, computer program product, and computing system for reducing write operations on a flash-based cache memory system includes writing user data to a flash-based cache memory system. Initial status metadata concerning the user data is written to a RAM-based memory system. The user data is written to a backend storage system. Mapping metadata concerning the user data is written to the flash-based cache memory system.

Abstract: A processing system selects entries for eviction at one cache based at least in part on the validity status of corresponding entries at a different cache. The processing system includes a memory hierarchy having at least two caches, a higher level cache and a lower level cache. The lower level cache monitors which locations of the higher level cache have been indicated as invalid and, when selecting an entry of the lower level cache for eviction to the higher level cache, selects the entry based at least in part on whether the selected cache entry will be stored at an invalid cache line of the higher level cache.

Abstract: A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.

Abstract: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

Abstract: A service level is assigned to each application that uses virtual memory. The service level is used to select a type of memory used when paging-in data. The service level is used to select a type of storage used when paging out data. The service level is used to select a page to evict from memory, e.g. based on service level probabilities. The service level is used to select a number of contiguous pages to page-in, e.g. based on a service level scalar. Accesses (hits) to the pages in memory may be tracked, including contiguous pages that are paged-in based on the scalar. Pages with low hit frequency may be evicted. The scalar for an application may be adjusted when at least some of the contiguous pages are infrequently accessed.

Abstract: A query for data stored in a database that includes a set of segments is received at a computer system. The set of segments are divided into a plurality of columns and at least one column of the plurality of columns includes one or more fields. The system analyzes the query to determine fields required to be retrieved from the database. The system determines whether a required field of the query is located in a main memory of the computer system. The system creates an input/output request for a column containing the required field for a plurality of segments of the set of segments prior to executing the query.

Abstract: A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g., read/write/execute) operations. The computing device encodes the indirect address using metadata and a cryptographic algorithm. The metadata may be stored in an unused portion of the indirect address.

Abstract: A system and process of adjusting units coupled to a control element which includes, installing the unit at a selected location. A parameter can be entered from a displaced user operable device. The unit can be directed to carry out a selected function. Performance can be evaluated whether an additional parameter alteration is required based on a predetermined criterion.

Abstract: A support information provisioning system a support device, an external device; and a customer device. The customer device includes an external connector and a remote access controller device that is coupled to the external connector. In situations where the customer device is experiencing at least one customer device issue that prevents the customer device from provisioning support information related to the operation of the customer device, the remote access controller device operates to detect that the external device has been connected to the external connector and, in response, automatically cause new support information about that customer device to be generated. When the external device is subsequently connected to the support device, it may then provide that new support information to the support device for analysis.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.

Abstract: A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: A semiconductor device in which, in principle, plural interrupt request signals can be inputted to a single interrupt terminal is provided. In the semiconductor device, peripheral devices output interrupt request signals of mutually different waveforms. When an interrupt request signal outputted from one of the peripheral devices is received, a microcomputer unit identifies the one of the peripheral devices based on the waveform of the received interrupt request signal. When an interrupt request signal is outputted from any one of the peripheral devices, the interrupt request signal is also inputted to the other ones of the peripheral devices. When one of the peripheral devices receives an interrupt request signal outputted from another one of the peripheral devices, the one of the peripheral devices can output an interrupt request signal of its own only after elapse of a predetermined output inhibition time.

Abstract: A system includes a single wire communications bus, a first slave device, and a second slave device. The first slave device and the second slave device each include a plurality of pins. The first slave device and the second slave device are uniquely identified on the single wire communications bus based on which one of the plurality of pins is coupled to the single wire communications bus.

Abstract: Peripheral apparatus for use with a host computer includes an add-on device, which includes a first network port coupled to one end of a packet communication link and add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data. A network interface controller (NIC) includes a host bus interface, configured for connection to the host bus of the host computer and a second network port, coupled to the other end of the packet communication link. Packet processing logic in the NIC is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the resources of the host computer.

Abstract: In one general aspect, a method can include determining an orientation of a plug inserted into a connector included in the computing device, providing a plurality of display data signals to a reordering switch included in the computing device, selecting, by the reordering switch and based on the determined orientation of the plug, a display data signal from the plurality of display data signals, providing the selected display data signal to at least one of a plurality of multiplexers, the plurality of multiplexers being orientated back-to-back, providing a data signal to the at least one of the plurality of multiplexers, enabling the at least one of the plurality of multiplexers, selecting the display data signal for output by the at least one of the plurality of multiplexers, and providing the selected display data signal to a contact included on the connector.

Abstract: A solid state drive (SSD) device includes a Peripheral Component Interconnect-Express (PCIe) interface, a non-volatile storage media, and a memory that stores code, the code including an Advanced Host Controller Interface (AHCI) controller, and a Non-Volatile Memory-Express (NVMe) controller. The SSD device is operable to select one of the AHCI controller and the NVMe controller to process data storage commands between the PCIe interface and the non-volatile storage media.

Abstract: Information is provided to a source device during link training regarding the state of a remote link when an intermediate device using a different protocol is connected between source and sink devices. The intermediate device includes two controllers connected by a cable, the first controller being connected to the source device and the second controller being connected to the sink device. State information regarding the remote device may be provided by a state machine that stores data to a register on the intermediate device. Based on the state of the remote link, the source device is able to generate a representation of the end to end link between the source and sink device, and to perform link training accordingly.

Abstract: A semiconductor die assembled in a wafer-level package includes a processing circuit, a multiplexer, and a transmit interface. The processing circuit generates a plurality of signal outputs. The multiplexer multiplexes the signal outputs into a multiplexed signal. The transmit interface transmits the multiplexed signal to another semiconductor die assembled in the wafer-level package.

Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

Abstract: A Universal Serial Bus (USB) converter circuit includes: a High Definition Multimedia Interface (HDMI) transceiver circuit, a signal converting circuit and a USB receptacle, wherein the HDMI transceiver circuit arranged to transmit/receive a HDMI signal, wherein the HDMI transceiver circuit includes at least a video signal and a plurality of processing signals; the signal converting circuit coupled to the HDMI transceiver circuit is arranged to execute a converting operation to processing a conversion between the plurality of processing signals and A USB signal; and the USB receptacle coupled to the signal converting circuit includes a USB signal pin and a set of video signal pin, wherein the USB signal is transmitted/received with an electronic device through the USB pin, and the video signal is transmitted/received with the electronic device through the set of video signal pin.

Abstract: Embodiments of a resistor module of a USB interface device and a method for operating a resistor module of a USB interface device are described. In an embodiment, a resistor module of a USB interface device includes a pull-down resistor connectable to a USB power-sourcing device, a switch connected between the pull-down resistor and a fixed reference voltage, an energy storage unit connectable to the USB power-sourcing device and configured to store electrical energy in response to a current from the USB power-sourcing device, a switch control unit connected to the energy storage unit and configured to control the switch with a control signal in response to a voltage of the energy storage unit, and a glitch filter connected to the switch and to the switch control unit and configured to remove a glitch in the control signal. Other embodiments are also described.

Abstract: Methods and apparatus for managing user-defined capacity reservation pools for network-accessible resources are disclosed. A system includes a plurality of resource instances of a provider network, and a resource manager. In response to a pool assignment request from a client specifying a pool identifier of a reserved instance pool created on behalf of the client, the resource manager assigns one or more resource instance reservations of the client to a pool with the first pool identifier. In response to an instance activation request from the client, the resource manager identifies a particular pool created on behalf of the client from which to select a particular resource instance reservation for activation, and activates the particular resource instance.

Abstract: According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

Abstract: Techniques to suppress redundant reads to register addresses and to replicate read data are disclosed. The redundant reads are suppressed when multiple source operands specify the same register address to read. Additionally, the read data is replicated to a data stream or data location corresponding to the source operands where the data read was suppressed.

Abstract: Systems and methods for managing patient information on a primary computer system involving the creation of an electronic patient chart; receiving updated information to the patient chart; and automatically accessing a secondary system based on the updated information. The primary and secondary computer systems communicate to better manage inventory, medical prescriptions and other administrative concerns. When the patient chart is edited by a healthcare professional, the primary computer system evaluates the updated information and then sends requests to one or more secondary systems automatically. The updated information may involve the need for a new medicine for the patient, a new appointment for the patient to be set up, and/or a new bill to be generated for the patient, among others. The secondary system or systems provide back-end management for these requests. Such back-end management occurs relatively automatically and substantially in real time.

Abstract: A method is disclosed for preprocessing a problem involving discrete optimization over a plurality of variables, the method comprising obtaining an indication of a problem involving discrete optimization; converting the problem involving discrete optimization into a problem suitable for a given optimization oracle architecture of an optimization oracle; providing a given number of times M the problem suitable for the given optimization oracle architecture to the optimization oracle; for each providing of the problem, performing a given number K of calls to the optimization oracle; each call generating a given configuration; obtaining a variable selection criterion, the variable selection criterion for determining at least one variable of the plurality of generated configurations that can be fixed; determining at least one variable that matches the variable selection criterion and a corresponding value for each variable; fixing the at least one determined variable at the corresponding value in the problem invo

Abstract: A method for processing data based on 3072-point Fast Fourier Transform (FFT) and a processor based on 3072-point FFT are provided. The method for processing data based on 3072-point FFT includes: storing 3072-point data into a data storage module according to a predetermined mapping relationship (101); reading 16 data in parallel from the data storage module for performing 3-point DFT operation, and storing results into the data storage module in situ after completion of the operation (102); and reading 32 data in parallel from the data storage module for performing 1024-point DFT operation and storing results into the data storage module in situ after completion of the operation until the FFT of 3072-point data is completed (103).

Abstract: A correlation operation circuit includes a first SRAM storing a plurality of pieces of detection pattern data, product-sum operators, a second SRAM storing intermediate data, and a comparator. When time series data is sequentially input, the intermediate data of all correlation functions referring to one time series data in a period during which the one time series data is input. When one time series data is input, the product-sum operator multiplies the detection pattern data sequentially read from the first SRAM by the one input time series data. The corresponding intermediate data is read from the second SRAM in synchronization with the multiplication, and the sequentially-calculated products are cumulatively added to the read intermediate data to be written back into the second SRAM as the intermediate data. As a result, the calculated correlation function data is supplied to the comparator to be compared with a predetermined specified value.

Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.