Patents Issued in January 29, 2019
  • Patent number: 10191799
    Abstract: A memory system is configured to perform a test operation to determine a deviation of a target storage location's bit error rate response relative to a model. The memory system determines the deviation level by measuring data sets stored in the target storage location to determine an actual bit error rate value and another actual parameter value used to estimate bit error rate. The memory system obtains an estimated value from the model based on the actual values and identifies the deviation by comparing the estimated value with the actual values.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 29, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yonatan Karlik, Judah Gamliel Hahn, Ariel Navon, Alex Bazarsky, Ofer Shapira
  • Patent number: 10191800
    Abstract: In one aspect, a method for metric payloads ingestion and playback is disclosed. The method includes receiving time series of metric payloads for a plurality of performance metrics indicating performance of a node or machine and storing the received time series of metric payloads in a payload tracking table of a database. The storing includes storing the received time series of metric payloads in different layers and partitioned regions of the payload tracking table. The layers represent time ranges corresponding to time points when the time series of metric payloads are received. The partitioned regions are assigned to received certain ones of the received time series of metric payloads. The method includes replaying the stored time series of metric payloads from a select one or more of the partitioned region or layer or both.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 29, 2019
    Assignee: Cisco Technology, Inc.
    Inventor: Gautam Borah
  • Patent number: 10191801
    Abstract: Disclosed embodiments include an electronic device having a write-once memory (WOM) and a memory controller. The memory controller includes a host interface receiving a data word including first and second symbols, each having at least two bits, a WOM controller that encodes the first and second symbols and outputs a WOM-encoded word including first and second WOM codes corresponding to the first and second symbols, respectively, an error correction code (ECC) controller that encodes the WOM-encoded word and outputs an ECC-encoded word including the first and second WOM codes and a first set of ECC bits corresponding to a first write operation, and a memory device interface that writes the ECC-encoded word the WOM device in the first write operation. Each of the first and second WOM codes include at least three bits with at least two of the at least three bits having the same logic value.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sai Zhang, Yuming Zhu, Clive Bittlestone, Srinath Ramaswamy
  • Patent number: 10191802
    Abstract: A cloud-based ETL system provides error detection, error correction and reporting of data integration flows hosted by cloud services. Categories of errors are identified using one or more checks at different points of a data integration flow and one or more actions selected based at least in part on the error category. A determination can be made whether the error category is fault tolerant and one or more actions can be selected based at least in part on the error fault tolerance to correct the error, restart a flow, or generate a notification assisting a user to correct the error.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 29, 2019
    Assignee: Oracle International Corporation
    Inventors: Ispati Nautiyal, Rajesh Balu
  • Patent number: 10191803
    Abstract: Disclosed are constructions of WOM codes that combine rewriting and error correction for mitigating the reliability and the endurance problems typically experienced with flash memory. A rewriting model is considered that is of practical interest to flash memory applications where only the second write uses WOM codes. The disclosed WOM code construction is based on binary erasure quantization with LDGM codes, where the rewriting uses message passing and has potential to share the efficient hardware implementations with LDPC codes in practice. The coding scheme achieves the capacity of the rewriting model.
    Type: Grant
    Filed: January 30, 2016
    Date of Patent: January 29, 2019
    Assignee: California Institute of Technology
    Inventors: Eyal En Gad, Wentao Huang, Yue Li, Jehoshua Bruck
  • Patent number: 10191804
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 10191805
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung
  • Patent number: 10191806
    Abstract: In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 29, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Cheng-Che Yang, Kuo-Hsin Lai
  • Patent number: 10191807
    Abstract: The memory system includes a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a write data from a host, a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is a remaining portion of the write data, a plurality of first memory devices suitable for storing first write data and the BCH error correction code, and one or more second memory devices suitable for storing the second write data and the Hamming error correction code.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 29, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung-Eun Lee, Jung-Hyun Kwon, Sang-Gu Jo
  • Patent number: 10191808
    Abstract: Systems and methods providing for storing fragments for one or more source objects at storage nodes of multiple cluster instances comprising a cluster set are disclosed. Repair of the stored data is operated within cluster instances autonomously or semi-autonomously of other cluster instances of the cluster set according to embodiments. Embodiments may provide a storage process operable to generate fragments for a first source object to be stored in a storage system using a first encoding, wherein a different plurality of fragments of the generated fragments are stored at different cluster instances of a cluster set. A repair process may be enacted at each cluster instance of the cluster set, wherein a repair process enacted at a cluster instance is used to maintain the recoverability of the fragments of the first source object stored at that cluster instance using a second encoding.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Michael George Luby
  • Patent number: 10191809
    Abstract: One embodiment provides a method comprising arranging a first data chunk into a ring structure, tagging the first data chunk by appending extra data to the first data chunk, and performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventor: Zhenxing Han
  • Patent number: 10191810
    Abstract: A mobile terminal and related repair method is disclosed. The method includes: obtaining current storage integrity information of the mobile terminal; matching the current storage integrity information and original storage integrity information, when the matching fails, connecting to the server, obtaining original system partition document from the server, and repairing the system partition according to the original system partition document.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: January 29, 2019
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Ching-Ho Chan, Hao-Hsiang Hsu
  • Patent number: 10191811
    Abstract: A system of booting a computer in which a pair of boots (or dual boots) is provided in the flash memory of the computer. The first flash boot, also called the primary boot, is activated when the computer is turned on, after the POST (Power on Self-Test). The primary boot determines if a secondary boot is stored in the flash memory of the computer. If the secondary boot is not stored in the flash memory of the computer, the primary boot resumes and the computer is booted using the primary boot. If a secondary boot is stored in the flash memory of the computer, the primary boot resumes and is completed, after which the computer is reset and rebooted using the secondary boot.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: January 29, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chih-Liang Hsu, Wei-Liang Cheng, Ying-Chin Huang
  • Patent number: 10191812
    Abstract: A storage server includes an IO controller, a management controller and physical drives. The IO controller generates multiple metadata updates and writes a cache entry that includes the multiple metadata updates to a first cache in memory of the management controller. The IO controller additionally writes a copy of the cache entry to a second cache in a memory of the IO controller and increments a commit pointer in the first and second caches to indicate that the metadata updates are committed.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 29, 2019
    Assignee: Pavilion Data Systems, Inc.
    Inventors: Suhas Dantkale, Venkeepuram R. Satish, Raghuraman Govindasamy
  • Patent number: 10191813
    Abstract: Persistent storage for a master copy is provided using operation numbers. A master copy can include a persistent key-value store such as a B-tree with references to corresponding data. When provisioning a slave copy, the master copy sends a point-in-time copy of the B-tree to the slave copy, which stores a copy of the B-tree, allocates the necessary space, and updates the references of the B-tree to point to a local storage before the data is transferred. When writing the data to persistent storage, a snapshot created on the master copy is an operation that is replicated to the slave copy. The snapshot is generated using a volume view that includes changes to chunks of data of the master copy since a previous snapshot, as determined using the operation number for the previous snapshot. Data (and metadata) for the snapshot is written to persistent storage while new input/output operations are processed.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 29, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Jianhua Fan, Benjamin Arthur Hawks, Norbert Paul Kusters, Nachiappan Arumugam, Danny Wei, John Luther Guthrie, II
  • Patent number: 10191814
    Abstract: The present disclosure provides a hierarchical storage management system for storing data. A first controller receives a request to migrate a data item to a first storage tier. The data item is associated with at least an initial object ID. The first controller, in response to the request, generates a new object ID and identifies a first record in a data structure, wherein the initial object ID is identical to an object ID of the first record and to a parent object ID of the first record. The first controller replaces the object ID of the first record with the new object ID, creates in the data structure a new record that is associated with the data item, sets an object ID of the new record and a parent object ID of the new record to the initial object ID, and stores the data item to the first storage tier.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nils Haustein, Christian Mueller, Dominic Mueller-Wicke
  • Patent number: 10191815
    Abstract: Techniques to back up a cluster shared volume (CSV) are disclosed. In various embodiments, a snapshot of the cluster shared volume is stored persistently on the cluster shared volume itself. A task to back up a corresponding assigned portion of the snapshot is assigned to each of one or more cluster servers available to participate in backing up the cluster shared volume. The cluster servers have shared access to the snapshot as stored on the cluster shared volume, and each is configured to perform the task assigned to it in parallel with any other cluster servers assigned to back up other portions of the same cluster shared volume snapshot. The respective assigned tasks are monitored to completion.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 29, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Sathyamoorthy Viswanathan, Ajith Gopinath, Kishore Kumar
  • Patent number: 10191816
    Abstract: A storage system according to certain embodiments includes a client-side repository (CSR). The CSR may communicate with a client at a higher data transfer rate than the rate used for communication between the client and secondary storage. During copy operations, for instance, some or all of the data being backed up or otherwise copied to secondary storage is stored in the CSR. During restore operations, copies of the data stored in the CSR is accessed from the CSR instead of from secondary storage, improving performance. Remaining data blocks not stored in the CSR can be restored from secondary storage.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 29, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Manoj Kumar Vijayan, Deepak Raghunath Attarde, Hetalkumar N. Joshi
  • Patent number: 10191817
    Abstract: A computer-implemented method for backing up large distributed scale-out data systems may include (1) identifying a backup job to be performed on a distributed scale-out storage system that presents a unified storage view, (2) determining, in response to the backup job applying to distributed scale-out storage and based on a scope of the backup job, a number of backup systems to deploy for performing the backup job, (3) deploying a plurality of backup systems creating a plurality of backups covering the plurality of data objects by (i) assigning, to each backup system, a subset of data objects within the backup job and (ii) backing up, by the backup system, the subset of data objects assigned to the backup system, and (4) combining the plurality of backups into a unified backup that represents the unified storage view. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 29, 2019
    Assignee: Veritas Technologies LLC
    Inventor: Srineet Sridharan
  • Patent number: 10191818
    Abstract: Various embodiments of systems, computer program products, and methods to replicate data in a distributed environment are described herein. In an aspect, the data from a first persistent storage unit associated with a primary data center is received. Further, at least a part of the received data is determined to be replicated by filtering the data based on one or more predetermined conditions. The determined part of the data is transmitted to replicate in a second persistent storage unit associated with a secondary data center to recover the part of the data during failure of the primary data center.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 29, 2019
    Assignee: SAP SE
    Inventors: Stoyan Boshev, Marc Wirth
  • Patent number: 10191819
    Abstract: A system according to certain aspects may include a client computing device including: a database application configured to output a database file in a primary storage device(s), the database application outputting the database file as a series of application-level blocks; and a data agent configured to divide the database file into a plurality of first blocks having a first granularity larger than a second granularity of the application-level blocks such that each of the first blocks spans a plurality of the application-level blocks. The system may include a secondary storage controller computer(s) configured to: in response to instructions to create a secondary copy of the database file: copy the plurality of first blocks to a secondary storage device(s) to create a secondary copy of the database file; and create a table that provides a mapping between the copied plurality of first blocks and corresponding locations on the secondary storage device(s).
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 29, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Henry Wallace Dornemann, Rahul S. Pawar, Jun H. Ahn
  • Patent number: 10191820
    Abstract: Techniques for virtual proxy based backup of virtual machines in a cluster environment are disclosed. In some embodiments, each of a subset of virtual machines hosted by physical nodes in a cluster environment is configured as a virtual proxy dedicated to backup operations. During backup, data rollover of each virtual machine in the cluster environment that is subjected to backup is performed using a virtual proxy.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 29, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Soumen Acharya, Anupam Chakraborty, Sunil Yadav, Tushar Dethe
  • Patent number: 10191821
    Abstract: Example embodiments respond to input/output (I/O) requests to a storage stack having a hierarchy of layers. In one such embodiment, responsive to an I/O request for data from a higher layer of the stack to a lower of the stack in hierarchy order, a first help response is generated at the lower layer and sent to the higher layer to recover the data. In turn, at the higher layer, it is determined whether a recover mechanism can fulfill the I/O request and, if not, a second help response is generated and sent to a next higher layer in the hierarchy. At the next higher layer, it is determined whether a recovery mechanism can fulfill the I/O request and, if not, a third help response is generated and sent to an even next higher layer in the hierarchy.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 29, 2019
    Assignee: Dell Products, LP
    Inventor: Damon Hsu-Hung
  • Patent number: 10191822
    Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: January 29, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, J. James Tringali, Ely Tsern
  • Patent number: 10191823
    Abstract: A method and system for restoring an original component from a replicated component are provided. The method includes instructing the original component in a first computing environment to boot from a restoration boot disk; synchronizing at least one original disk of the original component with at least one corresponding replicated disk of a replicated component in a second computing environment, wherein the at least one original disk maintains at least an original operating system of the original component, wherein the replicated component is configured to function in place of the original component; receiving a request to restore the original component; and instructing the original component to boot from the at least one original disk, upon determination the at least one original disk and the at least one corresponding replicated disk are consistent.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 29, 2019
    Assignee: CloudEndure Ltd.
    Inventors: Leonid Feinberg, Ofir Ehrlich, Ophir Setter, Roman Zeyde, Sigal Weiner, Eran Weiss
  • Patent number: 10191824
    Abstract: Implementations of this disclosure are directed to systems, devices and methods for implementing a cache data management system. Webserver computers receive cache data requests for data stored at a computer cluster comprising a plurality of master cache data server computers that do not have corresponding slave cache data server computers to store reserve cache data. Proxy computers in communication with the plurality of webserver computers and the computer cluster route the cache data requests from the webserver computers to the computer cluster. Each proxy computer includes a sentinel module to monitor a health of the computer cluster by detecting failures of master cache data server computers and a trask monitor agent to manage the computer cluster.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 29, 2019
    Assignee: MZ IP Holdings, LLC
    Inventors: Eric Liaw, Kevin Xiao, Glen Wong
  • Patent number: 10191825
    Abstract: This disclosure relates generally to device testing, and more particularly to a system and method for testing a device using a light weight device validation (LWDV) protocol. This includes accessing a test script corresponding to a test case testing the device. The test script includes a set of mutually independent primitive executables. The method includes packetizing one or more of the set of primitive executables based on a LWDV protocol. The method further includes transmitting the one or more encoded primitive executables to the device for execution.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: January 29, 2019
    Assignee: WIPRO LIMITED
    Inventors: Souvik Dutta, Debasish Chanda, Swarup Mandal
  • Patent number: 10191826
    Abstract: Methods, systems, and computer readable media for providing an anticipated data integrity check are disclosed. According to one method, the method includes generating a test message including an anticipated data integrity check value (ADICV), wherein the ADICV is computed using at least one value based on at least one expected modification to message data in the test message by at least one system under test (SUT), and sending the test message to the at least one SUT.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: January 29, 2019
    Assignee: KEYSIGHT TECHNOLOGIES SINGAPORE (HOLDINGS) PTE. LTD.
    Inventors: Alon Regev, Noah Steven Gintis
  • Patent number: 10191827
    Abstract: Methods, systems, and computer readable media for utilizing loopback operations to identify a faulty subsystem layer in a multilayered system are disclosed. One method includes executing a plurality of loopback operations at a respective plurality of loopback points positioned among subsystem layers of a multilayered system and detecting a failed loopback operation among the plurality of loopback operations. The method further includes identifying a faulty subsystem layer among the subsystem layers by comparing the failed loopback operation and a previously conducted successful loopback operation corresponding to a preceding subsystem layer that is adjacent to the faulty subsystem layer within the multilayered system.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Edris Abzakh
  • Patent number: 10191828
    Abstract: Methods, apparatus, systems and articles of manufacture to control a monitoring agent are disclosed herein. An example method includes instructing, via a processor, a monitoring agent of a compute node to perform a first monitoring operation associated with a first monitoring level. A second monitoring level is transitioned to in response to the first monitoring operation returning a first result that is within an acceptable threshold. In response to transitioning to the second monitoring level, an access right of a pre-requisite of the first monitoring operation at the compute node is modified without uninstalling the pre-requisite.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: January 29, 2019
    Assignee: VMware, Inc.
    Inventor: Ilan Uriel
  • Patent number: 10191829
    Abstract: According to one embodiment, a semiconductor device includes a memory-transfer control unit that controls data transfer between a memory and a sound unit. A plurality of sound data transfer routes are configured by one memory-transfer control unit and one sound unit. The semiconductor device outputs reproduction sound data via at least one sound data transfer route and acquires at least two pieces of recording sound data on account of one piece of reproduction sound data via at least two sound data transfer routes.
    Type: Grant
    Filed: July 18, 2015
    Date of Patent: January 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hirohiko Ito
  • Patent number: 10191830
    Abstract: Data processing systems according to various embodiments are adapted to process data regarding error evaluation for use in the development of a first user's executive function. In various embodiments, the data processing system displays one or more visual representations of an activity being executed (e.g., incorrectly). The system may indicate to the first user that the activity was, or is being, executed by a second user. The system may then prompt the first user for input regarding the second user's performance. The data processing system may gather and process related data and then use this information to assist the first user in improving the first user's executive function skills. In particular embodiments, the visual representations of the activity may show the execution of one or more errors that the first user made previously when executing the activity.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 29, 2019
    Assignee: EXQ, LLC
    Inventor: Sucheta A. Kamath
  • Patent number: 10191831
    Abstract: An agent inserts one or more hooks into a sub-execution runtime environment that is configured to include a script and/or targeted to include the script. The agent including the one or more hooks monitors a behavior of the sub-execution runtime environment and/or the script. The agent subsequently obtains context information regarding the sub-execution runtime environment and/or the script so that it can control the runtime of at least the sub-execution runtime environment. Related systems, methods, and articles of manufacture are also disclosed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 29, 2019
    Assignee: Cylance Inc.
    Inventor: Derek A. Soeder
  • Patent number: 10191832
    Abstract: Technology related to tools for supporting multi-language software programs is disclosed. In one example of the disclosed technology, a method can be used for testing a user interface of a software product. The method can include receiving a test recording captured using a first build of the software product targeted to a first language. A localized language file corresponding to a second language can be received. The test recording can be played back on a second build of the software product targeted to the second language. The playing back can include finding an equivalent under-test user interface element to a recorded user interface element of the test recording using a hierarchical search of properties in the localized language file. Additionally, the playing back can include performing a recorded action of the test recording on the equivalent under-test user interface element.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 29, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yu Zhang, Xiaohui Wang, Swati Gupta, Michael Eatherly, Chunyan Zhao
  • Patent number: 10191833
    Abstract: A method includes determining a set of shared memory access instructions and execution frequencies and selecting one or more groups of instructions that access a same memory location. The method also includes finding pairs of instructions from each group, for which another access to the same memory location may occur between execution of the instructions in the pair, and estimating a probability that a data race may occur using a time gap between the instructions and the execution frequencies, and generating a list of instruction tuples that include the pair of instructions. The method includes calculating a score for each instruction in the tuples, the score representing a likelihood of triggering a data race by injecting a delay before an instruction. The method includes selecting instructions having a score indicating a lower than a threshold probability that the instruction will comprise a last access of a data race.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 29, 2019
    Assignee: VMWARE, INC.
    Inventors: Bo Chen, Hao Chen
  • Patent number: 10191834
    Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Jungwoo Ha
  • Patent number: 10191835
    Abstract: A method and information processing system facilitate debugging of a multi-threaded application. A control program request associated with at least one thread of a process that has been designated for debugging is generated. The control program request is placed into a memory buffer associated with the thread by the debugger. The memory buffer is passed to a control program. A plurality of memory buffers is monitored. Each memory buffer in the plurality of memory buffers is associated with a different thread of the process. At least one memory buffer in the plurality of memory buffers is determined to include debugging event information from the control program determining. The debugging event information is processed. The processing includes at least one of notifying a user of the debugging event information and generating at least one control program request for a thread associated with the at least one memory buffer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel S. Gritter, MeiHui Wang, Joshua Wisniewski
  • Patent number: 10191836
    Abstract: A method, system, and apparatus are provided for debugging a compiled computer program having one or more variables by generating variable location information for a first variable stored in a CPU register that is parsed from runtime disassembly information for the compiled computer program and used to generate a pattern to search for the first variable in the runtime disassembly information to identify a program address for the first variable that can be used to set a software program watchpoint for the first variable.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 29, 2019
    Assignee: NXP USA, Inc.
    Inventors: Alexandra Dracea, Catalina D. Mitulescu, Daniel D. Popa
  • Patent number: 10191837
    Abstract: An automated end-to-end analysis of customer service requests is disclosed. A core dump is received, wherein the core dump corresponds to a customer service request regarding a crash of a computer system. The core dump is automatically analyzed with a processor to generate analysis results. A graphical representation for display on a graphic user interface of a computer is generate, wherein the graphical representation corresponds to the analysis results for the core dump.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: January 29, 2019
    Assignee: VMware, Inc.
    Inventors: Sowgandh Sunil Gadi, Naveen Prakash Rao, Travis Finch, Ayoob Khan
  • Patent number: 10191838
    Abstract: A method and device for checking influence of deleting a cache file. The method includes: acquiring a program to be checked, and acquiring a click path set and a cache path set corresponding to the program to be checked, in which the click path set includes a plurality of click paths, and the cache path set includes a plurality of cache paths, each click path set corresponds to a cache path; acquiring a cache path to be checked in the cache path set, and deleting a cache file to be checked from the cache path to be checked; according to a click path corresponding to the cache path to be checked, conducting a click simulation on the program to be checked; and according to an operating result of the program to be checked, acquiring the influence of deleting the cache file to be checked.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: January 29, 2019
    Assignee: BEIJING KINGSOFT INTERNET SECURITY SOFTWARE CO., LTD
    Inventors: Jianming Lin, Kangzong Zhang, Nan Zhang, Yong Chen, Ming Xu
  • Patent number: 10191839
    Abstract: To provide a search device with less memory consumption, the search device includes a first associative memory searched with a first search key, a second associative memory searched with a second search key, a concatenated search data generating unit that generates first search information based on hit information including multiple hits in the first associative memory, and a search key generating unit that includes a first key generating unit generating a portion of search data as the first search key and a second search key generating unit generating the first search information and another portion of the search data as the second search key.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeo Miki
  • Patent number: 10191840
    Abstract: A mapping table updating method for a rewritable non-volatile memory module is provided. The method includes: allocating a mapping table storage area for storing a physical address-logical address mapping table in a buffer memory. The method also includes: determining whether a remaining storage space of the mapping table storage area is less than a threshold. If the remaining storage space is less than the threshold, mapping information of the physical address-logical address mapping table stored in the mapping table storage area is updated into at least one logical address-physical address mapping table, and the mapping information of the physical address-logical address mapping table stored in the mapping table storage area is cleared. The method also includes: storing updated mapping information corresponding to a programmed active physical erasing unit into the mapping table storage area.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: January 29, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chang-Han Hsieh
  • Patent number: 10191841
    Abstract: A host device is provided. The host device includes a processor and an interface. The processor generates a physical block address and a solid state disk (SSD) identification code according to a logical block address of an access operation. The interface is coupled to the processor. The processor indicates one of a plurality of SSDs through the interface according to the SSD identification code to access data at the physical block address.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 29, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Xueshi Yang, Ningzhong Miao
  • Patent number: 10191842
    Abstract: An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 29, 2019
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Kumar Ganapathy, Kenneth Alan Okin, Rajesh Parekh
  • Patent number: 10191843
    Abstract: The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventor: David A. Palmer
  • Patent number: 10191844
    Abstract: The system identifies objects that cause thrashing behavior in garbage collection. A garbage collection process may be monitored for a period of time. Over that period of time, a number of objects may be observed to be collected by the garbage collection process. Data may be collected for those objects and a subset of those objects may be determined to be suspicious based on data collected for each object. The suspicious objects may then be reported as causing garbage collection thrashing.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: January 29, 2019
    Assignee: Cisco Technology, Inc.
    Inventor: Vinay Srinivasaiah
  • Patent number: 10191845
    Abstract: Techniques are disclosed for identifying data streams in a processor that are likely to and not likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization are deprioritized. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level, prefetch utilization, and memory resource utilization.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bernard C. Drerup, Richard J. Eickemeyer, Guy L. Guthrie, Mohit Karve, George W. Rohrbaugh, III, Brian W. Thompto
  • Patent number: 10191846
    Abstract: According to an embodiment, a cache unit includes: a first memory configured to temporarily hold data and an address of the data, a second memory configured to temporarily hold an address of particular data set in advance, and a controller configured to, when an instruction to load the data is made for a first specified address, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: January 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Seiji Maeda
  • Patent number: 10191847
    Abstract: Techniques are disclosed for identifying data streams in a processor that are likely to and not likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization are deprioritized. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level, prefetch utilization, and memory resource utilization.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bernard C. Drerup, Richard J. Eickemeyer, Guy L. Guthrie, Mohit Karve, George W. Rohrbaugh, III, Brian W. Thompto
  • Patent number: 10191848
    Abstract: The present invention provides a method and system for caching time series data. A computer system for caching time series data is disclosed. The computer system comprises one or more processors, at least one cache, and a computer readable storage medium. The computer readable storage medium contains instructions that, when executed by the one or more processors, causes the one or more processors to perform a set of steps comprising fetching the time series data from a time series data source, calculating one or more expiry timestamps, grouping the plurality of time series datum in to one or more time data chunks based on the one or more expiry timestamps, and storing a copy of the time series data and the one or more expiry timestamps in the at least one cache.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 29, 2019
    Assignee: InMobi PTE Ltd.
    Inventor: Arvind Jayaprakash