Abstract: A cache is sized using an ordered data structure having data elements that represent different target locations of input-output operations (IOs), and are sorted according to an access recency parameter. The cache sizing method includes continually updating the ordered data structure to arrange the data elements in the order of the access recency parameter as new IOs are issued, and setting a size of the cache based on the access recency parameters of the data elements in the ordered data structure. The ordered data structure includes a plurality of ranked ring buffers, each having a pointer that indicates a start position of the ring buffer. The updating of the ordered data structure in response to a new IO includes updating one position in at least one ring buffer and at least one pointer.

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

Abstract: The present invention discloses a method for distributed transaction processing in a flash memory, including the following steps: S1. performing two-phase commit on a transaction, removing a state log record of a two-phase commit protocol, and internalizing as an operation on flash memory metadata in a transaction interface; S2. storing a temporary data object as a shadow version while performing the transaction, using a shadow mapping table to store the address of the shadow version or a state of a page, using page metadata to record transaction information, using a transaction metadata page to record a transaction state, and using a transaction state table to record an address of the transaction metadata page; and S3. when the coordinator or a participant fails, recovering the FTL mapping table, shadow mapping table, and transaction state table with the help of stored data and flash memory metadata.

Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. When performing the allocation process for a selected entry, the control circuitry is arranged to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address. The control circuitry then determines whether predetermined criteria are met by the plurality of descriptors, the predetermined criteria comprising page alignment criteria and attribute match criteria.

Abstract: A system for providing both low-level, physical data access and high-level, logical data access to a single process is disclosed, having a data block table with a physical memory address portion and a logical memory address portion. Data blocks that are mapped to physical memory bypass multiple logical memory address layers, such as the operating system layer and a logical block address layer, while data blocks that are mapped to the logical memory will be routed through traditional API layers, providing both increased performance and flexibility.

Abstract: Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD. The DRAM and the SSD are also sectioned into pages and mapped to pages of the host memory. A host processor is operable to generate Input/Output (I/O) requests. An HBA driver is operable to process the I/O requests. The HBA driver is also operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

Abstract: Disclosed are systems and methods for managing a browser cache. An example method comprises storing in a browser cache on a user device information of web pages visited by a user during one or more web browsing sessions; determining logical relationships among the web pages stored in the cache; associating the web pages with one or more clusters based on the determined logical relationships; upon detecting a usage size of the cache equal to or exceeding a threshold value, identifying information associated with the one or more clusters in the cache; determining a web page or a cluster of web pages to be deleted from the cache based on the identified information; and deleting from the cache one or more web pages based on the identified information associated with each of the one or more clusters.

Abstract: A system and method for efficiently caching metadata in a storage system. Addresses from a plurality of I/O accesses to the storage system are captured and then a frequency domain representation of the addresses is generated. The frequency domain representation is used to measure the randomness of the various applications which are accessing the storage system. Scores are generated based on the measure of randomness, and scores are assigned to the various regions of the logical address space. Scores are then assigned to the metadata pages which are stored in the cache based on the region of the logical address space to which the metadata pages correspond. The scores are used when determining which metadata pages to evict from the cache. The cache will attempt to evict those metadata pages which correspond to regions of the logical address space that are servicing random I/O accesses.

Abstract: A hypervisor receives, from a guest virtual machine, a request to disable access to a memory range. The hypervisor disables access to the memory range. The hypervisor detects a prohibited access attempt. The prohibited access attempt is an access attempt to the memory range. Responsive to detecting the prohibited access attempt, the hypervisor stops the guest virtual machine. The hypervisor receives a request to reboot the guest virtual machine. The hypervisor reboots the guest virtual machine. Responsive to rebooting the guest virtual machine, the hypervisor enables access to the memory range.

Abstract: Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.

Abstract: Systems and methods for securing configuration information for cloud-based services. A system comprises a data store and data sets including plant process information and configuration information. A memory device stores computer-executable instructions. When executed by a processor coupled to the cloud service, the instructions receive configuration information, store it in a data file, apply a generated certificate to the file, and deploy the resulting protected configuration data file to the cloud-based service. In addition, the protected configuration data file is made available by obtaining the file from the cloud-based service.

Abstract: A technique implements memory views using a virtualization layer of a virtualization architecture executing on a node of a network environment. The virtualization layer may include a user mode portion having hyper-processes and a kernel portion having a micro-hypervisor that cooperate to virtualize a guest operating system kernel within a virtual machine (VM) of the node. The micro-hypervisor may further cooperate with the hyper-processes, such as a guest monitor, of the virtualization layer to implement one or more memory views of the VM. As used herein, a memory view is illustratively a hardware resource (i.e., a set of nested page tables) used as a container (i.e., to constrain access to memory of the node) for one or more guest processes of the guest operating system kernel.

Abstract: One or more mappings each define a correspondence between one or more input attributes of an input entity and one or more output attributes of an output entity, where the input entity includes one or more key attributes identified as part of a unique key, and the output entity includes one or more key attributes identified as part of a unique key. Generating instances of the output entity includes: determining one or more mapped input attributes of the input entity that correspond to each of the key attributes of the output entity, based on the mappings; and comparing the mapped input attributes with the key attributes of the input entity to determine whether the mapped input attributes include: (1) all of the key attributes of the input entity, or (2) fewer than all of the key attributes of the input entity.

Abstract: One or more mappings each define a correspondence between input attributes of an input entity and output attributes of an output entity, where the input out output entities each include one or more key attributes identified as part of a unique key. Computing result information, displayed in a user interface, includes: processing instances of a first input entity to generate instances of a first output entity; determining one or more mapped input attributes of the first input entity that correspond to each of the key attributes of the first output entity; generating the instances of the first output entity based on the determined one or more mapped input attributes; computing a total number of instances of the first input entity that were processed; and computing a total number of instances of the first output entity that were generated.

Abstract: An I/O (Input/Output) adapter device can present itself as a storage backend driver with an emulated storage backend driver interface to a corresponding storage frontend driver executing from an operating system running on a host device independent of a virtualization or non-virtualization environment. For each guest operating system executing from its respective virtual machine running on the host device, para-virtualized (PV) frontend drivers can communicate with corresponding PV backend drivers implemented by the I/O adapter device using a corresponding virtual function by utilizing SR-IOV (single root I/O virtualization) functionality.

Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM), and an interface circuit for interfacing the system to an external posted transaction bus. Each processor has the same address map. Each fetches instructions from SLMEM, and accesses data from/to SLMEM. A processor can initiate a read transaction on the posted transaction bus by doing an AHB-S bus write to a particular address. The AHB-S write determines the type of transaction initiated and also specifies an address in a shared memory in the interface circuit. The interface circuit uses information from the AHB-S write to generate a command of the correct format. The interface circuit outputs the command onto the posted transaction bus, and then receives read data back from the posted transaction bus, and then puts the read data into the shared memory at the address specified by the processor in the original AHB-S bus write.

Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Abstract: Embodiments of the present invention provide a method and system of switching a wireless connection between a plurality of input devices and a first host device to at least a second host device. Embodiments of the invention are directed to systems and methods for switching multiple, independently connected data input devices from a first host computing device to a second host computing device together based on a single command or operation.

Abstract: Examples of data polling using a chain sleep technique are disclosed. In one example, a computer-implemented method includes: computing a least common multiplier (LCM) based on a polling time for each of a plurality of devices deployed in a well operation to be polled; generating a sequence of polling elements, wherein each of the polling elements represents a multiple of the polling time for each of the plurality of devices, wherein the sequence of polling elements begins with the lowest polling time and ends with the LCM; sorting the sequence of polling elements from lowest value to highest value as an ordered list; calculating a distance between each of the polling elements of the ordered list; generating a polling chain based on the ordered list and the distance between each of the polling elements; and polling the plurality of devices in the well operation based on the polling chain.

Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data segment is then transmitted as the next data segment transferred.

Abstract: A USB interface to provide power delivery negotiated through a dedicated transmission channel includes a transmitter circuit including a digital-to-analog converter having an output coupled with an input of a transmission filter, a receiver circuit including an analog-to-digital converter having an input coupled with an output of a receiving filter, and a switching circuit configured in an operating mode of the USB interface to connect an output of the transmission filter and an input of the receiving filter to a connection node of the dedicated transmission channel.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device receives first command or data through a first serial port of the embedded-system device. The embedded-system device further exposes a second serial port to a host of the embedded-system device such that the host has control over the second serial port and receiving second command or data from the host for outputting at the second serial port. The embedded-system device also redirects the first command or data to the second serial port when the embedded-system device is in a first mode. The embedded-system device allows the second command or data to be output at the second serial port when the embedded-system device is in a second mode.

Abstract: It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing.

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

Abstract: A method is implemented by a network device to configure the operation of a Peripheral Component Interconnect Express (PCIe) switch to enable an efficient transition from a first active processor in a first root complex to a backup processor in a second root complex. The method involves determining the first active processor in the first root complex and a set of backup processors and a set of root complexes, and configuring each root complex for independent PCIe switch communication. The method further includes detecting a failure of the active processor in the first root complex, selecting and notifying the backup processor and the second root complex to transition to be a second active processor and second root complex, and starting communication with PCIe devices using previously configured independent PCIe switch communication for the second processor of the second root complex.

Abstract: A method for creating snapshots and backups in a virtual computing environment is provided. The method includes writing application output of an application spanning one or more virtual machines as an application consistency group to a writeback cache, wherein the one or more virtual machines are implemented using one or more compute nodes and wherein the writeback cache is implemented in direct attached storage in the one or more compute nodes. The method includes pausing I/O (input/output) operations of the application and marking the pausing, in the writeback cache. The method includes resuming the I/O operations of the application, after the marking and dumping data, according to the marking, from the writeback cache to a data node, as a snapshot.

Abstract: A semiconductor device in which a ground state of an Ising model is realized, includes a spin array in which a spin unit is formed, the spin unit including a memory cell storing a value of one spin in an Ising model, a memory cell storing an interaction coefficient from an adjacent spin interacting with the spin, a memory cell storing an external magnetic field coefficient of the spin, and a circuit deciding a next state of the spin by binary majority decision logic based on a product of the value of each of the adjacent spins and the corresponding interaction coefficient, and the external magnetic field coefficient. The spin array is formed by having a plurality of the spin units, each having each spin allocated thereto, arranged and connected on a two-dimensional plane on a semiconductor substrate in the state where a topology of the Ising model is maintained.

Abstract: A method, a computing system, and a non-transitory machine readable storage medium containing instructions for managing a stream processing topology are provided. In an example, the method includes receiving a first topology that communicatively couples a plurality of processing elements via a first arrangement of interconnections to perform an operation on a stream of data. A second topology is defined that communicatively couples the plurality of processing elements via a second arrangement of interconnections that is different from the first arrangement. The second topology assigns the plurality of processing elements a first set of operations. The second topology is provided to a stream processing manager and is modified during processing of the stream of data by assigning a second set of operations to the plurality of processing elements that is different from the first set of operations.

Abstract: A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

Abstract: An inter-integrated circuit bus arbitration system includes a first master circuit, a second master circuit, an analog switch circuit, an initial state identification circuit, and a selection control circuit. When the first master circuit is initiated to transmit data, the initial state identification circuit generates a first initial pulse signal. When the second master circuit is initiated to transmit data, the initial state identification circuit generates a second initial pulse signal. If the first initial pulse signal leads the second initial pulse signal, the selection control circuit generates a first control signal to make the analog switch circuit establish electrical connections between the first master circuit and an external data line and an external clock line when receiving the first control signal.

Abstract: A method for managing a multi-lane serial link is described. The method includes establishing a serial link between a number of integrated circuits across a first number of lanes. The first number of lanes are a subset of a number of available lanes on the serial link. The method also includes selecting to change a transmission state of a second number of lanes. The second number of lanes are a subset of the available lanes. The method also includes changing the transmission state of the second number of lanes while transmitting data on a number of remaining lanes. The method further includes synchronizing the first number of lanes and the second number of lanes.

Abstract: A gesture controlled calculator has a touch screen controlled by a microprocessor. The touch screen receives a multiplication problem input by a user through a virtual keyboard. After the problem is entered, the calculator breaks up the problem into easy multiplication problems and then very easy multiplication problems in response to touch gestures by the user. The very easy multiplication problems are then presented on the graphical user interface of the touch screen as columns of virtual digits cards. The virtual digit cards are added together in response to touch gestures by the user. The solutions to the very easy multiplication problems are then presented as columns of digit cards. These digit cards are then added together in response to touch gestures by the user. The solution to the multiplication problem is then presented in the graphical user interface.

Abstract: A global context object may be used to create context affinity between two or more commands executed at a remote computer. A local computer may access a connection pool to determine if a runspace exists for a particular context on the remote computer in which the command is to be executed. If the runspace does not exist in the connection pool, the local computer may create a runspace associated with a particular context and add the runspace to the connection pool. The local computer may receive result data of executed commands from a remote computer and store the result data for use by the global context object to create context affinity between two or more commands executed at the remote computer.

Abstract: A stratified or segmented composite data structure can be formed by selecting a group of data entities, stratifying or segmenting them according to attributes, and assigning relative weights to the components based on their stratified or segmented positions. The attributes are selected from a universe of possible values. Further positive and negative biases can be applied at any arbitrary point or position, including to individual data entities, groups of arbitrarily selected data entities, or arbitrary positions.

Abstract: Systems, apparatuses and methods for generating a graphical user interface (GUI) conforming to a graphical representation employ computer vision, optical character recognition, and other techniques to generate a structure of the GUI as a view hierarchy. A development project with source code and resource files is created to generate an application having the GUI. The application and GUI are applicable to mobile and other platforms using various operating systems, such as Android®, iOS®, and others.

Abstract: A persistent viewports architecture that provides a persistent and correctly-positioned viewport to a user when a collaboration document is being updated. The architecture identifies and utilizes a user's element-of-interest in content of the document to determine and recalculate the correct position of the user viewport. The architecture tracks a topmost element of the content (or section of content) from the viewport and employs the topmost element as a reference element. The topmost element can be one or more of a paragraph, a header, string of text, and an image. When the underlying document is to be updated, the viewport performs a lookup of reference element, and after finding the reference element, adjusts the X and Y offsets of the viewport so that the element-of-interest is inside the viewport.

Abstract: Technologies are described for rich visualization of embedded objects, attachments, and links within emails and similar forms of online conversations. In some examples, the embedded objects, attachments, and links may be analyzed and parsed to generate teasers, which may include enhanced images, summary information, and comparable features. The teasers may be presented within a body of an email or in a dedicated area of a conversation user interface and include interactive features such as presentation of detailed information upon selection without opening and processing individual emails.

Abstract: The present disclosure provides a method and an apparatus for establishing a sentence editing model and a sentence editing method and apparatus. The methods includes: obtaining queries and titles of clicked search results corresponding to the queries from search logs to form query-title pairs; forming training corpuses by taking a title in each of the query-title pairs as a sentence to be edited and taking a query in the query-title pair as an edited sentence; and training a translation model and a first language model using the training corpuses to obtain a sentence editing model including the translation model and the first language model; after obtaining a sentence to be edited, inputting the sentence to be edited to a sentence editing model to obtain an editing score of each candidate edited sentence; and selecting a candidate edited sentence having an editing score satisfying a preset requirement as an edited sentence.

Abstract: Information extraction and annotation systems and methods for use in annotating and determining annotation instances are provided herein. Exemplary methods include receiving training documents having annotated words, identifying a predetermined number of characters preceding and following each annotated word for each of the training documents to determine a context for each of the annotated words, performing an alignment of an annotated word and its context with characters in the target document, identifying common sequences, and assigning annotations to words in the target document when common sequences are found.

Abstract: The claimed subject matter provides a system and/or a method that facilitates communicating data utilizing a portable device. An interface component can receive annotation data related to a display associated with a portable device. An annotation component can append a screen shot corresponding to the display with the annotated data to create an annotated screen shot.

Abstract: Systems and methods are provided for intelligently adapting content presented in electronic forms. In some embodiments, a processor provides access to multiple instances of a first version of an electronic form by multiple clients based on determining that insufficient data exists in a data source for a category of information. The first version of the form can include content for soliciting data associated with the category of information. The processor can receive responsive electronic communications in response to providing access to the first version of the form. The processor can provide access to multiple instances of a second version of the electronic form by multiple clients based on determining from the received responses whether sufficient data exists for the category of information. The second version of the electronic form can omit or replace the content for soliciting data associated with the category of information.

Abstract: A computer system for receiving user data comprising a user access component having a display and a processor arranged to execute a data receiving application, wherein the data receiving application provides on the display at least one address field; and a geographical location device in communication with a location network and arranged to identify a geographical location of the device using information from the location network, the geographical location device located at a user address, the geographical location device operable to provide location data from which address data of the user address is derived and supplied to the data receiving application to automatically populate the address field on the display.

Abstract: The system includes an input interface and a processor. The input interface is to receive a spreadsheet and an indication of a spreadsheet cell of interest. The processor is to determine a first set of spreadsheet cells that the spreadsheet cell of interest depends on, determine a second set of spreadsheet cells that depend on the spreadsheet cell of interest, provide a spreadsheet cell data flow view for the spreadsheet cell of interest based at least in part on the first set of spreadsheet cells and the second set of spreadsheet cells, and in the event an indication of a new spreadsheet cell of interest is received, provide a spreadsheet cell data flow view for the new spreadsheet cell of interest.

Abstract: A spreadsheet includes a native spreadsheet object that represents a person. The person object may be used within a spreadsheet just as any other spreadsheet objects are utilized. For example, the person object may be integrated with spreadsheet formulas and other spreadsheet objects such as charts, tables, pivot tables, sheets, and the like. Spreadsheet formulas may perform operations specific to a person object (e.g. send message, get contact information, get status, get other person specific information, sort, and the like). Common actions may be associated with the person object, such as initiating communication with the person represented by the person object (e.g. phone call, email, text message, collaboration invite, and the like). Social networking information may also be associated with a person object. For example, social networking posts may be included within a spreadsheet, a user may post to a social network from the spreadsheet, and the like.

Abstract: Devices and methods for determining the content of a first segment of text in a first language, using a second segment of text in a second language. The second segment of text is a translation of the first segment of text.