Patents Issued in March 26, 2019
-
Patent number: 10241771Abstract: A virtual application packaged for a specific executing environment may be executed on a processing device having an executing environment different from the specific executing environment. A reference, included in extracted installer metadata, to one or more key paths of a hierarchically-structured data store may be modified according to a set of rules related to the executing environment detected in the processing device. The modified extracted installer metadata may be provided to an installer for installing the virtual application. During execution of the virtual application, a request to read, write, or modify the hierarchically-structured data store may be intercepted and changed, such that a first key path included in the request may be mapped to a second key path, based on the detected executing environment. Similarly, a response to the request, which may include the second key path, may be intercepted and modified, to the first key path.Type: GrantFiled: March 29, 2013Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Kristofer Reierson, Feroz Gora, Charles Kossi Kekeh, Peter A. Morgan, Joseph W. Rovine, John M. Sheehan, Lidiya Vikhlyayeva
-
Patent number: 10241772Abstract: A method is described that includes comprising receiving, by a first computing device and from a second computing device, an indication of user interaction with a first application. The method also includes determining, by the first computing device and based on the user interaction with the first application, a user engagement score associated with the first application, the user engagement score indicating at least one of how frequently or how long the user uses the first application. The method also includes responsive to determining that the user engagement score does not satisfy a threshold user engagement score, determining, by the first computing device and from a set of applications that are alternatives to the first application, a second application to substitute for the first application. The method further includes sending, by the first computing device and to the second computing device, for display, an indication of the second application.Type: GrantFiled: July 7, 2016Date of Patent: March 26, 2019Assignee: Google LLCInventors: Huazhong Ning, Haichun Chen
-
Patent number: 10241773Abstract: A desktop management system is described that provides an automated process for distributing and suggesting modifications. The system is comprised of a central server and multiple client devices connected through a network. Application layer drafts for a particular modification (such as an installation, update, un-installation, fix, etc.) are generated based on snapshots of client devices before and after the modification is applied. Several application layer drafts are produced for a particular modification. Based on commonalities between the several application layer drafts, an official application layer is produced. When a client device requests a modification, an official application layer for the requested modification is retrieved and merged onto the requesting client device to apply the modification. If a client device on the network lacks an application that is present on similar client devices on the network, the system can suggest the application to the client device.Type: GrantFiled: February 28, 2014Date of Patent: March 26, 2019Assignee: VMware, Inc.Inventor: Tal Zamir
-
Patent number: 10241774Abstract: A deployment system provides the ability to deploy a multi-node distributed application, such as a cloud computing platform application that has a plurality of interconnected nodes performing specialized jobs. The deployment system may update a currently running cloud computing platform application according to a deployment manifest and a versioned release bundle that includes jobs and application packages. The deployment system determines changes to the currently running cloud computing platform application and distributes changes to each job to deployment agents executing on VMs. The deployment agents apply the updated jobs to their respective VMs (e.g., launching applications), thereby deploying an updated version of cloud computing platform application.Type: GrantFiled: December 10, 2015Date of Patent: March 26, 2019Assignee: Pivotal Software, Inc.Inventors: Vadim Spivak, Kent Skaar, Oleg Shaldibin
-
Patent number: 10241775Abstract: Aspects of the embodiments are directed to a common interface for associating an ordered set of instructions and/or resources from a release automation application with a configuration manager node associated with a server type. Embodiments are directed to identifying an application, identifying a deployment environment for deploying the application, identifying a configuration manager, identifying a server type from a plurality of server types available for the application, identifying a configuration management node associated with the server type, defining an ordered set of instructions and/or resources for the configuration management node by selecting an instruction or resource from a list of instructions and recipes associated with the configuration management node, and storing the ordered set of instruction and/or resources for future deployment of the application in the configuration management node.Type: GrantFiled: January 14, 2016Date of Patent: March 26, 2019Assignee: CA, Inc.Inventors: Shozab H. Naqvi, Scott W. Fraser, Shen-Kai Su, Bryan Perino, Tony Tsai, Paul D. Peterson, Rahbar A. Farooqi
-
Patent number: 10241776Abstract: Changing user settings across applications and/or across devices via a dialog within one application is provided herein. The systems and methods discussed herein provide for an improved user experience and fewer computing resources to be expended when changing user settings by aggregating the changeable settings, allowing for their modification via a single dialog, and distributing settings changes to remote hosts, which in turn provide consistent settings across devices. The settings available to the user may be governed in association with the user's licenses to access programs and may be affected by domain level controls by an administrator.Type: GrantFiled: August 8, 2016Date of Patent: March 26, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Abhishek Kumar, Gargee Sharma, Subash Kumar Bhamidipati, Ananthakrishnan Ramanathan, Matthew Carlo Razza, Vidya Kotteri, Ying Zhe Chong, Cancan Shi, Bhanu Samyal
-
Patent number: 10241777Abstract: A method and a system are provided to manage analytics assets associated with at least one computer accessible to an organization using operating system (OS) containers. The method comprising receiving a request to process of a task on the user computing device. The method further select a set of analytics assets from a first category, based on at least one of a role of the user in the organization and a historical usage of the one or more analytics assets or a second category that corresponds to the user and are included in the container image associated with the user. The method further update the container image of the user, based on at least the selection of the set of analytics assets from the first category. The method further render the selected set of analytics assets through the updated container image on the user computing device of the user.Type: GrantFiled: August 16, 2016Date of Patent: March 26, 2019Assignee: CONDUENT BUSINESS SERVICES, LLCInventors: Rahul Ghosh, Varun Sharma, Ajith Ramanath, Atul Singh, Koustuv Dasgupta
-
Patent number: 10241778Abstract: In one embodiment, configuration information for a microservices application is obtained, the microservices application comprising a plurality of microservice containers, and the configuration information comprising version information for each of the plurality of microservice containers. A graphical representation of the microservices application is displayed, wherein the graphical representation of the microservices application comprises a representation of each of the plurality of microservice containers. It is determined, based on the version information, whether each of the plurality of microservice containers is updated or outdated. A graphical indication of an updated microservice container is displayed; a graphical indication of an outdated microservice container is displayed; and a graphical indication of an extent to which the outdated microservice container is out-of-date is displayed.Type: GrantFiled: September 27, 2016Date of Patent: March 26, 2019Assignee: CA, Inc.Inventors: Mark W. Emeis, Robert C. Hendrich, Dann M. Church, Craig Andrew Vosburgh
-
Patent number: 10241780Abstract: A system, method, and computer program product for facilitating troubleshooting of remote workstation issues reported by an end user to a technical support center analyst in an enterprise network. A plurality of remote workstation software support tools are encapsulated in a support center utility application. Upon receiving a call from an end user (also referred to as customer herein), the remote workstation name for the end user is entered into the support center utility application. This causes information for the remote workstation and end user to be presented to the analyst via a support center utility application interface. At least one encapsulated remote workstation software support tool is launched based on an issue reported by the end user, the tool being pre-populated with information for the remote workstation from the support center utility application interface.Type: GrantFiled: May 22, 2017Date of Patent: March 26, 2019Assignee: OPEN INVENTION NETWORK LLCInventor: Kenneth R. Gailey, Jr.
-
Patent number: 10241781Abstract: A computer-based method for managing a plurality of computer components in an organization is provided. The method is implemented using a Component Manager (CM) computing device. The method includes receiving, from a stakeholder computing device, component data for at least one computer component of the plurality of computer components. The method also includes storing the component data in a memory block in the memory device. The method further includes assigning a first lifecycle classification, a domain, and at least one stakeholder to the at least one computer component by updating the memory block in the memory device. The method also includes causing the stakeholder computing device to electronically display an interactive dashboard that includes a graphical representation of the at least one computer component. The method further includes prompting a stakeholder to update a component utilization scheme for the computer component, by electronically displaying the graphical representation.Type: GrantFiled: March 9, 2018Date of Patent: March 26, 2019Assignee: MASTERCARD INTERNATIONAL INCORPORATEDInventor: Jeffrey Scott Smith
-
Patent number: 10241782Abstract: A method and associated system. A patching schedule is generated by scheduling, in W sequential time windows, P patches applicable to virtual machines in L redundancy groups. Each redundancy group includes virtual machines and independently belongs to a respective software application x of X software applications, wherein P?1, L?1, Rm?1, and X?1. The L redundancy groups collectively comprise at least 2 virtual machines. The scheduling determines xwmk for T tuples (w, m, k) defined by (w=1, . . . , W) and (m=1, . . . , L) and (k=1, . . . , Rm), by maximizing an objective function subject to constraints. Determining xwmk includes setting xwmk=1 if virtual machine k in redundancy group m is to be patched in time window w or setting xwmk=0 otherwise.Type: GrantFiled: January 3, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Manish Gupta, Rajeev Puri
-
Patent number: 10241783Abstract: Disclosed are apparatus and methods for processing configuration data sets. A computing device can retrieve configuration data set(s) from data storage. A configuration data set can include key-value pairs related to configuring a software application, where a key-value pair can include a key name and an associated value. The computing device can merge the configuration data set(s) into a merged configuration data set by at least: determining whether multiple key-value pairs of the configuration data set(s) are in conflict; after determining that multiple key-value pairs of the configuration data set(s) are in conflict, determining a representative key-value pair to represent the multiple key-value pairs; and adding the representative key-value pair to the merged configuration data set. The computing device can provide the merged configuration data set to the software application.Type: GrantFiled: April 18, 2018Date of Patent: March 26, 2019Assignee: Google LLCInventors: Tal Dayan, Safa Alai, Arda Atali, Shuai Jiang
-
Patent number: 10241784Abstract: Support for dynamic behavior is specified while reducing reliance on JIT compilation and large runtimes; semantic characteristics are selectively attached to types and type members outside source code. A directives document contains human-readable directives in a parsable format for submission to an innovative compiler. The directives specify whether a type T or type member M is required, optional, or prohibited in a runtime environment. Some reference an application, library, assembly, or namespace group, and others reference group components: type, type instantiation, method, method instantiation, field, property, or event. Some directives force a generic instantiation. Some directives indirectly reference a type through a parameter, type parameter, or generic directive. Some directives reference degrees to manage runtime activation of type instances, runtime introspection over types, reflection, and/or runtime or static serialization.Type: GrantFiled: February 6, 2017Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: John Lawrence Hamby, David Charles Wrighton, Michal Strehovsky, Morgan Asher Brown, Fadi Hanna, Turgut Isik, Mircea Trofin, Fatma Didem Gokbulut, Robert Yung-Yi Fu
-
Patent number: 10241785Abstract: Production or development uses of an application may be identified from tracing data when the data fits a heuristic. The heuristic may include length of execution run, number of executions, repeating patterns within the execution run, or other factors. Similarly, prototyping or development uses of an application may be identified by frequent code changes, sporadic uses, low loads, and other factors. The production and development uses of an application may be displayed by a uses versus user graph, where production users may be displayed as those users with the largest number of uses. The tracing data may be gathered by monitoring an entire application or from monitoring functions, modules, subroutines, libraries, interfaces, services, or other portions of an application.Type: GrantFiled: March 27, 2014Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventor: Russell Krajec
-
Patent number: 10241786Abstract: Techniques are provided for performing automated operations to determine maturity of a specified project. Information is received regarding each of a plurality of artifacts associated with the project, such as project documentation, source code repositories, and a tracked issue database for the project. A data sufficiency level associated with each provided artifact is determined, and each artifact is provided to one or more of multiple analysis engines. The analysis engines are executed to produce one or more weighted feature vectors for each of the artifacts associated with the specified project, and input to a prediction engine in order to provide a maturity rating for the project based on the weighted feature vectors.Type: GrantFiled: January 26, 2017Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anuradha Bhamidipaty, Evelyn Duesterwald, Andrew L. Frenkiel, Peter H. Westerink
-
Patent number: 10241787Abstract: Embodiments of an invention for control transfer overrides are disclosed. In one embodiment, a processor includes an instruction unit to receive a control transfer instruction. The instruction unit includes a transfer override register to provide an alternative target for the control transfer instruction.Type: GrantFiled: March 31, 2014Date of Patent: March 26, 2019Assignee: Intel CorporationInventor: Paul Caprioli
-
Patent number: 10241788Abstract: An apparatus including a queue configured to store a plurality of instructions and state information indicating whether each instruction of the plurality of instructions can be performed independently of older pending instructions; and a state-selection circuit configured to set a state information of each instruction of the plurality of instructions in view of an older pending instruction in the queue.Type: GrantFiled: October 31, 2014Date of Patent: March 26, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Tariq Kurd, John Redford
-
Patent number: 10241789Abstract: An apparatus includes a binary translator to hoist a load instruction in a branch of a conditional statement above the conditional statement and insert a speculation control of load (SCL) instruction in a complementary branch of the conditional statement, where the SCL instruction provides an indication of a real program order (RPO) of the load instruction before the load instruction was hoisted. The apparatus further includes an execution circuit to execute the load instruction to perform a load and cause an entry for the load instruction to be inserted in an ordering buffer, and where the execution circuit is to execute the SCL instruction to locate the entry for the load instruction in the ordering buffer using the RPO of the load instruction provided by the SCL instruction and discard the entry for the load instruction from the ordering buffer.Type: GrantFiled: December 27, 2016Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventors: Alexander Y. Ostanevich, Sergey P. Scherbinin, Jayesh Iyer, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich, Andrey Chudnovets, Sergey A. Rozhkov, Boris A. Babayan
-
Patent number: 10241790Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.Type: GrantFiled: December 15, 2015Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
-
Patent number: 10241791Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.Type: GrantFiled: March 20, 2018Date of Patent: March 26, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Lingam, Seok-Jun Lee, Johann Zipperer, Manish Goel
-
Patent number: 10241792Abstract: A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.Type: GrantFiled: December 30, 2011Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Elmoustapha Ould-Ahmed-Vall, Suleyman Sair, Kshitij A. Doshi, Charles Yount, Bret L. Toll
-
Patent number: 10241793Abstract: In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.Type: GrantFiled: March 7, 2014Date of Patent: March 26, 2019Assignee: ANALOG DEVICES GLOBALInventors: Michael G. Perkins, John L. Redford, Kaushal Sanghai
-
Patent number: 10241794Abstract: Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.Type: GrantFiled: December 27, 2016Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Sergey P. Scherbinin, Jayesh Iyer, Alexander Y. Ostanevich, Dmitry Maslennikov, Denis G. Motin, Alexander V. Ermolovich, Andrey Chudnovets, Sergey A. Rozhkov, Boris A. Babayan
-
Patent number: 10241795Abstract: A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.Type: GrantFiled: July 12, 2016Date of Patent: March 26, 2019Assignee: Intel CorporationInventor: Mohammad Abdallah
-
Patent number: 10241796Abstract: A compiler-assisted lookahead (CAL) memory system for a CAL microprocessor consisting of a CAL memory management unit, a CAL lookahead instruction (LI) and compatible instruction (CI) memory system, and a CAL LI and CI cache system, is designed for operating with a CAL frontend processor to fetch LIs and CIs in a lookahead manner and to reorder the LIs/CIs fetched before decoding them for producing compatible results of the program. The invention is for enhancing performance and energy-efficiency of loop operations by reusing the LIs and CIs in the loops without fetching them iteratively from the CAL memory system.Type: GrantFiled: February 13, 2017Date of Patent: March 26, 2019Inventor: Yong-Kyu Jung
-
Patent number: 10241797Abstract: A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.Type: GrantFiled: July 17, 2012Date of Patent: March 26, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Ganesh Venkataramanan, Mike Butler, Krishnan V. Ramani
-
Patent number: 10241798Abstract: An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution pipeline. The issue control unit maintains a history buffer that reflects, for N previous cycles, the number of instructions issued during each of those N cycles. If the total number of instructions issued during the N previous cycles exceeds a threshold value, then the issue control unit throttles the instruction issue unit from issuing instructions during a subsequent cycle. In addition, the issue control unit increases the threshold value in proportion to the number of previously issued instructions and based on a variety of configurable parameters. Accordingly, the issue control unit maintains granular control over the rate with which the instruction issue unit āramps upā to a maximum instruction issue rate.Type: GrantFiled: September 20, 2013Date of Patent: March 26, 2019Assignee: NVIDIA CORPORATIONInventors: Peter Sommers, Peter Nelson, Aniket Naik, John H. Edmondson
-
Patent number: 10241799Abstract: Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.Type: GrantFiled: July 16, 2010Date of Patent: March 26, 2019Assignee: QUALCOMM IncorporatedInventors: Alexei V. Bourd, Guofang Jiao
-
Patent number: 10241800Abstract: A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.Type: GrantFiled: June 16, 2015Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Hung Q. Le, Dung Q. Nguyen, David R. Terry
-
Patent number: 10241801Abstract: An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file. The apparatus further includes a buffer to store strand documentation for a strand from the plurality of strands, where the strand documentation for the strand is to include an indication of a current register base for the strand. The apparatus further includes an execution circuit to execute an instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.Type: GrantFiled: December 23, 2016Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventors: Jayesh Iyer, Sergey P. Scherbinin, Alexander Y. Ostanevich, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich, Andrey Chudnovets, Sergey A. Rozhkov, Boris A. Babayan
-
Patent number: 10241802Abstract: A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.Type: GrantFiled: November 20, 2015Date of Patent: March 26, 2019Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)Inventors: John Lancaster, Martin Whitaker
-
Patent number: 10241803Abstract: Devices include a processor and a memory. The processor is configured to determine if a bootloader area does not contain a valid bootloader instruction set, to locate a bootloader instruction set, and to copy the bootloader instruction set to the bootloader area. The processor then executes the bootloader instruction set from the bootloader area.Type: GrantFiled: October 3, 2016Date of Patent: March 26, 2019Assignee: SCHNEIDER ELECTRIC IT CORPORATIONInventors: Wen-Chun Peng, Hsin-Hsiao Lin
-
Patent number: 10241804Abstract: Approaches are described for enabling a host computing device to store credentials and other security information useful for recovering the state of the host computing device in a secure store, such as a trusted platform module (TPM) on the host computing device. When recovering the host computing device in the event of a failure (e.g., power outage, network failure, etc.), the host computing device can obtain the necessary credentials from the secure store and use those credentials to boot various services, restore the state of the host and perform various other functions. In addition, the secure store (e.g., TPM) may provide boot firmware measurement and remote attestation of the host computing devices to other devices on a network, such as when the recovering host needs to communicate with the other devices on the network.Type: GrantFiled: April 10, 2017Date of Patent: March 26, 2019Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Nachiketh Rao Potlapally, Rachit Chawla, Jeremy Ryan Volkman, Michael David Marr
-
Patent number: 10241805Abstract: Embodiments described herein include methods and systems for remotely managing appliances, including enabling communication between a user of the appliance and third party systems. The third party systems can include any entity that has a relationship with the user of the appliance, such as a payment infrastructure handling incremental payments for the appliance, and managing access to the appliance accordingly. In some embodiments, the appliance being controlled is a mobile phone that also includes third party operating system software. Various methods for preventing alteration or replacement of the third party operating system are also described.Type: GrantFiled: December 10, 2015Date of Patent: March 26, 2019Assignee: PAYJOY INC.Inventor: Douglas James Ricket
-
Patent number: 10241806Abstract: The present invention extends to methods, systems, and computer program products for adjusting user interfaces based on entity location. Embodiments of the invention provide applications (or an operating system) with entity distance/proximity data. Applications can then scale content appropriately based on the proximity data. An operating system contains a distance/proximity driver framework for distance/proximity aware hardware sensors (IR, Radar, capacitive, camera, other). The proximity framework performs distance/proximity/number of viewers calculations from sensor data to formulate proximity data. From the proximity data, an application can determine how to scale user interface data.Type: GrantFiled: March 9, 2016Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Michael Hall, Alexander T. Bussmann
-
Patent number: 10241807Abstract: Provided is a vehicle control device with which it is possible to reduce the time required to rewrite a control program. In the vehicle control device according to the present invention, after an updated version of the control program has been stored in a second storage unit, a first storage unit is initialized in advance before the instruction to update the control program has been executed.Type: GrantFiled: August 17, 2015Date of Patent: March 26, 2019Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Fumiharu Nakahara, Kenichi Kurosawa
-
Patent number: 10241808Abstract: In one example of the disclosure, a graphic user interface is provided and a plurality of factors to be considered by a user in evaluating a test application are caused to be displayed via the interface. The test application to test a software program. User-assigned ratings for test application evaluation factors are received via the interface. The test application evaluation factors include a documentation test quality factor, a product-general test quality factor, a product-specific test quality factor, and a defect seventy factor. An overall test effectiveness rating for the test application is determined based upon the ratings.Type: GrantFiled: November 26, 2014Date of Patent: March 26, 2019Assignee: ENTIT SOFTWARE LLCInventors: Millikarjuna Reddy Kolagatla, Narasimhamurthy M R, Padmini R, Narayana Rao SVN
-
Patent number: 10241809Abstract: A context-sensitive help system for obtaining insights from a target environment in an unobtrusive manner. The context-sensitive help system detects a search or opening of a help document containing a plurality of placeholders and product/component names by a user; crawls documents in the knowledgebase and extracts product and/or component names and corresponding configuration parameters or placeholders; stores the product and/or component names and placeholders in the placeholder dictionary along with links and an index to documents in the knowledgebase. The system extracts insights from the target environment in an unobtrusive manner; and replaces placeholders in the help document with values from the target environment based on the insights from the target environment; and then displays the help document to the user.Type: GrantFiled: April 15, 2016Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Bharath Gopalakrishnan, Albee Jhoney, Sundaravelu Shanmugam
-
Patent number: 10241810Abstract: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.Type: GrantFiled: May 18, 2012Date of Patent: March 26, 2019Assignee: Nvidia CorporationInventors: Rupert Brauch, Madhu Swarna, Ross Segelken, David Dunn, Ben Hertzberg
-
Patent number: 10241811Abstract: A compilation system can define, at compile time, the data blocks to be managed by an Even Driven Task (EDT) based runtime/platform, and can also guide the runtime/platform on when to create and/or destroy the data blocks, so as to improve the performance of the runtime/platform. The compilation system can also guide, at compile time, how different tasks may access the data blocks they need in a manner that can improve performance of the tasks.Type: GrantFiled: November 24, 2017Date of Patent: March 26, 2019Assignee: Significs and Elements, LLCInventors: Muthu M. Baskaran, Benoit J. Meister, Benoit Pradelle
-
Patent number: 10241812Abstract: Systems and methods are provided for assigning and associating resources in a cloud computing environment. Virtual machines in the cloud computing environment can be assigned or associated with pools corresponding to users as dedicated, standby, or preemptible machines. The various states provide users with the ability to reserve a desired level of resources while also allowing the operator of the cloud computing environment to increase resource utilization.Type: GrantFiled: October 28, 2014Date of Patent: March 26, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Bradley Gene Calder, Ju Wang, Vaman Bedekar, Sriram Sankaran, Marvin McNett, II, Pradeep Kumar Gunda, Yang Zhang, Shyam Antony, Kavitha Manivannan, Hemal Khatri
-
Patent number: 10241813Abstract: A system and method for patching an application running in a computing system, the method comprising: in response to that there is a need to patch a first content and the first content has been in the memory, distinguishing between a new content and an old content, the new content being the patched first content, the old content being the first content that has been in the memory; and in response to that the new content is loaded to the memory, mapping to the new content a new process that needs to apply the first content, wherein the new process comprises a process that is started after loading the new content to the memory. An apparatus for patching an application is further disclosed. With the apparatus provided, it is possible to perform dynamic patching to a virtual machine or a physical machine without stopping a running process.Type: GrantFiled: July 25, 2016Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Chun Hai Chen, Yi Ge, Li Li, Liang Liu, Jun Mei Qu
-
Patent number: 10241814Abstract: Systems and methods for live migration are provided. A hypervisor receives a request to migrate a virtual machine from a source host machine to a destination host machine, and maps memory of the virtual machine on the source host machine to a storage device accessible by the source host machine and by the destination host machine.Type: GrantFiled: January 29, 2013Date of Patent: March 26, 2019Assignee: Red Hat Israel, Ltd.Inventor: Michael Tsirkin
-
Patent number: 10241815Abstract: A data handling system includes a managing resource that manages one or more managed resources. The managed resource inherits tags of its managing resource(s). A user of the data handling system may apply tags to a managing resource via a management console. The tags may be applied via a user interface and utilized to organize the managed and managing resources. The tags may be typeless in that the user may assign any type of meaning to any tag. Tags assigned to the managing resource are applied or inherited to the resources it manages. The pattern of inheritance repeats through ānā generations as managed resources, themselves, can be managing resources.Type: GrantFiled: August 26, 2014Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Randal L. Bertram, Niraj D. Patel, Aaron D. Sahlin
-
Patent number: 10241816Abstract: A data handling system includes a managing resource that manages one or more managed resources. The managed resource inherits tags of its managing resource(s). A user of the data handling system may apply tags to a managing resource via a management console. The tags may be applied via a user interface and utilized to organize the managed and managing resources. The tags may be typeless in that the user may assign any type of meaning to any tag. Tags assigned to the managing resource are applied or inherited to the resources it manages. The pattern of inheritance repeats through ānā generations as managed resources, themselves, can be managing resources.Type: GrantFiled: October 2, 2014Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Randal L. Bertram, Niraj D. Patel, Aaron D. Sahlin
-
Patent number: 10241817Abstract: A hypervisor associates a combined register space with a virtual device to be presented to a guest operating system of a virtual machine, the combined register space comprising a default register space and an additional register space. Responsive to detecting an access of the additional register space by the guest operating system of the virtual machine, the hypervisor performs an operation on behalf of the virtual machine, the operation pertaining to the access of the additional register space.Type: GrantFiled: November 25, 2014Date of Patent: March 26, 2019Assignee: RED HAT ISRAEL, LTD.Inventors: Michael S. Tsirkin, Paolo Bonzini
-
Patent number: 10241818Abstract: Disclosed herein is an in-memory virtual desktop system, which stores a virtual desktop image in main memory in order to prevent a load from being concentrated on a disk, and operates a virtual desktop using the virtual desktop image. The disclosed system includes an in-memory virtual desktop system, including hardware including main memory for storing virtual desktop images, and a hypervisor for virtualizing resources of the hardware and providing virtualized resources to a virtual desktop.Type: GrantFiled: February 22, 2016Date of Patent: March 26, 2019Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Seong-Woon Kim, Jong-Bae Moon, Byeong-Thaek Oh, Jung-Hyun Cho, Hag-Young Kim, Myeong-Hoon Oh, Ji-Hyeok Choi
-
Patent number: 10241819Abstract: Virtualization software establishes multiple execution environments within a virtual machine, wherein software modules executing in one environment cannot access private memory of another environment. A separate set of shadow memory address mappings is maintained for each execution environment. For example, a separate shadow page table may be maintained for each execution environment. The virtualization software ensures that the shadow address mappings for one execution environment do not map to the physical memory pages that contain the private code or data of another execution environment. When execution switches from one execution environment to another, the virtualization software activates the shadow address mappings for the new execution environment. A similar approach, using separate mappings, may also be used to prevent software modules in one execution environment from accessing the private disk space or other secondary storage of another execution environment.Type: GrantFiled: February 26, 2016Date of Patent: March 26, 2019Assignee: VMware, Inc.Inventors: Xiaoxin Chen, Carl A. Waldspurger, Pratap Subrahmanyam
-
Patent number: 10241820Abstract: Some embodiments provide a method for identifying a realization status of one or more logical entities of a logical network. In some embodiments the method is implemented by a controller that controls network data communications in a logical network. The method receives a request for realization status of a set of logical entities at a particular point of time that is associated with a particular value of a realization number. The method determines whether configuration data up to the particular point of time for each logical entity in the set has been processed and distributed to a set of local controllers that operates on a set of host machines. The method returns a realization reply that includes a successful realization message when the configuration data up to the particular point in time for each logical entity in the set has been processed and distributed to the set of local controllers.Type: GrantFiled: March 14, 2016Date of Patent: March 26, 2019Assignee: NICIRA, INC.Inventors: W. Andrew Lambeth, James Joseph Stabile, Ganesan Chandrashekhar, Pankaj Thakkar, Peter J. Balland, III, Igor Ganichev
-
Patent number: 10241821Abstract: The present disclosure provides RNG states. Generating the RNG states can include creating a first VM with a first RNG state and a second VM with a second RNG state and generating a plurality of interrupts for the first VM and the second VM. Generating the RNG states can also include providing the plurality of interrupts to the first VM with a first plurality of time intervals between the plurality of interrupts to configure the first RNG state and providing the plurality of interrupts to the second VM with a second plurality of time intervals, between the plurality of interrupts, that are different from the first plurality of time intervals to configure the second RNG state to be different from the first RNG state.Type: GrantFiled: December 2, 2016Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventors: Josh Triplett, Adriaan Van De Ven