Abstract: A system is provided for multicasting an event notification from an event producer to multiple event listeners, where the event producer and event listeners exist within a computer operating system having a user space, a kernel space, a device space, and an event protocol handler located in the kernel space. The system generates an event indication from an event producer located in the user space, kernel space, or device space, and receiving the event indication in the event protocol handler and generating an event notification. The event producer and the event listeners interface with the event protocol handler to send the event indication and receive the event notification. The event listeners may be located in the user space, kernel space, or device space.

Abstract: Examples disclosed herein relate to storage drive management. Some examples disclosed herein a storage controller may adjust failure criteria for a storage drive and determine whether to fail the storage drive based on the adjusted failure criteria. The storage controller may adjust the failure criteria based on various factors, such as the quantity of input/output (I/O) command abort attempts corresponding to the storage drive issued by a host device.

Abstract: A computer-implemented method for providing crash results for a computer system on a graphical user interface is disclosed. A component access control feature is displayed on a graphic user interface. The component access control feature enables a user to select a component and view crash results pertaining to the component. A graphical representation for display on the graphic user interface is generated. The graphical representation includes at least a portion of a signature back trace corresponding to a crash associated with the component.

Abstract: A system and method for providing a watchdog timer to enable collection of crash data is provided. Upon execution of certain operations, a source thread of an application initiates a watchdog thread that periodically sample state of data relating to the application. Should the operation not complete within a watchdog timeout period, the watchdog thread invokes a crash function to collect additional state data. At least a portion of the state data is stored for later analysis and debugging.

Abstract: An information handling system pre-boot fault monitor tracks errors detected before boot of an operating system and stores the errors in persistent memory as error hashes generated from information associated with the error. Corrective actions associated with error hashes are determined by data mining error hashes provided from a population of deployed systems and stored in the persistent memory of the deployed systems. As the pre-boot fault monitor detects errors, a matching comparison between detected error hashes and stored corrective action hashes provides pre-boot instructions with corrective actions so that boot can be completed and the error managed with the operating system after POST.

Abstract: Methods and systems for automatically resolving computerized electronic communication anomalies are disclosed herein. The system can include a memory including an error database containing information identifying a plurality of previous detected errors and configuration information associated with those errors. The system can include a plurality of user devices. Each of these plurality of user devices can include: a first network interface to exchange data via the communication network; and a first I/O subsystem to convert electrical signals to user interpretable outputs via a user interface. The system can include a server that can: receive an indication of the initiation of electronic communication; receive an electrical signal including attribute information; receive an error message; identify a trend in error messages; and provide an error solution if a trend is identified.

Abstract: Embodiments described herein provide a method, system, and computer readable medium configured to analyze a heap following a core dump is disclosed herein. The method begins by generating the core dump responsive to an occurrence of an event in a run-time environment. The core dump contains the contents of a heap at a moment in time that the event occurred. The processor analyzes the heap in the run-time environment using a first heap analysis method at a first starting point in the heap. The heap includes one or more slots. Each slot contains one or more objects. The processor analyzes the contents of the heap specified by the core dump using a second heap analysis method at a second starting point in the heap, responsive to determining that a first slot is not reachable.

Abstract: A device may receive error data indicating that an error occurred, the error being associated with a data processing job scheduled to be performed by a data processing platform. The device may identify input data for the data processing job associated with the error and determine that the error is based on the data processing platform not receiving the input data. In addition, the device may determine a location of the input data and determine a measure of priority associated with the data processing job. Based on the location of the input data and the measure of priority, the device may perform an action to correct the error.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: Systems and methods are disclosed for storing codewords in NAND memory. The method includes receiving a first and second codeword. The method includes storing a partition of the first codeword and a partition of the second codeword in a buffer. The method includes transferring the partition of the first codeword and the partition of the second codeword to a page in NAND memory.

Abstract: A data storage device comprises a nonvolatile semiconductor storage array containing data, a controller in communication with the nonvolatile semiconductor storage array, and a buffer containing RAID units, the RAID units being in communication with the nonvolatile semiconductor storage array via the controller. The controller is configured to receive write requests from a host device, and accumulate first data relating to the write requests in the RAID units. The controller is also configured to, concurrently, transfer the first data contained in the RAID units to the nonvolatile semiconductor storage array, calculate parity values of the first data contained in the RAID units, each parity value relating to each write request, and accumulate the parity values in a context identifier buffer. The controller is further configured to associate context identifiers with the parity values, and store the parity values and the context identifiers in the nonvolatile semiconductor storage array.

Abstract: A method for execution by a computing device of a dispersed storage network (DSN) to generate memory mapping of logical DSN addresses to storage units of the DSN. The method begins by equally dividing a namespace among groups of storage units of the DSN to produce a set of namespace sections. The method continues by for a first group of storage units, determining storage capacity for each storage unit of the first group of storage units, determining a total storage capacity for the first group of storage units, for a storage unit of a first group of storage units, determining a namespace fraction based on the storage capacity of the storage unit of the first group of storage units and on the total storage capacity and allocating a portion of the first namespace section based on the namespace fraction to the storage unit of the first group of storage units.

Abstract: A computing device includes an interface to communicate with a dispersed storage network (DSN), a memory, and a processing module. The computing device receives less than a decode threshold number of encoded data slices (EDSs) of a set of EDSs corresponding to a data object. The computing device also receives, from the second wireless communication system, at least one remaining EDS corresponding to the set of EDSs. the computing device combines the less than the decode threshold number of EDSs of the set of EDSs and the at least one remaining EDS to generate at least the decode threshold number of EDSs of the set of EDSs corresponding to the data object. The computing device dispersed error decodes the at least the decode threshold number of EDSs of the set of EDSs corresponding to the data object to reproduce the data segment of the plurality of data segments.

Abstract: A system, method, and computer readable medium for asynchronous live migration of applications between two or more servers. The computer readable medium includes computer-executable instructions for execution by a processing system. Primary applications runs on primary hosts and one or more replicated instances of each primary application run on one or more backup hosts. Asynchronous live migration is provided through a combination of process replication, logging, barrier synchronization, checkpointing, reliable messaging and message playback. The live migration is transparent to the application and requires no modification to the application, operating system, networking stack or libraries.

Abstract: The present subject matter relates to storage systems. In an example method, a write request is received from a computing device in a data backup mode. Data associated with the write request is written to a primary storage drive of a storage system when the write request is for an unallocated block of the primary storage drive. The data associated with the write request is written to a secondary storage drive of the storage system when the write request is for an allocated block of the primary storage drive.

Abstract: One or more techniques and/or systems are provided for profiling a dataset. For example, a snapshot of a volume may be evaluated to identify a set of data characteristics, such as file and directory size information. A baseline dataset profile of a dataset of data within the volume may be constructed based upon the set of data characteristics. Histograms and graphs of directory counts and file counts may be constructed based upon the baseline dataset profile. An incremental dataset profile may be constructed for the dataset based upon an evaluation of the snapshot and a subsequent snapshot of the volume. Histograms and graphs of directories and files that are modified, created, and/or deleted may be constructed based upon the incremental dataset profile. Performance predictions, analytics, field diagnostics of performance issues, and/or scheduling of service execution may be implemented for a storage network hosting the volume based upon dataset profiles.

Abstract: Examples include the acquisition of objects names for portion index objects. Some examples include acquisition, from a remote object storage system, of a list of object names for a plurality of portion index objects, stored in the remote object storage system. In some examples, for each of the portion index objects, the acquired object name includes an identifier of an associated deduplicated backup item and information identifying a data range of the associated deduplicated backup item that is represented by metadata of the portion index object.

Abstract: Systems and methods for backup data security classification. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include one or more processors and a memory coupled to the one or more processors, the memory including program instructions stored thereon that, upon execution by the one or more processors, cause the IHS to: receive a backup policy that includes a plurality of backup profiles, where each of the plurality of backup profiles corresponds to a different user within an organization, and store a copy of electronic data associated with a given one of the different users according to a backup profile.

Abstract: The present disclosure is related to systems and methods for scheduling and managing series of snapshots. An example method can include estimating a transfer time to transfer a first snapshot of a virtual computing instance (VCI) to a first snapshot series, and estimating a transfer time to transfer a second snapshot of the VCI to a second snapshot series. The method can further include determining a first schedule time to start a transfer of a first series of snapshots and determining a second schedule time to start a transfer of a second series of snapshots, wherein the first schedule time and the second schedule time are based at least in part on a respective recovery point objective (RPO). In some embodiments, the method can further include scheduling a point in time to record a next snapshot based at least in part on the shorter schedule time of the first schedule time and the second schedule time.

Abstract: A first hardware island is defined as including at least a first compute cluster. First backup infrastructure is associated with the first compute cluster. A second hardware island is defined as including at least a second compute cluster. Second backup infrastructure is associated with the second compute cluster. A partnership is established between the first and second compute clusters. A selection of a backup policy to be associated with a workload is received. The workload is provisioned to the first compute cluster for processing and the selected backup policy is provided to the second backup infrastructure.

Abstract: Techniques for synchronizing snapshot operations in a distributed consistency group of storage volumes. The disclosed techniques employ a schedule of discrete snapshot operations (e.g., pausing I/O requests from host computers, taking snapshots of storage volumes, un-pausing the I/O requests), which is provided to storage appliances storing the storage volumes within the distributed consistency group. By pre-scheduling such discrete snapshot operations to be performed by the storage appliances, an amount of real-time communications (e.g., issuing snapshot commands, receiving snapshot acknowledgements) required to complete the snapshot operations is reduced, allowing data storage systems to more easily satisfy I/O time-out requirements and avoid application unresponsiveness and/or crashes.

Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnosed result.

Abstract: An apparatus in one embodiment comprises a storage system including a plurality of storage nodes each associated with one or more storage devices. The storage system is configured to provide at least one virtual volume distributed over the storage nodes for utilization by a plurality of host devices. The storage nodes are configured to support selection between multiple operating modes for handling input-output operations directed to the distributed virtual volume by the host devices. The multiple operating modes comprise at least a cached mode of operation in which consistency across the storage nodes for the distributed virtual volume when accessed by different ones of the host devices is ensured utilizing a distributed cache coherence protocol implemented by cooperative interaction of cache controllers of respective ones of the storage nodes, and a cacheless mode of operation in which consistency is ensured without utilizing the distributed cache coherence protocol and its associated cache controllers.

Abstract: A computing system providing high-availability access to computing resources includes: a plurality of interfaces; a plurality of sets of computing resources, each of the sets of computing resources including a plurality of computing resources; and at least three switches, each of the switches being connected to a corresponding one of the interfaces via a host link and being connected to a corresponding one of the sets of computing resources via a plurality of resource connections, each of the switches being configured such that data traffic is distributed to remaining ones of the switches through a plurality of cross-connections between the switches if one of the switches fails.

Abstract: Establishing a synchronous replication relationship between two or more storage systems, including: identifying, for a dataset, a plurality of storage systems across which the dataset will be synchronously replicated; configuring one or more data communications links between each of the plurality of storage systems to be used for synchronously replicating the dataset; exchanging, between the plurality of storage systems, timing information for at least one of the plurality of storage systems; and establishing, in dependence upon the timing information for at least one of the plurality of storage systems, a synchronous replication lease, the synchronous replication lease identifying a period of time during which the synchronous replication relationship is valid.

Abstract: A technique for managing RAID (Redundant Array of Independent Disks) storage includes maintaining active-stripe metadata that stores, for each of multiple stripes that have been written by a RAID system, an entry that identifies the stripe and identifies a respective configuration plan in effect a last time the stripe was written. In response to a disk drive failure, the technique further includes generating a set of new plans that specify disk drive elements to be used in place of damaged ones and performing a selective repair operation. The selective repair operation iterates over a set of entries in the active-stripe metadata, performs a comparison between the identified plan for each stripe and a current plan implemented by the RAID system for writing to that stripe, and repairs the stripe when the identified plan and the current plan are different.

Abstract: A warning circuit is configured to output a warning in response to an integrated graphics card unit being coupled to a display screen and a discrete graphics card being coupled to a first connector. The first connector is configured to output a coupling signal in response to the discrete graphics card being coupled to the first connector. The integrated graphics card unit is configured to output a control signal in response to the integrated graphics card unit being coupled to the display screen. The warning circuit includes a controller that controls the discrete graphics card to convert display data to drive the display screen in response to receiving the coupling signal. The warning circuit is configured to output the warning in response to receiving the control signal and the coupling signal.

Abstract: Systems and methods are described for monitoring code execution within an on-demand code execution environment or other distributed code execution environment. The distributed, asynchronous nature of such environment can make determining the interactions between code executions difficult relative to traditional, non-distributed systems. The present disclosure enables the interrelations between code executions to be monitored by injecting monitoring information into the calls between those code executions. The monitoring information may be propagated through calls, such that a “path” or “trace” of code executions and calls can be determined. Data generated based on the monitoring information can be used to generate a profile for a set of code, so that a developer or other user may easily debug or optimize execution of the code.

Abstract: The invention is directed to a computer-implemented method and system for improving processing performance for a group of computing resources, the method implemented on at least one computer having a processor and accessing at least one data storage area. The method comprises implementing the processor for calculating a benchmark for each computing resource in the group of computing resources and normalizing the benchmark across the group of computing resources to determine a number of performance units for each computing resource. The method additionally includes providing a graphical user interface for facilitating visual comparison for comparing processing performance indicators for multiple computing resources in the group of computing resources and reconfiguring at least some of the computing resources represented on the graphical user interface based on the comparison.

Abstract: A computer-implemented method that includes monitoring execution of program code by first and second processor components. A computing system detects that a trigger condition is satisfied by: i) identifying an operand in a portion of the program code; or ii) determining that a current time of a clock of the computing system indicates a predefined time value. The operand and the predefined time value are used to initiate trace events. When the trigger condition is satisfied the system initiates trace events that generate trace data identifying respective hardware events occurring across the computing system. The system uses the trace data to generate a correlated set of trace data. The correlated trace data indicates a time ordered sequence of the respective hardware events. The system uses the correlated set of trace data to analyze performance of the executing program code.

Abstract: Embodiments disclosed herein provide for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to track a non-precise event and to increment upon occurrence of the non-precise event, wherein the non-precise event comprises a first type of performance event that is not linked to an instruction in an instruction trace. The processing device also includes a first handler circuit to generate and store a first record, the first record comprising architectural metadata defining a state of the processing device at a time of generation of the first record, wherein the first handler circuit to generate records corresponding to precise events. The processing device further includes a second handler circuit communicably coupled to the first handler circuit, the second handler circuit to cause the first handler circuit to generate a second record for the non-precise event upon overflow of the performance counter.

Abstract: Systems and methods are provided for implementing an automated parallel deployment solution. Embodiments of the invention described herein prevent defects from being introduced in a production environment, or those that could be introduced in a production environment, by parallel log monitoring of existing and new state systems. One or more systems may be created in parallel to the production system to detect and fix defects. In embodiments of the invention, as existing defects are captured and resolved by the automatic defect resolution system and method, these defects will not impact production any further. Thus, the automatic defect resolution system drives out all production defects over a window of time, requiring less and less maintenance over time. Once a given detect is fixed, the corresponding change is applied to the production environment to avoid future similar defects.

Abstract: A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which the application code includes a prefixed instruction to be modified by a prefix, a trap is provided. The trap is configured to report a presence of the prefix, but to otherwise perform the trap functions absent the prefix; i.e., the prefix is otherwise ignored in the processing of the trap.

Abstract: A method, system and program product for printer driver management in an enterprise network. Each requested printer driver is tested in a controlled environment to determine if the driver is compatible with at least one other driver in a set of drivers. The tested printer driver is conditioned for inclusion in a central repository that stores a plurality of sets of versioned drivers, if the printer driver is determined to be compatible. The tested driver and at least one associated file are packaged and stored in the central repository. The tested driver and associated file are deployed to at least one server hosting a distributed file share. The tested driver and associated file are downloaded to at least one print server. Driver files are touched with a date and time stamp so that workstations will automatically download updated printer drivers from the print server.

Abstract: Embodiments include method, systems and computer program products for protecting against unintentional command re-execution. The method includes applying a shell wrapper to a shell history in which the shell history includes one or more commands. The method further includes analyzing each of the one or more commands in the shell history using the shell wrapper. The method further includes disabling an ability to re-execute one or more commands in the shell history based on a determination that the one or more commands in the shell history are determined to be potentially dangerous.

Abstract: A user interface (“UI”) code coverage system and process determines the coverage by test code of UI Components in a computer program. In other words, the UI code coverage system and process determine whether the test code tests a UI Component. In at least one embodiment, the UI code coverage system and process identify the particular UI Components tested by the test code, provide coverage (i.e. tested) statistics, provide a visualization of the UI Component tested, provide a visualization of tested and not-tested (also referred to respectively as “covered” and “not covered”) UI Components of a UI Screen.

Abstract: Dynamically scheduled testing of a software application on one or more devices are disclosed. The system can schedule and execute of one or more test cases associated with a software application. When a device becomes available for testing, the system can determine the list of commits that have not yet been tested. If there are outstanding untested commits, the system can determine the list of test cases in a test plan that are to be scheduled and executed. For each test in the list of test cases, the system can compute an urgency value. Urgency value can be a function of the untested commits. For example, urgency value can be the number of untested commits associated with each test case. The system can then sort the test cases based on the urgency value and schedule the most “urgent” test case for execution.

Abstract: Example implementations relate to composing future tests. Some implementations may include a data capture engine to capture data points during test executions of the application under test. The data points may include, for example, test action data and application action data. Additionally, some implementations may include a data correlation engine to correlate each of the data points with a particular test execution of the test executions, and each of the data points may be correlated based on a sequence of events that occurred during the particular test execution. Furthermore, some implementations may also include a test composition engine to compose, based on an interaction with a visualization of results of a verification query of the correlated data points, a future test of the application under test.

Abstract: Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.

Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving a memory access latency value including a time to perform an operation with respect to the memory bank of the plurality of memory banks, receiving a set of operation percentages including an operation percentage for each of a plurality of operations performed on the memory bank, determining a probability associated with the memory access latency value using a mixture of Weibull distributions, described herein, comparing the probability to a threshold probability to provide a comparison, and selectively executing at least one action with respect to the memory bank based on the comparison.

Abstract: A method for obtaining and storing monitoring information. The method includes one or more computer processors generating a plurality of data records, based at least in part on a configuration for generating information, wherein the plurality of data records includes a first data record. The method further includes determining that a configuration for analyzing information dictates an analysis of at least a one data record, wherein the at least one data record includes a second data record. The method further includes determining that the plurality of data records do not include the second data record. The method further includes modifying the configuration for generating information to include generating the second data record. The method further includes generating an updated plurality of data records based on the modified configuration for generating information, wherein the updated plurality of data records includes the first data record and the second data record.

Abstract: A method and an apparatus for performing memory space reservation and management are provided, wherein the method is applied to a server system. The method includes: providing a mount point at a file system of a server in the server system, and creating a file at the mount point to occupy partial memory space of a physical memory; mapping the file to a section of virtual memory addresses to prevent any swap operation from being applied to the partial memory space; and updating file information of the file into a memory space management list to dynamically manage the partial memory space.

Abstract: Reusing data in a memory. A method includes determining to revalidate a first set of data stored in a first, invalidated, portion of the memory. An amount of data in a second set of data in the free portion of the memory that will also be revalidated by revalidating the first portion of the memory is determined. As a result, an action to perform is determined and performed. The action includes either revalidating the first portion of the memory if the amount of data in the second set of data is at or below a predetermined threshold or copying the first set of data in the first portion of the memory, and re-writing the first set of data to the active valid portion of the memory, if the amount of data in the second set of data is above the predetermined threshold.

Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for destaging cached data. A method includes caching write in a nonvolatile solid-state cache by appending the data to a log of the nonvolatile solid-state cache. The log includes a sequential, log-based structure preserved in the nonvolatile solid-state cache. A method includes destaging at least a portion of the data from the nonvolatile solid-state cache to the backing store in a cache log order. The cache log order comprises an order in which the data was appended to the log of the nonvolatile solid-state cache.

Abstract: According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed.

Abstract: A method for elective garbage collection in storage memory, performed by a storage system is provided. The method includes monitoring storage space available in each of a plurality of portions of storage memory of a storage system and detecting an imbalance in the storage space available across the plurality of portions of storage memory. The method includes performing garbage collection to rebalance the space available across the plurality of portions of storage memory, responsive to the detecting. A storage system is also provided.

Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.

Abstract: A computing apparatus, including at least one general computing core circuit, an internal interface circuit, an external interface circuit, a cache coherence engine circuit, and a protocol conversion circuit. The computing apparatus is coupled to an internal apparatus using the internal interface circuit, and is coupled to an external apparatus using the external interface circuit. When working in a first mode, the cache coherence engine circuit implements cache coherence between the computing apparatus, the internal apparatus, and the external apparatus, and in this case, the computing apparatus is used as a node controller. When working in a second mode, the cache coherence engine circuit processes only cache coherence between the computing apparatus and the internal apparatus, and the external interface circuit is used as a network interface circuit.

Abstract: A method comprises: receiving input data comprising a number of read and write uncached transactions, a transaction density, a number of active cores (N active cores) of the at least two cores, main memory address layout, and number of and an identifier for each of: banks and ranks in main memory, interconnects, cache pools, and memory controllers; defining all sets of active cores; defining up to N sets of memory pools; performing, for combinations of at least one set of active cores with each of at least one subset, the specified number of read and write uncached transactions with main memory at a specified transaction density for each defined combination of each active core combination and each defined memory pools; measuring the execution time of such performance for each combination; storing the execution time for each combination; and identifying at least one combination having a lower execution time.