Abstract: A data processing system includes a processor and a cache controller coupled to the processor, and adapted to be coupled to a memory. The cache controller uses the memory to form a pseudo direct mapped cache having a plurality of groups of pages. The memory forms a first number of selected pages, including a first page for storing a plurality of sets of tags and a plurality of remaining pages for storing data. Each tag, of the plurality of sets of tags, stores tags for respective entries in a corresponding one of the plurality of remaining pages.

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

Abstract: A caching system and methodology for data in a memory for faster access to commonly-used data by other applications and computer devices on a network. The memory can include a solid-state drive (SSD) array for the cache memory that has read-bias, in addition to a magnetic hard drive array. The system uses a logical set of slots to hold identifiers for specific groups of data that can be placed into cache memory and each identifier has a usage attribute that changes based upon the usage of the specific group of data and causes the identifier to move within the set of slots and potentially into cache memory.

Abstract: Methods and apparatus for a content-based deduplicated storage system for generating an address to hash (A2H) value for a control module as data blocks are received and generating, for a data module, hash to physical (H2P) values corresponding to the A2H values. A first cache can be provided for the control module, where the first cache can comprise an address value, a hash value, and physical location information. A second cache can be provided for the data module, where the second cache can comprise a bucket value, a hash value, and a filter mechanism, where the filter mechanism is configured to determine whether the hash value is present.

Abstract: A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and while each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.

Abstract: The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.

Abstract: A fast snap is a consistent point-in-time copy or logical copy of a storage object that can be created more quickly than an ordinary snap. In order to generate a fast snap a storage array creates a copy or logical copy of all of the dirty data associated with a source device by copying or logically copying dirty pages cache into a separate record in volatile memory, instantiates an unpopulated snap device that is backed by persistent storage, and generates a mapping between the record and the unpopulated snap device. The mapping includes the information needed to populate the unpopulated snap device with the dirty pages from the record. Once the fast snap has been created it is possible to service IOs to the source device and the fast snap device because the data can be accessed from the record and the cache.

Abstract: A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.

Abstract: Examples disclosed herein provide the ability for a non-system application to gain controlled access to a persistent memory region of a computing device. In one example method, the computing device creates a group identifier that has permission only to a specific location under the persistent memory region. The computing device registers the non-system application to the group identifier, and adds a certificate associated with the non-system application to a mandatory access control (MAC) permission list. Upon adding the certificate to the MAC permission list, the computing device defines MAC permissions to the non-system application, with regards to accessing the specific location under the persistent memory region.

Abstract: An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

Abstract: In a control apparatus which uses a CPU which does not have hardware for memory protection, a function is realized to detect unauthorized writing from a non-safety-related unit program in units of bits, for a safety-related unit data area of a RAM, a safety-related unit register area of an external integrated circuit, and a built-in peripheral I/O register of the CPU. A memory access monitoring unit requests an interrupt process upon detection of a write access of the safety-related unit program permitted to access a safety-related unit region. The interrupt process realizes a function to detect write access from a non-safety-related unit program area by using a program counter of a write access origin retracted to a stack area to judge whether the write access origin is a safety-related unit program or the non-safety-related unit program area, and judge, in units of bits, whether or not there is a change to a safety-related unit region.

Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM) that stores instructions and data, a system interface block, a posted transaction interface block, and an atomics block. Each processor is coupled to the system interface block via its AHB-S bus. The posted transaction interface block and the atomics block are shared resources that a processor can use via the same system interface block. A processor causes the atomics block to perform an atomic metering operation by doing an AHB-S write to a particular address in shared address space. The system interface block translates information from the AHB-S write into an atomics command, which in turn is converted into pipeline opcodes that cause a pipeline within the atomics block to perform the operation. An atomics response communicates result information which is stored into the system interface block. The processor reads the result information by reading from the same address.

Abstract: A data transfer control device includes an acquisition section, an analysis section, a band detection section, a mask output section and a selection section. The acquisition section acquires data from a plurality of processing sections for transmitting the data with a transmission path. The analysis section analyzes additional information of the data acquired by the acquisition section. The band detection section detects a transmission band of the transmission path based on the additional information. The mask output section outputs a request mask signal for suppressing the transmission of the data based on the transmission band detected by the band detection section and a target band preset on the transmission path. The selection section selects the data transmitted by the processing section based on the request mask signal output by the mask output section.

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

Abstract: A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.

Abstract: An operation method performed at a nonvolatile memory device may include receiving a program command and an address from an external device through a data signal (DQ), receiving a specific pattern from the external device through the data signal and a data strobe signal (DQS) synchronized with the data signal in a pattern period, receiving user data from the external device through the data signal and the data strobe signal in a data period, and selectively performing a program operation on the user data or a recovery operation based on a determination of whether the specific pattern matches with a particular pattern. A rising edge or a falling edge of the data strobe signal may be aligned with a left edge or a right edge of a window of the data signal in the pattern period.

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.

Abstract: In accordance with these and other embodiments of the disclosure, an information handling system may include a host system comprising a host system processor, a management controller communicatively coupled to the host system processor and configured to provide management of the information handling system via management traffic communicated between the management controller and a dedicated management network external to the information handling system, and a cryptoprocessor having a first communications interface to the host system and a second communications interface to the management controller and configured to carry out cryptographic operations on data communicated to the cryptoprocessor from the host system and the management controller such that the cryptoprocessor is accessible to the host system and the management controller.

Abstract: A system comprises a data storage, a decompression accelerator configured to decompress compressed data and thereby generate decompressed data, and a direct memory access (DMA) engine coupled to the data storage and the decompression accelerator. The DMA engine comprises a buffer for storage of a plurality of descriptors containing configuration parameters for a block of compressed data to be retrieved from the data storage and decompressed by the decompression accelerator, wherein at least one of the descriptors comprises a threshold value. The DMA engine, in accordance with one or more of the descriptors, is configured to read compressed data from data storage and transmit the threshold value and the compressed data to the decompression accelerator. The decompression accelerator is configured to decompress the compressed data until the threshold value is reached and then to abort further data decompression and to assert a stop transaction signal to the DMA engine.

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

Abstract: Systems and methods for improvement in bus communications with daisy-chained connected devices are described herein. In some embodiments, a bus communication system comprises a master chain controller, a first peripheral device, and a second peripheral device. A first communication bus couples a master interface port of the master chain controller to a slave interface port of the first peripheral device, and a second communication bus couples a master interface port of the first peripheral device to a slave interface port of the second peripheral device. The first communication device is configured to receive a communication packet via the first communication bus and to send a copy of the communication packet to the second peripheral device during transmission of the communication packet to the first peripheral device. The first communication device is also configured to send an idle state signal to the master chain controller.

Abstract: An electronic device includes a connector, a first communication circuit connected with the connector, a second communication circuit connected with the connector, and a processor. The processor is configured to verify identification information corresponding to an external electronic device connected with the electronic device through the connector, to receive or transmit, if the external electronic device is an electronic device of a first type, data from or to the external electronic device through the first communication circuit and the second communication circuit based on the identification information, and to receive or transmit, if the external electronic device is the electronic device of a second type, data from or to the external electronic device through the first communication circuit based on the identification information.

Abstract: A storage drive adapter may comprise an adapter board, which may include a first and second carrier module interface to removably engage with a first and a second storage drive carrier module, respectively. The adapter board may further include a dual ported storage drive connector to engage with a complementary storage drive bay interface. The dual ported storage drive connector may include a first port to provide a first signal path from the complementary storage drive bay interface to the first carrier module interface. Similarly, the dual ported storage drive connector may also include a second port to provide a second signal path from the complementary storage drive bay interface to the second carrier module interface.

Abstract: A method to provide transfer of data without the use of a network from an application program to an embedded device. A routing service establishes a communication channel without the use of a local area network. The routing service then manages the control of this communication channel for the transfer of data and closes the channel in an appropriate period.

Abstract: An information processing apparatus is connected through a plurality of paths to a plurality of controllers included in a storage device and includes a processor. The processor is configured to issue, to the storage device, an inquiry about a recommended path through which a data access command is to be issued to the storage device. The processor is configured to compare a delay predictive time with a response predictive time in regard to the data access command. The delay predictive time is a predictive value of a delay time due to a data communication using an inter-controller communication between the plurality of controllers. The response predictive time is a predictive value of a response time when the inquiry is issued to the storage device. The processor is configured to suppress the issuance of the inquiry when the response predictive time is equal to or longer than the delay predictive time.

Abstract: Described are systems, methods and computer-program product for replacing a prior input/output (I/O) module and terminal board with a universal I/O device by providing software based instructions and configuration settings for the installer. The method includes provisions for new wiring changes or harnesses as well as preset adapters, converting prior device configuration settings from an I/O module, pack, and/or terminal board to new configuration settings for a programmable I/O device, generating a wiring chart for any wiring changes based on the settings, and displaying the information for the installer and/or programmer's use. This allows a universal I/O device capable of each channel having different operating modes to replace one or more of a mixture of several types of dedicated I/O modules.

Abstract: One embodiment is directed to a method of tracking, using an automated infrastructure management (AIM) system, connections made using a breakout cable. The breakout cable comprises a plurality of breakout connectors at a breakout end of the breakout cable. The method comprises identifying a sequence for adding or removing connections involving the breakout connectors of the breakout cable, identifying events associated with adding or removing connections involving the breakout connectors of the breakout cable, and associating the breakout connectors of the breakout cable with added or removed connections based on the identified sequence and the identified events. Other embodiments are disclosed.

Abstract: A solution to the technical problem of improving device-to-device connection speeds includes the use of single-wire communication (SWC). Unlike the two differential wires required in transmission lines, SWC includes a transmission method using a single wire for data without requiring a return wire. The use of SWC has the potential to enable low loss channels of increasingly high bandwidth. The SWC improvements in bandwidth and frequency enable a significant reduction of power required for communication. SWC provides significant improvement in speed for each channel, so fewer wires may be used for each device-to-device connection. SWC also provides the ability to convey increased bandwidth and increased power over each wire, which further reduces the number of wires needed to provide power and communication.

Abstract: In one example implementation according to aspects of the present disclosure, a server chassis may include a server zone to receive a plurality of blade servers, each of the plurality of blade servers having a fabric connection. The server chassis may further include a flexible input/output zone to receive an input/output card, the input/output card being communicatively coupled to each of the plurality of blade servers via the fabric connection of each of the plurality of blade servers. The functionality of the input/output card may be distributed across the plurality of blade servers.

Abstract: Present disclosure relates to a method for managing a docking device and the docking device thereof. The docking device is configured with a processor and at least two coupling ports. The method comprises following steps: electrically coupling a computer and/or at least one peripheral device to the at least two coupling ports respectively; retrieving a plurality of characteristic profiles by the processor, wherein each of the characteristic profiles is retrieved from each of the at least two coupling ports; receiving, by the processor, an input signal from the computer or the at least one peripheral device; and changing the characteristic profiles based on the input signal by the processor.

Abstract: This application relates to methods and apparatus for configuring a serial data interface, especially a data interface (300) for a transducer (324) such as a digital microphone or loudspeaker. The data interface is selectively operable in a first or second serial data mode of operation for input of data to or output data from the transducer device. The first and second serial data modes are different, e.g. correspond to different serial formats. The data interface has a controller (330) configured to determine a resistance value (331, 332) at a sense terminal (314) of the transducer device and to control the data interface in the first serial data mode if the resistance value is within a first resistance range and control the data interface in the second serial data mode if the resistance value is within a second, different, resistance range.

Abstract: A universal serial bus (USB) link bridge device is disclosed. The USB link bridge device includes a host side module configured to be interfaced with a USB host. The host side module includes a receiver and is configured to receive serial data from the USB host, convert the received serial data into parallel data and store the parallel data into an elasticity buffer. A data controller coupled to the host side module is also included. The USB link bridge device further includes a device side module coupled to the data controller and includes a transmitter. The device side module is configured to receive parallel data from the data controller and convert the received parallel data into serial data and to transmit the serial data towards a USB device.

Abstract: A wearable device includes a device carrier, a device core unit, a first universal serial bus (USB) interface, a second USB interface, and a signal path selection unit. The device carrier is configured to carry the device core unit, the first USB interface, the second USB interface, and the signal path selection unit of the wearable device; the device core unit is configured to perform a core function of the wearable device; the first USB interface and the second USB interface are configured to connect to an external device; the signal path selection unit is configured to control a signal path between the first USB interface and the device core unit or a signal path between the first USB interface and the second USB interface to be connected.

Abstract: According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.

Abstract: A mobile computing device is provided. The device includes a first port having a pinout configuration that is configured to support at least one data format, a data source configured to provide data of a second data format that is different from the at least one data format, and a first multiplexer configured to selectively direct data from the data source towards the first port. The pinout configuration is modified to enable the first port to support the second data format.

Abstract: A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.

Abstract: A PCIe device for supporting SRIS includes a transceiver, a clock signal generator configured to generate a second reference clock signal, a connector in a structure to be connected to a PCIe host, and a selection circuit configured to determine whether a first reference clock signal is supplied through the connector and transmit one of the first reference clock signal and the second reference clock signal to the transceiver according to a result of the determination.

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract: A method for copying and transferring data by remote data memory access resulting in faster data transfer speeds is provided. The method includes determining an amount of garbage data of data information, and comparing the amount of garbage data to a threshold amount. In response to the amount of garbage data being below the threshold amount, a first portion of data that includes intended data of the data information and the garbage data is copied to a remote place. In response to the amount of garbage data exceeding threshold amount, a second portion of data that includes only the intended data is copied to the remote place by a scatter/gather input/output method of a remote data memory access protocol. The copied data is returned to a free list of the remote place.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: The invention describes a method of performing automatic commissioning of a network (N) comprising a plurality of network devices (10, 11, 12, 13), wherein each device (10, 11, 12, 13) is characterized by a device identifier (14) and wherein the devices (10, 11, 12, 13) are realized to exchange data packets (2), which method comprises the steps of obtaining a computer-readable installation plan (3) for the network (N), which installation plan (3) comprises a physical location descriptor (31) for devices (10, 11, 12, 13) of the network (N); deducing the network topology (T) of the network (N) from network descriptive information (40, 41, 42, 43) provided by the devices (10, 11, 12, 13) on the basis of data packets (2) exchanged between the devices (10, 11, 12, 13); and comparing the deduced network topology (T) to the installation plan (3) to allocate a physical location descriptor (31) to a device identifier (11).

Abstract: A method of controlling a processor includes receiving from a command buffer a first command corresponding to a first instruction that is processed by a second processing core and starting processing of the first command by the first processing core, storing in the command buffer a second command corresponding to a second instruction that is processed by the second processing core before the processing of the first command is completed, and starting processing of a third instruction by the second processing core before the processing of the first command is completed.

Abstract: A neural network unit (NNU) includes N neural processing units (NPU). Each NPU has an arithmetic unit and an accumulator. First and second multiplexed registers of the N NPUs collectively selectively operate as respective first and second N-word rotaters. First and second memories respectively hold rows of N weight/data words and provide the N weight/data words of a row to corresponding ones of the N NPUs. The NPUs selectively perform: multiply-accumulate operations on rows of N weight words and on a row of N data words, using the second N-word rotater; convolution operations on rows of N weight words, using the first N-word rotater, and on rows of N data words, the rows of weight words being a data matrix, and the rows of data words being elements of a convolution kernel; and pooling operations on rows of N weight words, using the first N-word rotater.

Abstract: A method for file conversion includes obtaining an original file including content, that includes objects. The method further includes rendering each object of the multiple objects into a page description language (PDL) format to obtain rendered objects, and extracting, from the original file, a tag for an object of the multiple objects. The method further includes generating object composition metadata based on a composition rule corresponding to the tag. The object composition metadata includes a description of a composition of the object in the original file, and is added with the rendered objects to a PDL file.

Abstract: A request to open a file from a plurality of files in a storage is received from an application. The storage is made up of an index partition, containing recordings of file system indexes, and a data partition, containing recordings of the indexes and the file system data body. A file descriptor is created with an update flag that references the file. A determination is made that the file is being updated by the application, and the update flag is set to a value representing that the file is being updated. A request to write an index of the file system is received. A determination is made whether a specific file from the plurality of files is being updated. The index is written to the storage with an extended attribute for the specific file indicating that the specific file was being updated at the time the index was written.

Abstract: A request to split a data set comprising observation records located in a group of storage objects is received. With respect to a particular observation record, a token is generated based on an identifier of the record's storage object and a key value of the record. A numeric value is calculated using the token, and the observation record is assigned to a split subset using the numeric value. An indication of the assignment is provided to a destination associated with the split subset.

Abstract: Unique systems, methods, techniques and apparatuses of an industrial control system are disclosed. One exemplary embodiment is an industrial control system including a computing device with non-transitory memory device, a user interface, and a processing device. The processing device is structured to execute a set of instructions stored with the non-transitory memory device so as to determine at least one folder but not all folders of a plurality of first level folders are authorized using a first authorization parameter, determine a plurality of second level folders is a subset of the authorized first level folder, determine at least one folder but not all folders of the plurality of second level folders are authorized using the second authorization parameter, generate a directory of authorized folders including the authorized first level folder and the authorized second level folder; and output the directory of authorized folders to the user interface.

Abstract: The claimed subject matter decreases duplicate entries and loops in an activity record. An exemplary method comprises analyzing a new entry from a user to determine an originating service and a type of activity and extracting an identifying portion of the new entry. The identifying portion includes a predetermined number of characters at a beginning of the entry. Additionally, the predetermined number of characters is based on a likelihood of duplicates in the activity record. The identifying portion is compared to a list of prior entries from the user, and an exclusion action is performed, if the new entry matches one in the list of prior entries. The exclusion action may be to hide the new entry, to delete the new entry, or to collapse the new entry into a matching prior entry.

Abstract: Techniques and systems for completing a database query. A time to complete a synchronous query in response to receiving an original database query is estimated by a database management system provided by one or more computing devices. A synchronous database query corresponding to the original database query is performed with the database management system if the estimated time to complete the synchronous query is less than a pre-selected threshold time. One or more asynchronous queries corresponding to the original database query are performed with the database management system if the estimated time to complete the synchronous query is greater than the pre-selected threshold time. A result, whether from a synchronous query or one or more asynchronous queries, is stored in an object within a non-relational database system.

Abstract: Data or one or more operations can be provided, based on one or more characteristics associated with the data and/or operations, to a designated computing group or pool of computing resources designated for handling the data and/or operations with the particular data characteristic(s). The designated computing group can, for example, be one of multiple computing groups in the same system or device. As such, all of the computing groups can still function together in the same system or device, for example, in parallel. However, each one of the multiple computing groups can, for example, be defined or predefined to include one or more computing resources that are more suitable for storing and/or processing data with one or more data characteristics or handle operations with one or more determined characteristics.