Abstract: Between a power supply potential and a reference potential, a first PMOS transistor and a first NMOS transistor are connected in series via an inverting output node and a second PMOS transistor and a second NMOS transistor are connected in series via a non-inverting output node. A third NMOS transistor is connected in parallel to the first NMOS transistor and a fourth NMOS transistor is connected in parallel to the second NMOS transistor. A gate of the first PMOS transistor and a gate of the third NMOS transistor are connected to the non-inverting output node and a gate of the second PMOS transistor and a gate of the fourth NMOS transistor are connected to the inverting output node. The first and second NMOS transistors receive a non-inverted signal and an inverted signal of an input signal at their gates, respectively.

Abstract: A level shifter circuit which includes a cross-coupled latch and a set-reset latch is introduced. The level shifter circuit includes a first input node, a second input node and a plurality of switches. The first input node and the second input node are configured to receive a first digital input signal and a second digital input signal, respectively. The plurality of switches are configured to be switched on or off according to at least one control signal to output a first output signal and a second output signal. The set-reset latch is coupled to the cross-coupled latch and includes a set input node, a reset input node and an output node. The set input node and the reset input node are configured to receive the first output signal and the second output signal of the cross-coupled latch, respectively. The output node outputs a level-shifted output signal according to the first output signal and the second output signal of the cross-coupled latch. A method adapted to a level shifter circuit is also introduced.

Abstract: According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output ( ( ( a ? b ) ? ( p 1 ? a ) ? ( p 2 ? b ) ) _ ? ( p 3 ? b ? a ) ) ? ( a ? b ? p 4 ) _ .

Abstract: A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.

Abstract: A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.

Abstract: An apparatus for rectifying a resolver output signal may include: a resolver configured to receive an excitation signal and to output a resolver output signal based on the excitation signal, the excitation signal indicating a position of a rotor of a motor; a microprocessor configured to receive a reference rectification signal generated by rectification of the excitation signal and to output a delay signal by delaying the reference rectification signal according to a preset value; and a delay amount detection circuit configured to receive a reference excitation signal generated by rectification of the resolver output signal, to receive the delay signal from the microprocessor, to compare the reference excitation signal with the delay signal, and to output a phase difference detection signal and a delay amount excess/shortage signal to the microprocessor.

Abstract: Disclosed is a gray code generator. The gray code generator includes a counter that counts first to fourth digital bits in response to a clock signal, and a converter that converts the first to fourth digital bits to first to fourth gray bits. The counter includes a replica flip-flop that outputs the clock signal as the first digital bit, a first flip-flop that inverts the second digital bit in response to the clock signal to output the second digital bit, a second flip-flop that outputs a high level in response to the clock signal when a second inverted digital bit is different from a third inverted digital bit, and a third flip-flop that outputs the high level in response to the clock signal when a result of performing a NOR operation on the second and third inverted digital bits is different from a fourth inverted digital bit.

Abstract: A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.

Abstract: A phase-lock-loop (PLL) circuit includes a reference PLL circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference PLL circuit, and configured to distribute the reference clock signal; and a plurality of designated PLL circuits coupled to the clock tree circuit, wherein the designated PLL circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.

Abstract: A enhanced DLL includes a delay chain, a phase detector and a delay control unit. The delay chain is arranged to delay a reference clock signal to generate a delayed reference clock signal and reflect the delay control setting on the delayed reference clock signal, wherein the delay chain is periodically reset according to a period of the reference clock signal. The phase detector is coupled to the delay chain, and arranged to detect a phase shift between the delayed reference clock signal and the reference clock signal, thereby to generate a control value. The delay control unit is coupled to the delay chain and the phase detector, and arranged to adjust the delay control setting based on the control value.

Abstract: A digital frequency-division phase-locked loop, including a time-to-digital converter (TDC), a digital loop filter (DLF), a digital-controlled oscillator (DCO), a feedback frequency divider (DIV), a sigma-delta modulator (SDM), and a calibration apparatus, where the calibration apparatus compensates for, based on a frequency control word and a frequency-division control word generated by the SDM, a digital signal output by the TDC to obtain a calibration signal. The DLF performs digital filtering on the calibration signal to obtain an oscillator frequency control signal and set the oscillator frequency control signal as an output signal of the DCO.

Abstract: Methods and systems are provided for calibrating voltage-controlled oscillators (VCOs). frequency control information, relating to output frequency of a VCO, which varies based on changes in operational conditions, may be determined. The frequency control information enables indicating the output frequency within a range of allowable values for control inputs and a range of expected values based on the operational conditions. For each control input setting, calibration control information for a calibration voltage associated with a control input, may be determined, based on the frequency control information, with respect to the operational conditions, to generate a constant output frequency. The operational conditions may be assessed, and a calibration voltage corresponding to the assessed operational conditions may be determined.

Abstract: The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator.

Abstract: Pipelined analog-to-digital converters (ADCs) include a flash ADC that reduces noise tones in power supply current drawn by the flash ADC. A pipelined analog-to-digital converter (ADC) includes a flash ADC and error correction circuitry coupled to the flash ADC. The flash ADC includes a plurality of latched comparators and a plurality of driver circuits. Each of the latched comparators includes an inverting output and a non-inverting output. Each of the driver circuits is coupled to one of the latched comparators, and includes an input terminal and an output terminal. In a first subset of the driver circuits the input terminal is coupled to the inverting output of one of the latched comparators. In a second subset of the driver circuits the input terminal is coupled to the non-inverting output of one of the latched comparators.

Abstract: An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.

Abstract: A peak/bottom detection circuit is disclosed. A comparator compares a voltage of one of three or more capacitors with an input voltage. A calculation amplifier amplifies the voltage of one of the three or more capacitors. Each of three or more switches respectively corresponding to the three or more capacitors connects a corresponding capacitor among the three or more capacitors to one of the comparator, the calculation amplifier, and a source of the input voltage. A controller generates control signals for sequentially switching connection destinations of the three or more capacitors and to supply the control signals to the three or more switches, respectively, in which the connection destinations of three capacitors among the three or more capacitors are different from each other.

Abstract: An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.

Abstract: The present disclosure provides a simplified, multiple-gain, front-end circuit for analog-to-digital converter systems. In an example, a front-end circuit for an analog-to-digital converter (ADC) can include first and second input amplifiers configured to receive an input signal, and a gain selection circuit coupled to the first input amplifier and the second input amplifier; the gain selection circuit comprising a plurality resistor strings, each resistor string including a plurality of resistors coupled in series, and wherein each string includes a first end node coupled to an output of the first input amplifier and a second end node coupled to an output of the second input amplifier.

Abstract: A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n?1, the value of si corresponds to a range of the ith partition.

Abstract: Aspects of the disclosure can relate to a process for transmitting a pump-off pressure profile for formation integrity testing within a limited bandwidth. For example, a process may include measuring pump-off pressure data. The pump-off pressure data represents the pump-off pressure profile. The method also includes determining, from the pump-off pressure data, a pump-off pressure data portion corresponding to a formation integrity testing characteristic. The method also includes compressing pump-off pressure data portion with a compression protocol to produce compression bits. The compression bits representing the pump-off pressure data portion corresponding to the formation integrity testing characteristic. The method also includes transmitting, via a communication module, the compression bits to a computing device.

Abstract: A data compression system can include a compression unit comprising a single chaotic system having an identified initial condition that produces a desired output sequence of data corresponding to a data set being stored. The single chaotic system can be identified using a chain of controlled nonlinear systems and a dynamical search technique to match the output, in sequence over consecutive time intervals with the chain of the controlled nonlinear systems.

Abstract: Methods and systems for storing data includes inflating received data having a first compression format. Blocks are created from the inflated data for a second compression format. The blocks are compressed in the second format using a processor. The contents of the blocks are verified concurrently with compressing the blocks. Compression is aborted if the verification of the contents fails. An output of the compression is stored if verification of the contents succeeds and storing the received data if verification of the contents fails.

Abstract: The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields.

Abstract: A method, computer system, and a computer program product for high-speed data compression is provided. The present invention may include receiving an input stream. The present invention may include selecting a header based on the received input stream, wherein the header includes a base, a scheme and a delta count. The present invention may include determining whether there are any remaining values in an uncompressed input stream. The present invention may include reading a first next value from the input stream. The present invention may include determining whether the read first next value is representable with a current base scheme. The present invention may include calculating the delta count based on determining that the read first next value is representable with the current base scheme. The present invention may include writing the calculated delta count to the selected header. The present invention may include incrementing the written delta count.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

Abstract: Techniques for improving the latency or processing performance of an error correction system are described. In an example, the error correction system implements LDPC decoding and uses an early termination rule to determine whether the LDPC decoding should be terminated prior to reaching a maximum number of iterations. The early termination rule involves various parameters that relate to the syndrome of the decoded LDPC codeword at each iteration. These parameters include the number of the current decoding iteration and the weight of the syndrome at the current iteration. For example, the early termination rule specifies that the LDPC decoding should be terminated prior to the maximum number of iterations either when the weight of the syndrome is zero, or when the current number of iterations reaches an iteration number threshold and the weight of the syndrome equals or exceeds a checksum threshold.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input and output (I/O) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. The generation of the write enablement signal may be based on a write signal which may be delayed by a delay time according to whether an error correction operation is performed.

Abstract: A method and apparatus for efficient data decoding is described. Data is encoded by an LDPC encoder using a G matrix. An LDPC decoder uses a modified H matrix to decode encoded blocks of data, the modified H matrix having at least two columns of its circulants swapped with each other. The encoded blocks of data are stored, decoded and reconstructed in an order that considers the circulants in the columns that have been swapped.

Abstract: Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: Systems, methods, and apparatus for enhanced partial processing of satellite user data are disclosed. In one or more embodiments, a disclosed method for processing satellite data comprises encoding with an outer encoder in a transmitting terminal, modulating with a transmit modulator in the transmitting terminal, demodulating with a satellite demodulator in a satellite, encoding with an inner encoder in the satellite, modulating with a satellite modulator in the satellite, demodulating with a receive demodulator in a receiving terminal, decoding with an inner decoder in the receiving terminal, and decoding with an outer decoder in the receiving terminal. In one or more embodiments, the outer encoder and/or the inner encoder is operable to perform forward error correction (FEC) encoding. In at least one embodiment, the outer decoder and/or the inner decoder is operable to perform FEC decoding.

Abstract: Aspects of the invention include calculating, by a transmitter, source cyclic redundancy code (CRC) bits for payload bits. The source CRC bits include source CRC bits for a first type of CRC check and source CRC bits for a second type of CRC check. The source CRC bits are stored at the transmitter. The payload bits and the source CRC bits for the first type of CRC check are transmitted to the receiver. The receiver performs the first type of CRC check based at least in part on the payload bits and the source CRC bits for the first type of CRC check. The receiver also calculates and stores at the receiver calculated CRC bits for the second type of CRC check. If the first type of CRC check indicates an error, a comparison of the source and calculated CRC bits for the second type of CRC check is initiated.

Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.

Abstract: The present disclosure provides methods and systems for mitigating signal noise. In implementations, the systems and methods perform operations including continuously determining an instantaneous power of a signal path. The operations also include determining a dynamic noise threshold by sampling the instantaneous power at different times and selecting a minimum of the instantaneous power sampled during the different times. The operations further include determining that the instantaneous power is less than the dynamic noise threshold. Additionally, the operations include blocking communication from the signal path. Further, the operations include iteratively updating the dynamic noise threshold.

Abstract: A duplexer includes first and second filter circuits and first and second wirings. The first filter circuit allows a signal of a first frequency band to pass therethrough between a first terminal and a common terminal and includes a first resonator which is connected at one end to a line disposed between the first terminal and the common terminal to branch off from the line. The second filter circuit allows a signal of a second frequency band, which is different from the first frequency band, to pass therethrough between a second terminal and the common terminal. The first wiring is connected at one end to the common terminal and is opened at the other end. The second wiring is connected at one end to the other end of the first resonator and is grounded at the other end. The first wiring is electromagnetically coupled with second wiring.

Abstract: A front end module that performs a CA method includes a signal path through which a signal of a first frequency band propagates, a signal path through which a signal of a second frequency band propagates, a switch module that includes antenna terminals and selection terminals and is connected to antenna elements, and a balun that is disposed at the signal path. First and second balanced terminals of the balun are connected to the selection terminals, and the balun causes a fundamental wave or harmonic of a transmission signal of the first frequency band input through an unbalanced terminal to branch into branch signals having opposite phases and outputs the branch signals to the first balanced terminal and the second balanced terminal.

Abstract: A multiway switch, a radio frequency system, and a communication device are provided. The multiway switch is configured to be coupled with an antenna system and a radio frequency circuit. The multiway switch has eight T ports and four P ports. The eight T ports include two first T ports, and each of the two first T ports is coupled with all the four P ports. The antenna system includes four antennas corresponding to the four ports. The multiway switch is configured to implement a function of transmitting a sounding reference signal (SRS) through the four antennas in turn.

Abstract: Systems, devices and methods are disclosed using a transmitter architecture to keep the transmitter in a deep sleep mode before activation/enabling. The transmitter tag comprises a power-good-detector, a first regulator and a second regulator. The power-good-detector includes a power-good-latch, a ring oscillator and a ripple counter. Upon disconnecting a GPIO pin from the ground, the power-good-latch sends a Bias_EN signal to the regulator. Upon receipt of the Bias_EN signal, the first regulator transmits a wakeup signal to the ring oscillator, which then starts sending the clock signals to the ripple counter. When the counted clock signals reach a threshold value, the ripple counter sends the power-good-digital signal to the flip flops. When the tag is in the reset mode, the power-good-digital signal is also low. When the power-good-digital signal goes from low to high, the tag is out of the reset mode.

Abstract: A bias circuit provides additional bias current for power amplifiers during data bursts to compensate for the gain droop caused by a rise in the power amplifier temperature during the data burst. A bias circuit includes a difference amplifier and switches coupled to the difference amplifier. The switches operate the bias circuit in a first mode when a transmit data burst is detected and operate the bias circuit in a second mode after the bias circuit has operated in the first mode for a predetermined period of time. In the first mode, the bias circuit charges a storage capacitor and sets an output current to zero. In the second mode, the bias circuit outputs the output current that increases above the initial value of zero as the PA warms up, where the excursion of this increase of current is determined by a register. The switches disable the bias circuit when the transmit data burst ends.

Abstract: Systems and methods are provided for millimeter-wave (MMW) communication, the system includes a transceiver chip to generate and to receive signals. An interface is used to communicate the signals between the transceiver chip and one or more active antenna modules. The signals include modulated MMW signals and control signals. The transceiver chip includes baseband circuitry, up and down conversion mixers, and RF front-end circuitry. An active antenna module receives a first modulated MMW signal from the interface for transmission via antennas and to receive a second modulated MMW signal from the antennas for transmission through the interface to the transceiver chip.

Abstract: A system and method for improving radio performance through automatic channel selection utilizing a closed-channel model is disclosed. A measurement engine records maximum user throughput on a per station basis during normal traffic operation. The measurement engine further records throughput metrics based on test traffic sent to all associated stations during idle operation. A policy logic engine utilizes the measurements to determine an optimal transmission channel for transmission and receipt of data.

Abstract: Certain aspects of the present disclosure generally relate to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element. In certain aspects, the first inductive element may be coupled in series with the third inductive element. In certain aspects, the circuit also includes a capacitive element coupled in parallel with the fourth inductive element, the capacitive element and the fourth inductive element forming a notch circuit, the notch circuit coupled in series with the second inductive element.

Abstract: A quadrature transmitter includes a first and second matched transmitter path. Each transmitter path receives respective sets of quadrature baseband signals. At least one local oscillator port receives respective sets of quadrature LO signals. Mixer stage(s) respectively multiply the sets of quadrature baseband signals with the respective sets of quadrature LO signals to produce a respective output radio frequency signal. A combiner combines the output RF signals. The first set of quadrature signals is a substantially 45° phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45° phase shifted version of the second set of quadrature LO signals. A baseband error correction circuit corrects a phase error between the quadrature baseband signals at baseband and a LO error correction circuit corrects a phase error between the quadrature baseband signals at a LO frequency.