Abstract: A method of restoring a database across cloud environments is provided. An example method includes receiving, in a second cloud environment from a first cloud environment, first metadata describing a first data version stored in the first cloud environment. The first metadata describes where first data items are located within the first data version stored in the first cloud environment, includes an access procedure or protocol such that the second cloud environment can access the first data items, and includes authorization information necessary to confirm that the second cloud environment is authorized to access the first data items. In response to an instruction, the first data items are restored to the second cloud environment using the first metadata.

Abstract: A unified backup workflow process for different hypervisor configurations of virtual machines on different storage of a cluster leverages RCT-based backup functionality so that backup operations can be performed by a single host of the cluster. The process enables backing up together virtual machines that are local, as well as part of CSV or SMB storage using virtual machine level snapshots as checkpoints rather than volume level snapshots that were traditionally used. Backup data is sent to a backup server as a data stream rather than a file, which avoids the necessity of maintaining chains or structures that identify parent-child disks on the server.

Abstract: Described herein are systems and methods for real-time fault detection in electrical circuits. Various embodiments provide a fault detection circuit that uses a resistor network that is controlled to detect an internal current leak in multiple directions, e.g., to ground or to a power supply. The magnitude of the leakage current may be estimated from voltage measurements at voltage pins. In addition, as part of circuit diagnostics, open and short circuit fault conditions may be identified by using current sources and measuring deflections at the voltage pins.

Abstract: A computer-implemented method includes: monitoring, by a computing device, failover data from one or more high availability stacks, wherein the failover data includes data associated with prior failovers associated with the one or more high availability stacks; scoring, by the computing device, a plurality of prior failovers identified in the failover data; generating, by the computing device, a failover instruction for implementing a failover based on the scoring; and causing, by the computing device, and based on the failover instruction, an application to migrate from a target cluster to a destination cluster.

Abstract: A method for replicating a first virtual storage system of a customer includes receiving periodically collected configuration data, workload data, service failure data, and management workflow data on the first virtual storage system, creating a first multi-dimensional array of observed variables based on periodically collected data, applying dimensionality reduction to the first multi-dimensional array to determine an artificial variable having a largest variance, determining a smaller, second multi-dimensional array that represents the first multi-dimensional array based on the artificial variable, and building a second virtual storage system to replicate the first virtual storage system based on the second multi-dimensional array.

Abstract: The present invention relates to a data processing system for providing business continuity protection, comprising: a business center comprising a first data processing unit, a first pre-communication unit, and at least a first post-communication unit; a disaster recovery center comprising a second data processing unit, a second pre-communication unit, and at least a second post-communication unit; wherein the first pre-communication unit and the second pre-communication unit are communicatively coupled to the first post-communication unit respectively when the business center operates normally; the first pre-communication unit and the second pre-communication unit are communicatively coupled to the second post-communication unit respectively when the disaster recovery center operates in place of the business center. The data processing system can reliably switch between the business center and the disaster recovery center, thereby providing a complete protection for the business continuity.

Abstract: A database cluster architecture based on dual port solid state disk (SSD) is disclosed. The database cluster including a plurality of nodes and a plurality of dual port solid state disks (SSDs). Each dual port SSD of the plurality of dual port SSDs is connected to a unique pair of nodes and each node in the unique pair of nodes is connected to a unique pair of dual port SSDs. A first node of the plurality of nodes writes a transaction log to a first dual port SSD, a second node connected to the first dual port SSD acquires the transaction log from the first dual port SSD and operates a database process to recover data according to the transaction log when the first node crashes.

Abstract: The detection of idle virtual machines through usage pattern analysis is described. In one example, a computing device can collect utilization metrics from a virtual machine over time. The utilization metrics can be related to one or more processing usage, disk usage, network usage, and memory usage metrics, among others. The utilization metrics can be separated into a set of training metrics and a set of validation metrics, and a number of clusters can be determined based on the set of training metrics. The clusters can be used to organize the set of validation metrics into groups. Depending upon the number or overall percentage of the utilization metrics assigned to individual ones of the plurality of clusters, it is possible to determine whether or not the virtual machine is an idle virtual machine. Once identified, idle virtual machines can be shut down to conserve processing resources and costs.

Abstract: An application usage estimation device includes: a rule DB serving as a rule holding unit configured to hold an application usage estimation rule for estimating, based on location information, whether a specific application is used; and an application usage estimation unit configured to acquire the location information from a user terminal and to estimate, based on the application usage estimation rule held in the rule DB, whether the specific application is used in the user terminal.

Abstract: An electronic device and a method for event logging are provided. The electronic device includes a random access memory (RAM), a non-volatile memory, a transient error detector, and a clock counter. When a status of input-output ports in the electronic device changes, the transient error detector takes the status of the input-output port and its change as one of the event logs, obtains a time stamp corresponding to the one of the event logs according to a count value counted by the clock counter, and sequentially and temporarily stores the one of the event logs and a corresponding time stamp to the RAM. And, the transient error detector determines whether the event log is a cause to fault. When the event log is the cause to fault, the transient error detector stores the event logs and the corresponding time stamps in the RAM to the non-volatile memory.

Abstract: A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which the application code includes a prefixed instruction to be modified by a prefix, a trap is provided. The trap is configured to report a presence of the prefix, but to otherwise perform the trap functions absent the prefix; i.e., the prefix is otherwise ignored in the processing of the trap.

Abstract: Embodiments of the present disclosure relate to methods, systems, and computer program products for monitoring a state of an application. A target object that is to be monitored in an application may be determined in response to receiving a monitoring configuration. A position of the target object in source codes of the application may be identified. A state of the target object may be monitored in response to the application being traced to a location corresponding to the position.

Abstract: Disclosed aspects relate to debugging a set of code components of an application program. A set of defect data which indicates a set of defects may be collected with respect to an application program. The set of defect data may be derived from a set of post-compilation users of the application program. A set of test case data which indicates a set of user interface features of the application program may be collected with respect to the application program. The set of test case data may be derived from a set of development tests of the application program. Using both the set of defect data and the set of test case data, a set of fragility data for the set of code components of the application program may be determined. Based on the set of fragility data, the set of code components of the application program may be debugged.

Abstract: A neural network for identifying defects in source code of computer software. The neural network comprises: at least one convolutional layer configured to generate a one or more feature abstractions associated with an input segment associated with the source code; at least one recurrent layer configured to identify within the one or more feature abstractions a pattern indicative of a defect in the source code; and at least one mapping layer configured to generate a mapping between the identified pattern and a location of the indicated defect in the source code.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve runtime performance of software executing on a heterogeneous system. An example apparatus includes a feedback interface to collect a performance characteristic of the heterogeneous system associated with a compiled version of a block of code at a first runtime, the compiled version executed according to a function designating successful execution of the compiled version on the heterogeneous system, the heterogeneous system including a first processing element and a second processing element different than the first processing element; a performance analyzer to determine a performance delta based on the performance characteristic and the function; and a machine learning modeler to, prior to a second runtime, adjust a cost model of the first processing element based on the performance delta, the adjusted cost model to cause a reduction in the performance delta to improve runtime performance of the heterogeneous system.

Abstract: A computing device is provided, including a processor configured to receive source code at a compiler. The source code may include at least one compound conditional having a plurality of conditions. For each condition of the plurality of conditions, the source code may further include a respective code block including instructions to evaluate the condition. For each ordering of a plurality of orderings of the plurality of conditions, the processor may determine that the ordering satisfies one or more legality constraints. For each ordering of the plurality of orderings that satisfy the one or more legality constraints, the processor may determine a respective estimated computational cost for that ordering. The processor may reorder the plurality of conditions to have an ordering that has a lowest estimated computational cost of the plurality of orderings that satisfy the one or more legality constraints.

Abstract: Embodiments of the present disclosure disclose a method and an apparatus for testing a code file. A preferred embodiment of the method comprises: compiling a to-be-tested code file to obtain an intermediate code file; instrumenting a code block identifier of each code block in the intermediate code file to the intermediate code file; determining an identifier of a jump relationship between two code blocks that have the jump relationship in the intermediate code file; performing dynamic testing to the instrumented intermediate code file based on respective code block identifiers and respective identifiers of jump relationships. This embodiment enhances bug detection capabilities for testing a code file.

Abstract: A connection can be made to a processing element of a remotely deployed and live streaming application executed by a first data processing system, the processing element containing at least one operator that processes at least one tuple. As the live streaming application is executed, without slowing or modifying data flow of the live streaming application execution to client devices, a copy of the tuple and a memory dump of state data for a state of the operator can be received, and the tuple can be tracked through a call graph. The state data can be loaded into a local instance of the operator loaded into a debugger. At least a portion of the call graph can be presented to a user, and a flow of the tuple through the call graph based on the state data for the operator can be indicated.

Abstract: Processing automation scripts used for testing pages includes running the automation scripts using a processor, searching for an element on the page according to locating information in an instruction of the automation scripts, collecting element-related information of the element in response to finding of the element on the page according to the locating information, and associating the collected element-related information of the element with the instruction of the automation scripts. The element-related information associated with the instruction is saved.

Abstract: Apparatus, systems, methods, and articles of manufacture for automated quality assurance and software improvement are disclosed. An example apparatus includes a data processor to process data corresponding to events occurring with respect to a software application in i) a development and/or a testing environment and ii) a production environment. The example apparatus includes a model tool to: generate a first model of expected software usage based on the data corresponding to events occurring in the development and/or the testing environment; and generate a second model of actual software usage based on the data corresponding to events occurring in the production environment. The example apparatus includes a model comparator to compare the first model to the second model. The example apparatus includes a correction generator to generate an actionable recommendation to adjust the development and/or the testing environment to reduce a difference between the first model and the second model.

Abstract: An electronic product testing system includes: a retrieving module configured to access an electronic file, the electronic file containing data generated based on a testing of a first product, the testing of the first product performed based at least in part on a first set of digits; and a testing device having a processing unit configured to perform testing of a second product based on the data in the electronic file, and also based on a second set of digits different from the first set of digits, the second product having at least one feature that is different from the first product, wherein the testing device is configured to perform the testing of the second product by submitting the second set of digits for processing by a repository.

Abstract: A remote network management platform software application containing application programming interfaces (APIs) may be configured to facilitate the use of plugin software. A particular API may be associated with logic configured to check whether a toggle variable is active or inactive. A first unit of program code may be configured to execute when the toggle variable is inactive, and a second unit of program code may be configured to execute when the toggle variable is active. First plugin software may be implemented in a scripting language. The first plugin software, whether enabled or disabled, might not affect the toggle variable. Second plugin software may also be implemented in the scripting language. The second plugin software, when enabled, is configured to set the toggle variable as active.

Abstract: In an approach for testing an application for a security vulnerability, a processor inserts an instrumentation hook in the application to be tested, wherein the instrumentation hook is executed prior to a sink operation. A processor transmits a probe input value to the application to be tested. A processor detects a modification to the probe input value at the instrumentation hook by comparing the probe input value at the instrumentation hook to a signature value and detecting that the probe input value matches the signature value. A processor removes the sink operation from testing for the security vulnerability.

Abstract: The invention introduces an apparatus for a redundant array of independent disk (RAID) reconstruction, at least including a RAID group and a processing unit. The processing unit starts an unused-space scan procedure to determine a logical address range that is a candidate to be skipped for the RAID group and send the logical address range to a stripe reconstruction procedure; and starts the stripe reconstruction procedure to receive the logical address range from the unused-space scan procedure, determine a stripe of drives of the RAID group to be skipped from being reconstructed according to the logical address range, and omit a reconstruction to the determined strip.

Abstract: Methods for transfer of bulk data from a leader device to a follower device over a bus are described. The methods employ address frames and write frames. The bus, the address frames, and the write frames are compatible with Clause 45 of IEEE Std 802.3-2015. The methods achieve a reduction in the number of frames employed to transfer data as contrasted with conventional indirect write transactions. After transmitting on a Management Data Input/Output (MDIO) data signal an address frame that specifies the follower device and that contains the address of an initial register, the leader device proceeds to transmit on the MDIO data signal multiple write frames that specify the target follower device, the multiple write frames transmitted one at a time, each write frame containing a different block of the bulk data. A follower device implements a post-write-increment-address action, despite the absence of any definition in Clause 45 of IEEE Std 802.3-2015 of a post-write-increment-address frame.

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks, and a controller that generates a first mapping table for mapping information of logical addresses between a host device and physical addresses of the nonvolatile memory device and controls the first mapping table to be stored in the memory blocks. The controller may include a host interface unit that receives a second logical address to be written in a second mapping table from the host device and a second memory that stores the second mapping table.

Abstract: An integrated circuit (IC) exposes hardware blocks thereof via an addressable control space defining fields at corresponding global addresses. The addressable control space is shared across the hardware blocks. Each hardware block has implemented fields; the implemented fields of a hardware block are mapped to a subset of the fields of the addressable control space. One or more implemented fields of more than one hardware block are each mapped to the same field of the addressable control space. A hardware block internally compresses the fields of the addressable control space in accordance with its implemented fields to perform a write operation. A hardware block internally expands the implemented fields to the fields of the addressable control space to perform a read operation.

Abstract: A memory system having non-volatile media, a volatile memory, and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. The non-volatile media has a quantity of memory units and stores an address map that defines logical addresses used in the requests in terms of physical addresses of the memory units in the non-volatile media. The host system has a memory connected to the memory system via a communication channel. The memory system has a cache manager that stores a first portion of the address map in the volatile memory of the memory system and a second portion of the address map in the memory of the host system. In response to an operation that uses a logical address defined in the second portion, the cache manager retrieves the second portion of the address map from the memory of the host system through the communication channel to the volatile memory of the memory system.

Abstract: A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Abstract: A storage device includes a cache memory and a processor configured to perform, in accordance with an amount of dirty data stored in the cache memory, a determination of a first physical volume and a first logical volume placed in the first physical volume from the plurality of physical volumes and the plurality of logical volumes placed in the plurality of physical volumes, perform selection, from a first plurality of physical volumes in which the determined first logical volume is placed by mirroring, of a second physical volume other than the determined first physical volume, and perform selection, from the plurality of physical volumes, of a third physical volume other than the second plurality of physical volumes, and write data of the first logical volume read from the second physical volume, to the third physical volume, and delete the first logical volume from the determined first physical volume.

Abstract: In a data processing system, a store request is provided having corresponding store data and a corresponding access address, and a memory coherency required attribute corresponding to the access address of the store request is provided. When the store request results in a write-through store due to a cache hit or results in a cache miss, the corresponding access address and store data is stored in a selected entry of the store buffer and a merge allowed indicator is stored in the selected entry which indicates whether or not the selected entry is a candidate for merging. The merge allowed indicator is determined based on the memory coherency required attribute from the MMU and a store buffer coherency enable control bit of the cache. Entries of the store buffer which include an asserted merge allowed indicator and share a memory line in the memory are merged.

Abstract: Provided are a computer program product, system, and method for using track locks and stride group locks to manage cache operations. A group of tracks from the storage devices are stored in a cache. Exclusive track locks for tracks in the group in the cache are granted for writes to the tracks in the group in the cache, wherein exclusive track locks can be simultaneously held for writes to different tracks in the cache. An exclusive group lock for the group of tracks in the cache is granted to destage the tracks in the group from the cache to the storage devices. The exclusive group lock is released in response to completing the destage of the tracks in the group in the cache to the storage devices.

Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

Abstract: The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.

Abstract: A controller of a data storage device includes: a host interface providing an interface to a host computer; a flash translation layer (FTL) translating a logical block address (LBA) to a physical block address (PBA) associated with an input/output (I/O) request; a flash interface providing an interface to flash media to access data stored on the flash media; and one or more deep neural network (DNN) modules for predicting an I/O access pattern of the host computer. The one or more DNN modules provide one or more prediction outputs to the FTL that are associated with one or more past I/O requests and a current I/O request received from the host computer, and the one or more prediction outputs include at least one predicted I/O request following the current I/O request. The FTL prefetches data stored in the flash media that is associated with the at least one predicted I/O request.

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Abstract: The data cache of a processor is segregated by execution mode, eliminating the danger of certain malware by no longer sharing the resource. Kernel-mode software can adjust the relative size of the two portions of the data cache, to dynamically accommodate the data-cache needs of varying workloads.

Abstract: The disclosed technology is generally directed to protection against unauthorized code. In one example of the technology, a read request to a restricted region of memory is detected. The read request is associated with a first processor. In response to detecting the read request to the restricted region of memory, a data value that causes an exception in response to execution by the first processor is provided.

Abstract: An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.

Abstract: Disclosed herein is a technique for managing I/O requests transmitted between a computing device and a storage device. According to some embodiments, the technique can be implemented by the computing device, and include providing at least one I/O request to a submission queue configured to store a plurality of I/O requests. In conjunction with providing the at least one I/O request, the computing device can identify that at least one condition associated with the submission queue—and/or a completion queue—is satisfied, where efficiency gains can be achieved. In turn, the computing device can (1) update an operating mode of the storage device to cause the storage device to cease interrupt issuances to the computing device when I/O requests are completed by the storage device, and (2) update an operating mode of the computing device to cause the computing device to periodically check the completion queue for completed I/O requests.

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

Abstract: A device hot-plug system includes a chassis. A connector is included in the chassis. A reset pin is included on the connector. A hot-plug device is configured, in response to being hot-plugged to the connector, to enter a device reset state. While in the device reset state, the hot-plug device monitors a reference clock and determines that the reference clock has been stable for a predetermined time period. In response to determining that the reference clock has been stable for a predetermined time period, the hot-plug device exits the device reset state and provides a de-assertion signal on the reset pin.

Abstract: Provided are a computer program product, system, and method for adding dummy requests to a submission queue to manage processing of queued requests according to priorities of the queued requests. A determination is made of a priority for a request to stage a track from the storage device to the cache or to destage a track from the cache to the storage device, comprising a first priority or a second priority. The first priority is higher than the second priority. At least one dummy request is added to a queue in response to the request having the second priority. The controller upon processing a dummy request in the queue discards the dummy request without performing an operation with respect to the storage device. An I/O request having the second priority is added to the queue. The controller processes the I/O request to stage or destage data.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.

Abstract: Systems, methods, and apparatus for communicating a control signal between device components are provided. Within an apparatus, an integrated circuit (IC) sends a control signal to a system on chip (SoC). The control signal requests enablement or disablement of one or more resources corresponding to the IC. Thereafter, a converting circuit within the SoC converts the control signal from the IC into a command to be transmitted to one or more devices. The converting circuit then transmits the command to the one or more devices via a bus coupling the SoC to the one or more devices. The one or more devices includes one or more power management integrated circuits (PMICs) configured to control the one or more resources.

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

Abstract: According to one embodiment, when an external device is connected, the electronic device detects devices in the external device, and setup of detected devices. When the electronic device is powered, when a power state is restored from a hibernation or a sleep state to a normal state, or when the external device is connected, it is determined whether a first device is included in the detected devices. When the first device is included and when setup of a second device is failed, detection of devices and setup of detected devices are repeated.

Abstract: A system of automation components, having a control unit, having a memory area which includes a parameter data record, and a key memory, which is able to be connected to the control unit via an unambiguously allocatable, electrically conductive connection. The key memory is location-bound, in particular able to be spatially fixedly allocatable to a specific point in a system as a whole, the key memory having at least one non-volatile memory area, including an unambiguous item of identifying information. The control unit is able to read out the identifying information. The system also includes an external data memory, which is able to be directly accessed, and data is able to be exchanged between the control unit and the external data memory.

Abstract: A data bus system includes a processor having a data output and a transceiver connecting the data output to a data bus. The transceiver includes a bus-hold circuit configured to maintain a latest value of the data output. At least one output latch connects the data bus to at least one corresponding controlled system.