Abstract: An oculink electronic device having a flexible circuit board includes an oculink connector, a first rigid circuit board, a second rigid circuit board and the flexible circuit board. The first rigid circuit board is connected with the oculink connector. The flexible circuit board is extended from the first rigid circuit board and the second rigid circuit board and disposed between the first rigid circuit board and the second rigid circuit board. Therefore, not only the assembling steps are reduced, but also the total length is significantly shortened. The rotatable characteristic is provided, and the space requirement of installation is reduced.

Abstract: A network-based services provider may reserve and provision primary resource instance capacity for a given service (e.g., enough compute instances, storage instances, or other virtual resource instances to implement the service) in one or more availability zones, and may designate contingency resource instance capacity for the service in another availability zone (without provisioning or reserving the contingency instances for the exclusive use of the service). For example, the service provider may provision resource instance(s) for a database engine head node in one availability zone and designate resource instance capacity for another database engine head node in another availability zone without instantiating the other database engine head node. While the service operates as expected using the primary resource instance capacity, the contingency resource capacity may be leased to other entities on a spot market. Leases for contingency instance capacity may be revoked when needed for the given service (e.g.

Abstract: An illustrative “VM heartbeat monitoring network” of heartbeat monitor nodes monitors target VMs in a data storage management system. Accordingly, target VMs are distributed and re-distributed among illustrative worker monitor nodes according to preferences in an illustrative VM distribution logic. Worker heartbeat monitor nodes use an illustrative ping monitoring logic to transmit special-purpose heartbeat packets to respective target VMs and to track ping responses. If a target VM is ultimately confirmed failed by its worker monitor node, an illustrative master monitor node triggers an enhanced storage manager to initiate failover for the failed VM. The enhanced storage manager communicates with the heartbeat monitor nodes and also manages VM failovers and other storage management operations in the system. Special features for cloud-to-cloud failover scenarios enable a VM in a first region of a public cloud to fail over to a second region.

Abstract: Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

Abstract: Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.

Abstract: A method and system for recovering data from a storage system is disclosed. The method includes predicting, by a fault tolerance device, a fault within the storage system comprising one or more disk array enclosures, wherein each of the one or more disk array enclosures comprise a plurality of disks. The method further includes identifying, by the fault tolerance device, a data block going to be affected by occurrence of the predicted fault, wherein the data block is identified within a first disk in the plurality of disks. The method includes extracting, by the fault tolerance device, data stored in the data block before occurrence of the predicted fault. The method further includes transferring, by the fault tolerance device, the data extracted from the data block to a second disk not going to be affected by occurrence of the predicted fault.

Abstract: A system and method to record and trace data exchanges between cooperating hardware unit operations and software unit operations, providing an efficient mechanism to trace back to a root cause point from an observed failure point in a series of executed instructions performed within a data processing system. A data debug memory records information pertaining to each system memory access performed by instructions executed by the hardware and software units into separate memory information blocks. Linked relationships are created between certain ones of the memory information blocks to represent data dependencies that occurred between the instructions. These linked relationships may then be utilized to generate lists that map the various data dependencies between the executed instructions.

Abstract: Analog-to-digital conversion is tested in-field using an on-chip built-in self-test (BIST) sub-circuit formed within an underlying integrated circuit. Processing cycles may be conscripted during an idle state when the analog-to-digital conversion is not needed. The BIST requires a test time which may be compared to an idle time. If the idle time exceeds the test time, then the BIST may be entirely performed. However, if the idle time is unknown or less than the test time, the BIST may be paused and resumed between subsequent idle states.

Abstract: The present disclosure is related to devices and systems for immutable file storage. An example device can include instructions to hash a log file received from a log source to produce a hash value, store the hash value and information describing the log file, communicate the hash value and the information to a third party service, wherein the third party service maintains the communicated hash value and the communicated information such that the communicated hash value and the communicated information are immutable, access the communicated hash value and the communicated information, and compare the stored hash value and the stored information with the communicated hash value and the communicated information to determine whether the log file is unmodified.

Abstract: A code testing system identifies possible code errors that may generate unexpected application behaviors. The code testing system identifies function calls in the system by identifying function call sites that do not specify a receiver object but may invoke a function that uses a receiver object. To identify these call sites, the code testing system analyzes function operation to determine receiver functions that use a receiver object, and may exclude functions that use the receiver object in a pro forma way or that does not rely on or affect properties of the object. A callgraph is generated for the functions in the code to identify possible functions called from a call site. When a call site, based on the callgraph, may invoke a receiver function, the call site is analyzed to determine whether it specifies a receiver object for the called function and identifies an error when the call site does not specify a receiver object.

Abstract: A system executes multiple ruleset version scanning, warning and correction using a Software Deployment Management (SDM) environment such as Pega®. The system presents a code scanning interface to a user; receives input from the user selecting input rulesets comprising at least one ruleset and at least one version of the ruleset for scanning; accesses a guiderail database comprising a plurality of guiderails configured as best practices for SDM application development; scans the input rulesets comprising applying at least a portion of the plurality of guiderails to each of the input rulesets; and determining which of the input rulesets comprise compliance issues and a severity of each of the compliance issues; and presents an indication of severity of compliance issues for each of the input rulesets to the user using the code scanning interface.

Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving source code of an application, providing intermediate code based on the source code, the intermediate code including at least one instruction for profiling at least one line of the source code, providing profiling data by processing the intermediate code, processing the profiling data based on one or more of a latency model and an energy model to respectively provide at least one latency metric and at least one energy metric of the at least one line, and storing modified source code that is provided based on a modification of the at least one line of source code.

Abstract: A method, computer program product, and computer system for performing, at a computing device, an analysis of a web application. A response is annotated by the web application with coverage data based upon, at least in part, the analysis, wherein the coverage data indicates which actions have been performed on the web application and which actions have not been performed on the web application according to results of the analysis. The response that includes the coverage data is shared with one or more users.

Abstract: Provided is a system for building and validating an application (including e.g., various software versions and revisions, programming languages, code segments, among other examples) without any scripting required by a system user. In one embodiment, an SDLC system is configured to construct a build and test environment, by automatically analyzing a submitted project. The build environment is configured to assemble existing user code, for example, to generate an application to test. Code building can include any one or more of code compilation, assembly, and code interpretation. The system can include a user interface provided to clients, users, and/or customer environments to facilitate user interaction and control of build and test validation. The system can accept user specification of configurations that controls the way the system runs the user's tests. The system can also provide flexible billing models for different customers.

Abstract: A method and a system are described for generation of test automation scripts in real time. The method includes scanning a plurality of properties associated with objects within a user interface of an application under test. The method includes comparing the properties with a pre-stored object library. The pre-stored object library comprises metadata of pre-stored properties of the application under test. This includes identifying the updated properties associated with one or more objects from the plurality of objects based on the comparison of metadata of updated objects with the metadata of existing or pre-stored properties. This includes creating a unique XPATH reference for each of the one or more of objects based on the identified one or more updated properties. The method includes generating in real time one or more test automation scripts for each of the one or more of objects based on the unique XPATH reference.

Abstract: A method and a testing tool for automated testing of HMI applications includes: identifying, at least one vehicle from a plurality of vehicles as HMI enabled vehicle, and a HMI application installed on an electronic device corresponding to the at least one vehicle; identifying one or more errors in one or more additional features being integrated with the HMI application; generating test data based on one or more test scripts related to the one or more additional features and historical test analysis of the HMI application; and executing the one or more test scripts on the HMI application based on the test data for automated testing of Human Machine Interface (HMI) applications associated with vehicles. The disclosed method and the testing tool provide a common framework for testing HMI applications of various vehicles.

Abstract: An online system ranks test cases run in connection with check-in of sets of software files in a software repository. The online system ranks the test cases higher if they are more likely to fail as a result of defects in the set of files being checked in. Accordingly, the online system informs software developers of potential defects in the files being checked in early without having to run the complete suite of test cases. The online system determines a vector representation of the files and test cases based on a neural network. The online system determines an aggregate vector representation of the set of files. The online system determines a measure of similarity between the test cases and the aggregate vector representation of the set of files. The online system ranks the test cases based on the measures of similarity of the test cases.

Abstract: A system comprising at least one processor; and at least one storage device. The storage device(s) store instructions that, when executed, cause the at least one processor to: determine an initial state of a production processing system, store the initial state, capture information about a plurality of transactions executing within the production processing system, configure, based on the initial state of a production processing system, a test processing system, deploy, within the test processing system, source code not included in the production processing system, generate, based on the information about the plurality of transactions, a replay test script, wherein the replay test script comprises a replay of the plurality of transactions, and wherein the replay test script further comprises transactions based on a new use case for the source code not included in the production processing system, and execute, within the test processing system, the replay test script.

Abstract: Systems and methods for performing automated software testing on user interface elements are disclosed. For instance, a first element of an application can be identified. A signature can be generated for the first element. The signature for the first element can include one or more attributes descriptive of the first element. After an update of the application, a candidate element signature can be generated for one or more candidate elements in the updated application. The signature for the first element can be compared to each candidate element signature to determine whether the first element matches each candidate element, thereby enabling the first element to be located after the update of the application.

Abstract: Example implementations relate to root cause analysis of non-deterministic tests. In response to detecting a non-deterministic test of an application under test, some implementations may cause rerun executions of the non-deterministic test. Some implementations may also capture data during the rerun executions. The data may include application data, test data, and environment data. Some implementations may also analyze the captured data to determine a root cause of a failure of the non-deterministic test. The analysis may be based on a comparison between failed rerun executions and passed rerun executions.

Abstract: Certain aspects involve building and debugging models for generating source code executed on data-processing platforms. A target data-processing platform is identified that requires bin ranges for modeling coefficients and reason codes for input attributes. A processor outputs source code, which is generated from a modeling code, in a programming language used by the target data-processing platform.

Abstract: According to one general aspect, an apparatus may include a host interface, a memory, a processor, and an erasure-based, non-volatile memory. The host interface may receive a write command, wherein the write command includes unencoded data. The memory may store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The processor may select a memory address to store information included by the unencoded data based, at least in part, upon the rewriteable state of the memory address. The erasure-based, non-volatile memory may store, at the memory address, the unencoded data's information as encoded data, wherein the encoded data includes more bits than the unencoded data and wherein the encoded data can be over-written with a second unencoded data without an intervening erase operation.

Abstract: Embodiments of this disclosure allow non-position-independent-code to be shared between a closed application and a subsequent application without converting the non-position-independent-code into position-independent-code. In particular, embodiment techniques store live data of a closed application during runtime of the closed application, and thereafter page a portion of the live data that is common to both the closed application and a subsequent application back into volatile memory at the same virtual memory address in which the portion of live data was stored during runtime of the closed application so that the paged lived data may be re-used to execute the subsequent application in the managed runtime environment. Because the paged live data is stored at the same virtual memory address during the runtimes of both applications, non-position-independent-code can be shared between the applications.

Abstract: According to one embodiment, a cache memory device includes a nonvolatile cache memory, write unit, determination unit, selection unit, and erase unit. The nonvolatile cache memory includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The write unit writes data to the nonvolatile cache memory. The determination unit determines whether the plurality of erase unit areas satisfy an erase condition or not. The selection unit selects an area to be erased from the plurality of erase unit areas when the plurality of erase unit areas satisfy the erase condition. The erase unit erases the data written to the area to be erased.

Abstract: In one embodiment, a memory control process of a device receives a plurality of program/erase (P/E) requests for a flash memory of the device. The memory control process then stores data associated with the plurality of P/E requests in a random access memory (RAM) of the device, and aggregates the plurality of P/E requests into a single P/E operation. The memory control process may then send the single P/E operation to the flash memory at a given interval to update the flash memory with the data stored in the RAM.

Abstract: Example apparatus and methods provide improved reclamation, garbage collection (GC) and defragmentation (defrag) for data storage devices including solid state drives (SSD) or shingled magnetic recording (SMR) drives. An erasure code (EC) layer that facilitates logically or physically erasing data from the SSD or SMR as a comprehensive GC or defrag is added to the SSD or SMR. Erased data may be selectively recreated from the EC layer as needed. Pre-planned EC write zones may be established to further optimize GC and defrag. Recreated data may be written to selected locations to further optimize SSD and SMR performance. Erasure code data may be distributed to co-operating devices to further improve GC or defrag. Example apparatus and methods may also facilitate writing data to an SMR drive using tape or VTL applications or processes and providing a pseudo virtual tape library on the SMR drive.

Abstract: A system and process for recompacting digital storage space involves continuously maintaining a first log of free storage space available from multiple storage regions of a storage system such as a RAID system, and based on the first log, maintaining a second log file including a bitmap identifying the free storage space available from a given storage chunk corresponding to the storage regions. Based on the bitmaps, distributions corresponding to the storage regions are generated, where the distributions represent the percentage of free space available from each chunk, and a corresponding weight is associated with each storage region. The storage region weights may then be sorted and stored in RAM, for use in quickly identifying a particular storage region that includes the maximum amount of free space available, for recompaction.

Abstract: A method for managing a flash memory module, an associated flash memory controller and an associated electronic device are provided, wherein the method includes: when the flash memory module is powered on, and a garbage collection operation is not finished before the flash memory module is powered on: determining a progress of the garbage collection operation to generate a determination result; and determining to discard a target block in the garbage collection operation or to write dummy data into remaining pages of the target block according to the determination result.

Abstract: The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.

Abstract: A virtual link buffer provides communication between processing threads or cores. A first cache is accessible by a first processing device and a second cache accessible by a second processing device. An interconnect structure couples between the first and second caches and includes a link controller. A producer cache line in the first cache stores data produced by the first processing device and the link controller transfers data in the producer cache line to a consumer cache line in the second cache. Each new data element is stored at a location in the producer cache line indicated by a store position or tail indicator that is stored at a predetermined location in the same cache line. Transferred data are loaded from a location in the consumer cache line indicated by a load position or head indicator that is stored at a predetermined location in the same consumer cache line.

Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.

Abstract: Enabling a prefetch request to be controlled in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. One or more processors identify, based on a prefetch tag, a prefetch request that is associated with a prefetch instruction that is executed by a remote processor. The one or more processors generate the prefetch request in a remote processor according to a prefetch protocol. The prefetch request includes i) a description of at least one prefetch request operation and ii) a prefetch request information. A local processor, of the one or more processors, receives the prefetch request from the remote processor.

Abstract: An system for prefetching data for a processor includes a processor core, a memory, a cache memory, and a prefetch circuit. The memory may be configured to store information for use by the processor core. The cache memory may be configured to issue a fetch request for information from the memory for use by the processor core. The prefetch circuit may be configured to issue a prefetch request for information from the memory to store in the cache memory using a predicted address, and to monitor, over a particular time interval, an amount of fetch requests from the cache memory and prefetch requests from the prefetch circuit. The prefetch circuit may also be configured to disable prefetch requests from the memory for a subsequent time interval in response to a determination that the amount satisfies a threshold amount.

Abstract: A drive controller associated with a data storage medium may receive a command from a host to write a set of data to a storage space of the data storage medium. The drive controller may determine that insufficient space is available in a cache space of the data storage medium to write the set of data to the cache space and may dynamically convert an available portion of the storage space into a dynamic cache space associated with the cache space. The dynamic cache space may remain visible to the host as the available portion of the storage space. The drive controller may then write the set of data to the cache space and report to the host that the set of data is written to the storage space of the data storage medium.

Abstract: Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.

Abstract: The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.

Abstract: NAND flash storage devices and methods are provided that use a non-NAND cache to store write data until a substantially complete storage unit is available. An exemplary solid state storage device comprises a NAND flash memory device; a non-NAND cache; and a controller configured to obtain write data from a remote host for storage in the NAND flash memory device; store the write data in the non-NAND cache; and transfer the write data from the non-NAND cache to the NAND flash memory device when a predefined storage criterion is satisfied. The predefined storage criterion comprises, for example, a storage unit of the write data stored in the non-NAND cache, where the storage unit comprises a block of data erased in a single garbage collection cycle. The predefined storage criterion is optionally established to reduce open block degradation in NAND flash memory devices.

Abstract: An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.

Abstract: A technique includes using a cache controller of an integrated circuit to control a cache including cached data content and associated cache metadata. The technique includes storing the metadata and the cached data content off of the integrated circuit and organizing the storage of the metadata relative to the cached data content such that a bus operation initiated by the cache controller to target the cached data content also targets the associated metadata.

Abstract: A nonvolatile memory system includes: a nonvolatile memory device that includes a nonvolatile memory cell array and a page buffer; and a memory controller that loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, and in response to a logical address received from outside the memory controller, translates the logical address into a physical address based on the mapping data that is loaded into the page buffer.

Abstract: Aspects of managing Translation Lookaside Buffer (TLB) units are described herein. The aspects may include a memory management unit (MMU) that includes one or more TLB units and a control unit. The control unit may be configured to identify one from the one or more TLB units based on a stream identification (ID) included in a received virtual address and, further, to identify a frame number in the identified TLB unit. A physical address may be generated by the control unit based on the frame number and an offset included in the virtual address.

Abstract: Smart weighted container data cache eviction preserves write evict units (WEUs) containing the most frequently and recently accessed blocks to maintain low latency data cache. Prior to performing cache eviction, the WEUs are weighted based on the page statistics maintained for each WEU. Page statistics include page hit/frequency and recency statistics associated with each WEU and data cache eviction is performed at the WEU level of granularity. Therefore, an entire WEU can be evicted based on page hit/frequency and recency statistics associated with the WEU.

Abstract: According to some embodiment, a backup storage system receives a request from a client for reading a data segment associated with a file object stored in a storage system. In response to the request, the system determines whether a cache hit counter associated with the data segment exceeds a cache hit threshold. The system further determines whether the data segment is associated with a file region of the file object that is frequently accessed. The system writes the data segment into a memory responsive to determining that the cache hit counter exceeds the cache hit threshold and the data segment is associated with the frequently accessed file region. Otherwise, the system writes the data segment into a solid state device (SSD) operating as a cache device.

Abstract: The present embodiments relate to methods and apparatuses for side-band management of security for server computers. According to certain aspects, such management is directed to the security of data that is stored under the local control of the server, as well as data that flows through the network ports of the server. Such locally stored data is secured by encryption, and the encryption keys are managed by a management entity that is separate from the server. The management entity can also manage the security of network data flowing through the server using its own configuration of network security applications such as firewalls, monitors and filters.

Abstract: A storage medium storing a device driver is a storage medium storing a device driver executed by a computer to control communication between the computer and a peripheral device connected to the computer, and a process for matching a first characteristic and a second characteristic is executed by the device driver, with respect to information transmitted and received between the application software and the peripheral device, on the basis of first information and second information acquired from the peripheral device.

Abstract: An intelligent electronic device (IED), e.g., an electrical power meter, having at least one removable memory device for storing data sensed and generated by the intelligent electronic device is provided. The IED includes a housing; at least one sensor; at least one analog-to-digital converter; at least one processing unit coupled to the at least one analog-to-digital converter configured to receive the digital data and store the digital data in a removable memory; and at least one device controller coupled to the at least one processing unit, the at least one device controller including an interface disposed on the housing for interfacing with the removable memory, wherein the at least one device controller is operative as a USB master or USB slave device controller.

Abstract: A microcontroller device comprises at least one processor (8), one or more peripheral systems (6) and a resource supply module (2). The processor (8) and peripheral system(s) (6) are each arranged to generate a signal when they require power and/or a clock signal. These signals stimulate the resource supply module (2) to supply the requested resource.

Abstract: An electronic device includes a memory and a system on chip (SoC). The memory device includes a first memory cell area assigned to a first channel and a second memory cell area assigned to a second channel. The SoC includes a first processing unit and a second processing unit. The first processing unit is configured to transmit a first command for accessing the first memory cell area to the memory device through the first channel. The second processing unit is configured to transmit a second command for accessing the second memory cell area to the memory device through the second channel. The memory device is configured such that a bandwidth of the first channel and a bandwidth of the second channel are different from each other.

Abstract: Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. The receiver may be configured to receive differential data signals to receive write data at a rate, and each of the first and second transmitters may be configured to encode a plurality of bits into a respective data signal and provide the respective data signals at the data rate.

Abstract: According to certain aspects, a memory module is coupled to a memory controller of a host computer system via an interface. The memory module is operable in at least a second mode and a first mode. The memory module in the second mode is configured to perform training related to one or more training sequences initiated by the memory controller while the memory module is not accessed by the memory controller for memory read or write operations. The memory module in the first mode is configured to perform one or more memory read or write operations not associated with the one or more training sequences by communicating data signals with the memory module. The memory module has an open-drain output pin via which the memory module output a signal indicating a parity error having occurred while the memory module is performing a normal memory read or write operation, and via which the memory module output a signal related to the one or more training sequences.