Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit is configured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract: A memory device includes a memory, and a processor coupled to the memory and configured to hold memory information corresponding to the memory, access information corresponding to access to the memory, and storage information indicating a storage area of the access information, extract, based on the storage information, an access information code including the access information, output the memory information in response to a read request from an external, and output the extracted access information code in response to an acknowledgment received from the external corresponding to the memory information.

Abstract: A nonvolatile memory device includes: a plurality of word lines that are stacked; a vertical channel region suitable for forming a cell string along with the word lines; and a voltage supplier suitable for supplying a plurality of biases required for a program operation on the word lines, where a negative bias is applied to neighboring word lines disposed adjacent to a selected word line at an end of a pulsing section of a program voltage which is applied to the selected word line.

Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

Abstract: A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.

Abstract: A memory element includes a free magnetization layer (“FR-ML”) in a film form, a nonmagnetic layer (“NML”), and a fixed magnetization layer (“FX-ML”), The NML and FX-ML are stacked on the FR-ML. The FR ML stores a single bit of data “0” or “1” according to a magnetization direction and rewrites the data by reversing the magnetization direction. An antiferromagnet that exhibits the anomalous Hall effect and has a reversible magnetization direction is used for the FR-M. The reversal of the magnetization direction of the FR-ML is performed using the FX-ML by the spin-transfer torque technique. To read data, a reading current is caused to flow in one direction, and a Hall voltage generated in the FR-ML by the anomalous Hall effect is extracted from the FR-ML. The polarity of the Hall voltage is reversed in accordance with the magnetization direction of the FR-ML.

Abstract: The present disclosure provides a magnetic random access memory structure, including an array region, and a logic region adjacent to the array region. The logic region includes a bottom electrode via, a magnetic tunneling junction layer over the bottom electrode via, a top electrode over the MTJ, a conformable oxide layer over the MTJ and the top electrode, and a silicon oxide layer over the conformable oxide layer. The conformable oxide layer and the silicon oxide layer extend from the array region to the logic region.

Abstract: A data writing method is configured such that a spin device includes a conducting portion extending in a first direction and a device portion stacked on one surface of the conducting portion and including a non-magnetic layer and a ferromagnetic layer, wherein an energy equal to or smaller than an energy represented by a predetermined relational expression (1) is applied in the first direction of the conducting portion when the pulse width of an applied pulse is t.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of detective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.

Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.

Abstract: Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch that stores a row address; and a time based sampling circuit. The time based sampling circuit includes: a sampling timing generator that provides a timing signal of sampling a row address; and a plurality of bank sampling circuits, wherein each bank sampling circuit of the bank sampling circuits is included in a corresponding memory bank of the memory banks and provides a sampling signal to the latch in the corresponding memory bank responsive to the timing signal of sampling the row address; and an interval measurement circuit that receives an oscillation signal, measures an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further provides a steal rate timing signal for adjusting a steal rate to the sampling timing generator.

Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may be configured to output a command. The semiconductor device may be configured to receive and decode the command and generate an internal command to perform a preset operation. The semiconductor device may be configured to update a synchronization temperature code with a temperature code when the temperature code changes. The semiconductor device may be configured to apply the synchronization temperature code to the controller in synchronization with the internal command.

Abstract: A semiconductor integrated circuit is described. A transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about ½of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.

Abstract: Provided is a periodic signal generation circuit including: a clock generation unit suitable for generating first to Nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “N”; a pulse generation unit suitable for generating first to Nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “N” by combining two or more clocks among the first to Nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to Nth periodic pulses depending on combination information.

Abstract: A layout structure of a sub word line driver for use in a semiconductor memory device is disclosed. The sub word line driver may include a first active region through which first and second main word lines pass. The sub word line driver may include first gates arranged in the first active region, and configured to receive word line selection signals. Each of the first gates is formed to have a substantially square shape.

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Abstract: An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

Abstract: A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations.

Abstract: A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.

Abstract: A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.

Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.

Abstract: The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal. The supply circuit includes an inverter circuit having an input coupled to the wiring, and a switch element controlled by an output signal of the inverter circuit. The switch element couples the boosted voltage to the distal end of the wiring.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

Abstract: A Flash memory access module performs memory access management of a Flash storage device including a plurality of storage cells. The Flash memory access module includes: a read only memory for storing a program code; and a microprocessor which executes the program code to perform the following steps: performing a first sensing operation corresponding to a first sensing voltage in a storage cell, and performing a second sensing operation in the storage cell; using the first sensing operation and at least the second sensing operation to generate a first digital value and a second digital value, respectively, of the storage cell; using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.

Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.

Abstract: According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.

Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.

Abstract: A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The neuromorphic circuit further includes a set of row-lines respectively connecting the synaptic array cell in series to a plurality of pre-synaptic neurons at first ends thereof. The neuromorphic circuit also includes a set of column-lines respectively connecting the synaptic array cell in series to a plurality of post-synaptic neurons at second ends thereof. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with the set of row lines and the set of column lines.

Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.

Abstract: A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.

Abstract: A non-volatile storage device includes: a first electrode; a second electrode; a variable resistance element including a variable resistance layer having a resistance value which changes according to a voltage pulse applied between the first and second electrodes; a voltage pulse application circuit which applies the voltage pulse between the first and second electrodes; and a control circuit which controls the voltage pulse application circuit. Upon receiving an external instruction, the control circuit: reads a current resistance state of the variable resistance element; and when the current resistance state is the high resistance state, causes the voltage pulse application circuit to apply a first additional voltage pulse having a first polarity between the electrodes; and when the current resistance state is the low resistance state, causes the voltage pulse application circuit to apply, between the electrodes, a second additional voltage pulse having a second polarity different from the first polarity.

Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Abstract: According to one embodiment, a semiconductor memory device includes a memory string including a first select transistor, a first transistor adjacent to the first select transistor, and a memory cell transistor, a first select gate line, a first interconnect, a word line, a row decoder, a temperature sensor, and a control circuit. In the erase operation, the control circuit selects a first mode for applying a first voltage to the first interconnect when a temperature measured by the temperature sensor is equal to or higher than a first temperature, and selects a second mode for applying a second voltage to the first interconnect when the temperature measured is less than the first temperature.

Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

Abstract: Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.

Abstract: Disclosed are a memory device, a memory package including the same, and a memory module including the same. The memory package includes a first memory device configured to operate in response to a first chip select signal from an external device, a second memory device configured to operate in response to a second chip select signal from the external device, and a third memory device configured to operate in response to a third chip select signal from the external device. The third memory device includes a buffer unit that is connected with an internal circuit of the third memory device through an internal data line, is connected with the first memory device through a first memory data line, is connected with the second memory device through a second memory data line, and is connected with the external device through a data line.

Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: performing a single-layer erasing operation on one of physical erasing units; performing a multi-layer erasing operation on another one of the physical erasing units; and performing a wear leveling operation based on the one and the another one of the physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data.

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a read operation on a selected memory block among the plurality of memory blocks. The control logic controls the read operation of the peripheral circuit. The selected memory block is coupled to a plurality of bit lines, and the plurality of bit lines are grouped into a plurality of bit line groups. The peripheral circuit performs data sensing by applying different reference currents to the plurality of bit line groups, respectively.

Abstract: Page-level reference voltage parameterization techniques are provided for solid state memory devices. A method comprises obtaining a bit error count for a plurality of page numbers across a plurality of blocks of a solid state memory device; determining a substantially optimal reference voltage for each page number that substantially minimizes a corresponding bit error count; collecting, for each reference voltage, page numbers and corresponding substantially optimal reference voltages; and determining, for each reference voltage, a non-linear function that substantially fits a distribution of the collected page numbers and corresponding substantially optimal reference voltages, wherein a given page having a given page number is read using a plurality of parameters of the non-linear function to generate the substantially optimal reference voltage for the given page number.

Abstract: A voltage generator of a nonvolatile memory device includes a charging circuit, a current mirror circuit, a discharging circuit and an output circuit. The charging circuit amplifies a difference between a reference voltage and a feedback voltage to generate a first current. The current mirror circuit is connected to the charging circuit and generates a second current based on the first current. The discharging circuit is connected to the current mirror circuit to draw the second current, and discharges the output voltage to a target level by adjusting discharging amount of the second current based on a sensing voltage which reflects a change of the feedback voltage. The output circuit is connected to the current mirror circuit, and provides the output voltage based on the first current and the second current to a first word-line connected to an output node.