Abstract: An inverter system for a vehicle is provided. The system includes an energy storage that stores electrical energy and a first inverter that includes a plurality of first switching devices and converts energy stored in the energy storage into AC power. A second inverter includes a plurality of second switching devices that are different in types from the first switching devices, and is connected to the energy storage in parallel with the first inverter. The second inverter converts the energy stored in the energy storage into AC power. A motor is driven by the AC power converted by the first inverter and the second inverter. A controller generates a PWM signal based on required output of the motor and operates the motor by inputting the generated PWM signal to at least one or more of the first inverter and the second inverter.

Abstract: A power source system includes: a rotary electrical machine; a power source; a switch that is provided between the power source and the rotary electrical machine; and a power source control device that controls opening/closing of the switch in response to a request for power feeding to the rotary electrical machine. The power source control device is configured to, in response to the power source system stopping operation, bring the switch into a closed state in a predetermined period of time. A rotary electrical machine control device controlling the rotary electrical machine includes: a determination unit that, in response to the power source system stopping operation, determines that the switch is in the closed state; and an abnormality diagnosis unit that, in response to the determination unit determining that the switch is in the closed state, performs an abnormality diagnosis of the rotary electrical machine.

Abstract: The invention relates to an autonomous and movable device (1) for generating, storing and distributing electrical power, comprising means (2) for generating electrical power, namely photovoltaic panels (20), resting on at least one supporting element (3), namely a standardized shipping container (3 qql, 32). The latter encloses internal means (6) for storing the electrical power generated by said generating means (2), said supporting element (3) also enclosing means for converting signals generated by the generating means (2) into signals suitable for supplying power to the storing means, and at least one electrical connector (8) for connecting external power-storing devices.

Abstract: A method and apparatus for “double cropping”, with photovoltaic panel arrays mounted on and operating from specialized photovoltaic solar array support structures that are supported above agricultural fields at heights that allow the passage of large mechanized farm equipment to pass beneath. The arrays are optimized for sun sharing operation in that their solar panel design, spacing and computerized movement are optimized to both generate electricity and increase the agricultural efficiency of the underlying land.

Abstract: A tower having a solar panel attached at the top of the tower. The solar panel is attached with a bracket having a movable arm and fixed arm. Both arms pivotally engage a rear of the panel. The pivot arm is attached to a long shaft that extends all the way to the ground and is movable from the ground to adjust the angle of the solar panel.

Abstract: A waterproof and electricity-insulating support structure for solar panels includes a base frame having a top portion with two side portions disposed at two sides of the top portion. Each of the side portions connects with a bottom portion to be fixed on a steel frame forming a roof. A fastening member is fixed to the top portion of the base frame to form an assembling space for solar panels therebetween. A plurality of rubber strips for waterproofing and insulating from electricity are disposed between the side portions and the solar panels and between the fastening member and the solar panels.

Abstract: A foldable solar panel including at least two solar modules mounted to a substrate. The foldable solar panel includes hook and loop tape to secure the foldable solar panel in the folded configuration. The foldable solar panel includes at least two straps and at least two horizontal rows of webbing operable to attach the foldable solar panel to a load-bearing platform.

Abstract: A circuit includes an oscillator having a driver and a resonator. The driver receives a supply voltage at a supply input and provides a drive output to drive the resonator to generate an oscillator output signal. A power converter receives an input voltage and generates the supply voltage to the supply input of the driver. A temperature tracking device in the power converter controls the voltage level of the supply voltage to the supply input of the driver based on temperature such that the supply voltage varies inversely to the temperature of the circuit.

Abstract: A class-E power oscillator (PO) is disclosed. The class-E PO includes a first inductor, a switch, a first capacitor, a resonant circuit, and a feedback network. The first inductor is coupled in series to a first power supply. The switch is connected between the first inductor and a primary common node. The first capacitor is connected between the first inductor and the primary common node. The resonant circuit includes a second inductor, a second capacitor, and a resistor. The second inductor is connected between the first inductor and the primary common node. The second capacitor is connected between the first inductor and the primary common node, and is coupled in series to the second inductor. The resistor is connected between the first inductor and the primary common node, and is coupled in series to the second inductor. The feedback network is connected between the switch and a feedback node. The feedback node is located between the second inductor and the second capacitor.

Abstract: An amplification circuit includes an input terminal for receiving a radio frequency input signal, an output terminal for outputting an amplified radio frequency signal, a bias circuit for providing a bias voltage, an impedance circuit, a transistor, and a filter circuit. The impedance circuit is coupled to the bias circuit and the input terminal, and provides a voltage drop between the first terminal and the second terminal of the impedance circuit. The first transistor has a first terminal coupled to the output terminal, a second terminal coupled to a first reference voltage terminal, and a control terminal coupled to the impedance circuit and for receiving the radio frequency input signal. The filter circuit is coupled to the first transistor and the impedance circuit, filters out a harmonic signal, and provides a feedback signal including a primary frequency signal of the amplified radio frequency signal to the impedance circuit.

Abstract: In accordance with embodiments of the present disclosure, a method for power supply rejection for an amplifier may include generating a correction signal by multiplying a quantity indicative of a power supply voltage of the amplifier by a transfer function defining a response from the power supply voltage of the amplifier to an output signal of the amplifier and subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.

Abstract: A radio frequency (RF) amplifier circuit includes an amplifier device and a first baseband bias circuit. The amplifier device includes a first input configured to receive a first signal to be amplified and a first output configured to output a first amplified signal. The first baseband bias circuit includes an input coupled to the first output of the amplifier device. The first baseband bias circuit includes a first envelope decoupling circuit and a first harmonic decoupling circuit. The first envelope decoupling circuit includes a first bulk capacitor and a first distributed inductor configured to resonate in a baseband frequency range. The first harmonic decoupling circuit includes a second bulk capacitor and a second distributed inductor configured to resonate at a harmonic frequency of the frequency of the first signal received at the input of the amplifier device.

Abstract: A bias circuit includes a current source to generate a reference current, a temperature compensation portion in an off-state in an initial start period in response to a first control signal, and in an on-state in a normal driving period, subsequent to the initial start period, and to receive a first current of the reference current, and a bias output portion to generate a warm up current based on the reference current in the initial start period and to generate a bias current based on a second current, which is lower than the reference current by an amount of the first current, in the normal driving period.

Abstract: A circuit (200) for testing failure of a connection between a radio frequency, RF, integrated circuit (201) and external circuitry (204), the circuit comprising: an amplifier (205) having first and second input paths (215, 216) and first and second output paths (206, 207); a first power detector (208, 209) coupled to one of said first or second output paths; at least one connection (211) between said first and second output paths (206, 207) and said external circuitry (204), connecting said outputs to a RF combiner (210) said external circuitry; at least one disabling circuit (230, 232, 234, 236, 240, 242, 260, 262) coupled to at least one of said first and second output paths (206, 207) or at least one of said first and second input path (215, 216), before said path reaches said power detector (208, 209); for disabling one of said inputs or outputs; wherein when said input or output path is disabled (206, 207), and a signal is output along the enabled output path (206, 207), the power detector (208, 209) on

Abstract: The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide amplifiers that can be used in high power RF applications. Specifically, the amplifiers described herein may be implemented to include one or more matching networks with the transistor(s) and inside the device package in a way that may facilitate operation at high frequencies and over wide bandwidths. Specifically, the amplifiers can be implemented with matching networks that include inductive and capacitive elements arranged in double T-match configuration, where at least some inductive elements are implemented with bond wires and the capacitive elements are implemented with integrated passive devices (IPDs). In such implementations the double T-match configuration of the matching network can be fully implemented inside the package, and may provide the amplifier with high frequency, wide bandwidth performance.

Abstract: An audio preamplifier includes a first stage including a first triode of a first vacuum tube in a common cathode configuration configured to perform a first gain function favoring one of low frequencies and mid-range frequencies in response to user input; a second stage including a second triode of the first vacuum tube in a common cathode configuration configured to perform a second gain function favoring one of low frequencies and mid-range frequencies in response to user input; a third stage including a first triode of a second vacuum tube in a common cathode configuration configured to perform a tone-shaping function favoring one of low frequencies and mid-range frequencies in response to user input; and a fourth stage including a second triode of the second vacuum tube in a follower configuration configured to perform a tone stack function in response to user input.

Abstract: An amplification subsystem for a communication system includes a downstream amplifier configured to transmit a downstream signal within a first frequency range, an upstream amplifier configured to transmit an upstream signal within a second frequency range, and a bidirectional amplifier configured to selectively transmit a mid-band signal in either of the upstream and downstream direction.

Abstract: The present disclosure provides a reconfigurable low noise amplifier (LNA) circuit. This reconfigurable LNA circuit can be used for connecting multiple receive signal paths to a particular LNA in one configuration as well as used for connecting a single receive signal path to a particular LNA in another configuration. In the single receive signal path configuration, the single receive signal path is not degraded by the parasitics of a particular set of switches used for the multiple receive signal paths configuration.

Abstract: An RF transceiver front end includes a receiver limb including a length of transmission line, an impedance matching network, a downstream shunt switch and a downstream further receiver component and a transmitter limb. The impedance matching network is configured to transform the input impedance of the further receiver component to match the input impedance of the receiver limb when the shunt switch is open and the RF transceiver front end is operable in receiver mode. The impedance matching network is further configured to transform the input impedance of the shunt switch to present an open circuit as the input impedance of the receiver limb when the shunt switch is closed and the RF transceiver front end is operable in transmitter mode. The length of transmission line can be from zero to less than ?/4 at the operating frequency of the RF transceiver.

Abstract: A device (100) for driving a self-conducting n-channel output stage field effect transistor (V1) comprising a control signal input (110), a control signal output (120) for connection to a gate electrode (V1G) of the output stage field effect transistor (V1), a first node (N1) connected to the control signal output (120), a second node (N2), and a first transistor (V4). A source electrode (V4S) of the first transistor (V4) is connected to the first node (N1), a gate electrode (V4G) of the first transistor (V4) is connected to the second node (N2) and a drain electrode (V4D) of the first transistor (V4) is either connected to the source electrode of the output field effect transistor (V1) or connected to a supply voltage (+Vdd). A resistor (R1) is connected with one end to the second node (N2). The device (100) is characterized in that the resistor (R1) is connected at the other end to the first node (N1).

Abstract: An amplifying device includes: an amplifying circuit connected between an input terminal and an output terminal and amplifying a signal input in an amplification mode; and a bypass circuit including a filter connected to a bypass path for bypassing the amplifying circuit, wherein the bypass path is in an off-state in the amplification mode and is in an on-state in a bypass mode, and the filter bypasses an input high-frequency signal to ground, in the amplification mode.

Abstract: Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.

Abstract: In examples, an apparatus for sensing current comprises a power transistor; a sense transistor coupled to the power transistor; and an offset addition circuit coupled to the power transistor and the sense transistor, the offset addition circuit comprising a first pair of transistors and a differential amplifier. The apparatus also comprises a cascode amplifier circuit coupled to the offset addition circuit, the cascode amplifier circuit comprising a second pair of transistors, and a gain trim circuit coupled to the cascode amplifier circuit, the gain trim circuit including another differential amplifier and a third transistor. The apparatus further includes an analog-to-digital converter (ADC) coupled to the gain trim circuit and storage coupled to the ADC.

Abstract: An amplifier circuit comprising: a first amplifier, comprising a voltage input terminal and a voltage output terminal; a voltage offset providing circuit, comprising a first terminal coupled to a first predetermined voltage source, a second terminal coupled to the voltage output terminal, and a third terminal, wherein a voltage at the third terminal is higher than a voltage at the second terminal by an offset voltage; and a voltage control capacitor, comprising a fourth terminal coupled to the third terminal, and a fifth terminal coupled to the voltage input terminal, wherein a capacitance value of the voltage control capacitor corresponds to a voltage difference between a voltage at the fifth terminal and a voltage at the fourth terminal. A better compensation for the amplifier circuit can be acquired since a voltage control capacitor having a capacitance value corresponding to the output voltage of the amplifier is applied.

Abstract: Exemplary multipath digital microphones described herein can comprise exemplary embodiments of automatic gain control and multipath digital audio signal digital signal processing chains, which allow low power and die size to be achieved as described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can facilitate switching between multipath digital audio signal digital signal processing chains while minimizing audible artifacts associated with either the change in the gain automatic gain control amplifiers switching between multipath digital audio signal digital signal processing chains.

Abstract: A resonator comprising a piezoelectric film which creates an acoustic path that is slightly longer in a central region of the resonator than at an edge of the resonator.

Abstract: A filter structure includes a ground plane in a first metal layer of an IC package, a plate in a second metal layer of the IC package, a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device. An inductive device in a third metal layer of the IC package is electrically connected to the plate, and a perimeter of the plate is aligned with a perimeter of the inductive device.

Abstract: In tuning a radio frequency (RF) module including a non-volatile tunable RF filter, a desired frequency and an undesired frequency being provided by an amplifier of the RF module are detected. The non-volatile tunable RF filter is coupled to an output of the amplifier of the RF module. A factory setting of an adjustable capacitor in the non-volatile tunable RF filter is changed by factory-setting a state of a non-volatile RF switch, such that the non-volatile tunable RF filter substantially rejects the undesired frequency and substantially passes the desired frequency. The adjustable capacitor includes the non-volatile RF switch, and the factory setting of the adjustable capacitor corresponds to a factory-set state of the non-volatile RF switch. An end-user is prevented access to the non-volatile RF switch, so as prevent the end-user from modifying the factory-set state of the non-volatile RF switch.

Abstract: The present disclosure relates to a ladder-type surface acoustic wave (SAW) device, which includes a piezoelectric layer, two reflective structures, at least one series interdigital transducer (IDT) coupled between a first signal point and a second signal point, and at least one shunt IDT. The at least one shunt IDT is coupled at least between the first signal point and ground, or between the second signal point and ground. Herein, the two reflective structures, the at least one series IDT, and the at least one shunt IDT reside over the piezoelectric layer. The at least one series IDT and the at least one shunt IDT are arranged between the two reflective structures.

Abstract: In a first approach, a reconfigurable radio frequency (RF) filtering module includes a phase-change material (PCM) RF switch bank and an RF filter bank. Each RF filter in the RF filter bank is capable to be engaged and disengaged by a PCM RF switch in the PCM RF switch bank. In a second approach, a tunable RF filter includes PCM RF switches and a capacitor and/or an inductor. Each of the capacitor and/or inductor is capable to be engaged and disengaged by at least one PCM RF switch of the PCM RF switches. In a third approach, an adjustable passive component includes multiple segments and a PCM RF switch. A selectable segment in the multiple segments is capable to be engaged and disengaged by the PCM RF switch. In all approaches, each PCM RF switch includes a PCM and a heating element transverse to the PCM.

Abstract: A non-volatile adjustable phase shifter is coupled to a transceiver in a wireless communication device. The non-volatile adjustable phase shifter includes a non-volatile radio frequency (RF) switch. In one implementation, the non-volatile RF switch is a phase-change material (PCM) RF switch. In one approach, the non-volatile adjustable phase shifter includes a selectable transmission delay arm and a selectable transmission reference arm. A phase shift caused by the non-volatile adjustable phase shifter is adjusted when the non-volatile RF switch engages with or disengages from the selectable transmission delay arm. In another approach, the non-volatile adjustable phase shifter includes a selectable impedance element. A phase shift caused by the non-volatile adjustable phase shifter is adjusted when the non-volatile RF switch engages with or disengages from the selectable impedance element. In either approach, the phase shift changes a phase of RF signals being transmitted from or received by the transceiver.

Abstract: An electronic impedance tuner comprises an adjusting circuit, N cell tuning circuits identical in structure and a switch controller. The adjusting circuit comprises a first microstrip line, a second microstrip line, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a first PIN diode. Each cell tuning circuit comprises a third microstrip line, a fourth microstrip line, a fourth capacitor, a fifth capacitor, a second PIN diode and a third capacitor. The capacitance Cd of the fourth capacitor meets the condition: 4 ? ? Y s N ? ? ? ? ? f 2 ? ? ? req ? 1 - ? ? req ? 2 ? C d ? Y s ? ? ? f 1 ? ? ? req ? 1 - ? ? req ? 2 . The length d of the third microstrip line meets the condition: ? 1 / 4 ? ( N + 1 ) < d < c 4 ? ? reff ? [ ( C d · Z 0 ) 2 + ( 2 ? ? ? f Bragg ) 2 - C d · Z 0 ] .

Abstract: An oversampling channelizer for processing overlapping data that includes a data storage unit, coupled to a data line that receives data values. The data storage unit includes a plurality of lanes, wherein each of the plurality of lanes includes dedicated memory locations and wires that store and transmit data values for a data vector of a data frame, and that store and transmit additional data values for a subsequent data vector of a subsequent data frame that includes a plurality of the data values from the data vector in the data frame. The oversampling channelizer includes a coefficient storage unit that stores a plurality of coefficient vectors for a plurality of coefficient frames. The oversampling channelizer includes a computation unit that computes a dot product of the data values for the data vectors of the data frame with coefficient values for coefficient vectors of a coefficient frame selected by a coefficient storage unit.

Abstract: A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.

Abstract: A method of monitoring the condition of a circuit comprises establishing a known baseline signal for a type of circuit (each is somewhat different) and defining these characteristics in terms of the lead and trailing edge angular components (@ zero crossing point), the voltage (amplitude), and the period (time length) of the waveform. Ideally, the angular component of the square wave should be vertical, or at 90 degrees to x-axis. The baseline non-regular square wave that is composed of current, voltage, any harmonic thereof, or the combination of these signals which best indicate predictive measurement attributed to the type of circuit being monitored. Future wave forms indicate the rate of decay based upon the aggregated angular, amplitude, and period components of the zero-crossing points when compared to the baseline signal and/or prior waveform of the observed specific splice. The rate of decay can help determine the life expectancy of the circuit.

Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

Abstract: A monitoring circuit is implemented for comparing a sampled voltage taken from a selected sampling capacitor and a reference voltage from a voltage buffer (150). The voltage buffer (150) is configurable according to programming provided to a programmable logic controller, PLC, (570). Comparisons may be made on a periodic basis, such as a time-division multiplexed basis, in connection with register settings in the PLC (570).

Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.

Abstract: A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected PCM RF switch. The ASIC is also configured to determine if the selected PCM RF switch is in an OFF state or in an ON state. In one implementation, a testing method using the ASIC is disclosed.

Abstract: A light switch network comprises a plurality of light switch units, each comprising a gesture interface to sense a user gesture by receiving at least one gesture signal from a sensing zone, and configured to exchange one or more gesture status signals with at least one other switch unit in the network in relation to the received gesture signal; each switch being enabled, on receiving the gesture signal: in a first mode, to change a designated switch mode and/or state in response to the gesture signal; or in a second mode, to not change the designated switch mode and/or state according to one or more conditions associated with the status signals received from the other switch unit.

Abstract: A system includes a housing, a sensing electrode disposed within the housing, and a connecting electrode. The system also includes a capacitive sensing circuit galvanically connected to the connecting electrode at a first port, but not to the sensing electrode. The capacitive sensing circuit is configured to determine a first capacitance between the first port and a ground. The first capacitance includes a variable capacitance between the connecting electrode and a person when the person is touching the housing.

Abstract: Systems and methods for performing an efficient ZQ calibration are provided herein. The described techniques use non-linearity compensation circuitry configured to compensate for a non-linear relationship between variation in a plurality of ZQ calibration codes and corresponding resistance variations, by adjusting either: a magnitude of the adjustment to the calibration step, the ZQCODE to an alternative ZQCODE, or both the magnitude of the adjustment to the calibration step and the ZQCODE to the alternative ZQCODE.

Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: A PUF device and a method of outputting a random sequence are disclosed. The PUF device includes: at least one processing unit and at least one PUF unit, and a first PUF unit of the at least one PUF unit includes a first MOS transistor and a second MOS transistor, two sources of the two MOS transistors are connected to a same input voltage; two gates of the two MOS transistors are floating; and two drains of the two MOS transistors are respectively connected with a first processing unit, and the first processing unit is configured to: output a first random value corresponding to the first PUF unit according to a difference between two results output by the two drains of the two MOS transistors, when the input voltage is greater than or equal to a preset voltage.

Abstract: Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.

Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.

Abstract: A method and apparatus for increasing the operation lifetime of a beam tube, BT, (2) having an electron multiplier (2F) which amplifies a received ionic current with an electron multiplier gain, GEM, to provide an electrical current (IBT) output by the said beam tube, BT, (2), is provided.

Abstract: An analog to digital converter (ADC) includes voltage inputs, a transconductor configured to convert the voltage inputs into currents, current-controlled oscillators, a counter, and digital logic. The current-controlled oscillators propagate respect currents from the transconductor. The counter is configured to count repeated traversal of one or more oscillators. The digital logic is configured to, based upon results from the counter, provide a code configured to indicate a value of associated voltage input.