Patents Issued in April 9, 2020
  • Publication number: 20200110635
    Abstract: The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.
    Type: Application
    Filed: November 28, 2019
    Publication date: April 9, 2020
    Inventors: Shuai HU, Xuda ZHOU, Tianshi CHEN
  • Publication number: 20200110636
    Abstract: An electronic device includes a CPU that executes the process execution program to function as a plurality of process execution units as threads and an execution control unit. The plurality of process execution units use the CPU to execute a process. The execution control unit controls executing of the process by the plurality of process execution units. The execution control unit sets a CPU usage priority level for each of the plurality of process execution units. The execution control unit changes the CPU usage priority level of the job of a type other than a specific type to a priority level that is equal to or less than a specific priority level, when the job of the specific type and the job of the type other than the specific type are simultaneously executed.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Applicant: KYOCERA Document Solutions Inc.
    Inventors: Shuhei OBARA, Wataru SUNAMI, Satoshi HAYAMA, Yoshitaka MATSUKI
  • Publication number: 20200110637
    Abstract: A method, apparatus, and system for regulating resource usage of a backup application is disclosed. The operations comprise: continuously monitoring and obtaining system resource usage, process states, and backup policy parameters; generating a normalized band value based on the system resource usage, the process states, and the backup policy parameters; generating a straight line plot based on the band value, a total CPU value, and a deviation value; calculating a slope of the straight line plot, wherein the slope is utilized to generate a deviation value based further on a first value and a second value received from a user, and wherein the deviation value is fed back to the generation of the straight line plot to normalize the slope; generating control values based on the slope; and adjusting performance of the backup application based on the control values to regulate system resource usage of the backup application.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Mahesh Reddy Appireddygari Venkataramana, Lakshminarayanan Muniswamy, Tushar B. Dethe, Swaroop Shankar D H
  • Publication number: 20200110638
    Abstract: An aspect includes the automatic generation of blueprints for orchestration engines from discovered workload representations. A computer-implemented method includes receiving, using a processor, a description of a workload executing in a source computing environment. The description of the workload is mapped, using the processor, to one or more resource descriptors located in a repository of resource descriptors describing resources available in a target computing environment. A declarative representation of the workload in the target computing environment is generated, using the processor, based at least in part on the mapping and the description of the workload. The declarative representation includes a specification of resources required by the workload in the target environment.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventors: Neeraj Asthana, Thomas Chefalas, Alexei Karve, Matthew Staffelbach, Alla Segal, Sai Zeng
  • Publication number: 20200110639
    Abstract: This disclosure is directed to a technique for memory management where physical memory areas may be partitions into a hierarchy of portions, the hierarchy may include a domain level that includes a page level that includes a slice level that includes an object level. Objects within a slice are a consistent size but may be different sized for different slices. A set of states reflecting memory usage status for each of the slices includes: a clean state for unused; a partial state; a full state; and a dirty state. Responses to allocation requests may be performed by selecting objects that are in a most preferred state based on a state allocation cost and a memory allocation cost either alone or in combination. A compact memory layout may be used to reduce run-time fragmentation of memory.
    Type: Application
    Filed: October 7, 2018
    Publication date: April 9, 2020
    Inventors: Christopher J. Corsi, Sudhanshu Goswami, Kevin Kauffman
  • Publication number: 20200110640
    Abstract: Techniques that facilitate orchestration engine resources and/or blueprint definitions for hybrid cloud composition are provided. In one example, a system includes a blueprint component and a blueprint transformation component. The blueprint component determines one or more abstract resource types for an abstract blueprint associated with a computing platform. The one or more abstract resource types are indicative of information associated with one or more computing resources for the computing platform. The blueprint transformation component transforms the one or more abstract resource types for the abstract blueprint into one or more executable resources for an executable blueprint that is executable by an orchestration engine.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Neeraj Asthana, Thomas E. Chefalas, Alexei Karve, Ameya Tayade
  • Publication number: 20200110641
    Abstract: A sourcing interface enables a particular device communicatively connected on a network to share one or more resources of the particular device with other devices communicatively connected to the network and coordinate task bidding with the other through broadcasting requests on the network. The sourcing interface manages dispatch of a particular task to one or more selected devices, the one or more selected devices selected based on one or more bids received by the particular device that best match a service level of particular request by the particular device, the dispatched task migrated to the one or more selected devices instead of handled by a web service provider. The sourcing interface monitors, at the particular device, for a result of execution of the particular task from the one or more selected devices, the one or more selected devices collecting telemetry data for usage reporting to the web service provider.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: Michael C. Hollinger, Chang Chen, Rodolfo Lopez, Juan G. Rivera, Michael R. Reddock
  • Publication number: 20200110642
    Abstract: A funnel locking technique for normal read-copy update (RCU) grace period requests. Based on a calculated future normal RCU grace period, a traversal is initiated of a funnel lock embodied as a hierarchical tree of nodes. The funnel-lock traversal starts at an initial node whose lock is held throughout the funnel-lock traversal. For each node accessed during the funnel-lock traversal that is not the initial node, a lock on the node is held while accessing that node. For each accessed node, the funnel-lock traversal is terminated if the future normal RCU grace period has already been requested at that node, if the node believes that the future normal RCU grace period as already started, or if the node is not the initial node and believes that any normal RCU grace period is underway. Otherwise, a request for the future normal RCU grace period is recorded at the node.
    Type: Application
    Filed: October 6, 2018
    Publication date: April 9, 2020
    Inventor: Paul E. McKenney
  • Publication number: 20200110643
    Abstract: Systems and methods for providing inter-process communication in a wearable computing device are disclosed. A hardware abstraction layer is provided for a plurality of physical devices. An application program accesses the plurality of physical devices via the hardware abstraction layer. A unique inter-process communication context is created for each application program and physical device pair. A socket interface is provided for each unique inter-process communication context.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 9, 2020
    Inventor: Roland Edwin Vane
  • Publication number: 20200110644
    Abstract: An example system and method facilitates operation of a networked software application, i.e., client application which communicates with a network resource (e.g., web service) during periods of intermittent network connectivity, by selectively intercepting and shredding and/or unshredding service response messages. In a specific embodiment, the example system includes one or more pluggable shredders and unshredders that are used to explode a complex REpresentational State Transfer (REST) payload into its constituent structured primitive objects for ease of consumption by the User Interface (UI) of the client application. The exploded, i.e., shredded response message payloads are stored in local cache, where the cached data is strategically structured as compared to the received REST payload. One or more unshredders selectively reconstruct one or more REST response message payloads if client reissues the corresponding REST request message while offline.
    Type: Application
    Filed: June 12, 2019
    Publication date: April 9, 2020
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Blake Sullivan, Kentaro Kinebuchi, Jing Wu, Min Lu, Andrew Schwartz, Max Starets
  • Publication number: 20200110645
    Abstract: Apparatus having first and second sets of memory devices commonly connected to receive a first enable signal and a second enable signal, respectively, and a multiplexer connected to receive the first and second enable signals. The multiplexer is configured to connect the first set of memory devices to an output of the apparatus in response to the first enable signal having a first logic level, and to isolate the first set of memory devices from the output in response to the first enable signal having a second logic level different than the first logic level. The multiplexer is further configured to connect the second set of memory devices to the output in response to the second enable signal having the first logic level, and to isolate the second set of memory devices from the output in response to the second enable signal having the second logic level.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 9, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Suresh Rajgopal, Dan E. Soto, Steven Eskildsen
  • Publication number: 20200110646
    Abstract: Embodiments relate to an incident handling system for individual components of an overall software system. In particular, an engine receives error data information from a source of error information in a software component. That error information source may comprise a log entry, a formal error message, an exception, or a system crash. In response, the engine queries an underlying metadata description of the software system to receive a query result with additional metadata (e.g., unique artifact identifier, name) relevant to the error. Analysis of the error data and error metadata allows the engine to create an incident that is dispatched to an existing error tracking system, for support ticket creation and handling by the appropriate party. Adapter(s) allow the incident handling system to convert error data into generic form for search/analysis, and then to convert the incident information back into the specific format expected by the existing error tracking system.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventor: Christian Martick
  • Publication number: 20200110647
    Abstract: A topology-based triage workflow service can display expert generated workflows in conjunction with a topology. A user can select a device experiencing an issue and can walk through a workflow for diagnosing an issue. The service analyzes the workflow to determine which components are related to each troubleshooting step and can highlight them within the topology to indicate to a user the relevant components. The service can also retrieve and display metrics relevant to each step in the workflow. As workflows are used, the service can track users' paths through workflows, troubleshooting success, and feedback. Based on the feedback, the application can improve workflows, suggest root causes of issues, or create automated scripts based on the most popular/successful workflows for solving particular issues.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Benoit Christian Bernard Souche, Timothy Diep
  • Publication number: 20200110648
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing view change. One of the methods is to be implemented on a blockchain and performed by a first node of N nodes in a view change protocol. The method includes: multicasting a view change message to at least some of the N nodes; obtaining, respectively from at least Q second nodes of the N nodes, at least Q echo messages each comprising: a consistent current view known to the second node indicating a primary node designated among the N nodes, and a consistent current sequence number known to the second node, the current sequence number associated with a latest transaction or a latest block, the current sequence number is larger than a first sequence number known to the first node; and responsive to obtaining the at least Q echo messages, ending the view change protocol.
    Type: Application
    Filed: March 18, 2019
    Publication date: April 9, 2020
    Inventor: Dayi YANG
  • Publication number: 20200110649
    Abstract: Disclosed embodiments relate to identifying Electronic Control Unit (ECU) anomalies in a vehicle. Operations may include monitoring, in the vehicle, data representing real-time processing activity of the ECU; accessing, in the vehicle, historical data relating to processing activity of the ECU, the historical data representing expected processing activity of the ECU; comparing, in the vehicle, the real-time processing activity data with the historical data, to identify at least one anomaly in the real-time processing activity of the ECU; and implementing a control action for the ECU when the at least one anomaly is identified.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Applicant: Aurora Labs Ltd.
    Inventor: Zohar Fox
  • Publication number: 20200110650
    Abstract: A system of verifying execution sequence integrity of an execution flow includes a monitoring system in communication with one or more sensors of a system being monitored, where the monitoring system includes one or more electronic devices, and a computer-readable storage medium having one or more programming instructions. When executed, the one or more programming instructions cause at least one of the electronic devices to receive from the sensors, a parameter value for each of one or more parameters that pertain to an operational state of the system, combine the received parameters to generate a combination value, apply a hashing algorithm to the combination value to generate a temporary hash value, search a data store for a result code associated with the temporary hash value, and in response to the result code associated with the temporary hash value indicating that the temporary hash value is incorrect, generate a fault notification.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventor: Ching Yee Hu
  • Publication number: 20200110651
    Abstract: The systems and methods of the present disclosure are generally related to managing distributed sales, service and repair operations. In particular, the systems and methods of the present disclosure relate to managing a distributed network of sales, service and/or repair operations that include automated features.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 9, 2020
    Inventor: David A. Milman
  • Publication number: 20200110652
    Abstract: Techniques to more readily identify issues that arise in connection with memory systems and streamline the analysis process. A detailed activity log is generate with corresponding start and stop traffic events to facilitate identification of problems in memory devices. Each event registered in the log includes numerous items of information. The information facilitates identifying the origin of a particular problem including when and where it occurred, thus making failure analysis (FA) both easier and faster.
    Type: Application
    Filed: September 11, 2019
    Publication date: April 9, 2020
    Inventors: Alexander ZAPOTYLOK, Andrei KONAN
  • Publication number: 20200110653
    Abstract: A method and system for processing data is disclosed. The system has a storage for storing a log, a state machine communicatively coupled to the storage for maintaining the log by executing log-actions, where the log stores indications of the processed data. The state machine has a plurality of generations each of which has a respective GUID. A single one of the generations is designated as a master generation of the state machine at any given moment in time. The master generation has exclusive privileges for executing write log-actions to the log at the any given moment in time. The method includes transmitting, by a master-candidate generation, a block request to the log that is instrumental in (i) preventing execution of write log-actions from any generation having a given GUID that is inferior the GUID of the master-candidate, and allowing execution of write log-actions exclusively from the master-candidate.
    Type: Application
    Filed: June 6, 2019
    Publication date: April 9, 2020
    Inventors: Denis Nikolaevich PODLUZHNY, Andrey Viktorovich FOMICHEV
  • Publication number: 20200110654
    Abstract: A computer-implemented method of creating a log file is disclosed. The method comprises: storing a request of a service to be executed by a computer system, wherein the service is performed using multiple software methods; executing the service by providing the request to the computer system; detecting a failure of the service; performing a stack trace of the service to identify a subset of the multiple software methods; providing a source code for the subset of the multiple software methods; modifying the source code for the subset of the multiple software methods to add logging statements, wherein the logging statements are configured for generating log data; re-executing the service using the modified source code to generate the log data; and generating the log file from the log data.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventors: Maria H. Oleszkiewicz, Bartlomiej T. Malecki, Blazej R. Rutkowski, Daniel J. Ryszka
  • Publication number: 20200110655
    Abstract: One example method includes receiving measurement information concerning the operation of a computing system component, comparing the measurement information to a standard, based on the comparison, determining whether or not the measurement information indicates the presence of an anomaly in the operation of the computing system component, when an anomaly is indicated, generating a prediction, based upon the measurement information, as to when the computing system component is expected to fail, and implementing, prior to failure of the computing system component, a proactive data protection action which protects data associated with the computing system component.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: John S. Harwood, Assaf Natanzon
  • Publication number: 20200110656
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Publication number: 20200110657
    Abstract: A set of processors in a symmetric multiprocessor (SMP) system are deconfigured following a first failed processor to return the SMP system to a symmetric state. One or more deconfiguration options are identified, and a respective cost is calculated for each deconfiguration option. A deconfiguration option is selected and applied to the SMP system based on the respective costs of the one or more identified deconfiguration options.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventors: Jayanth Othayoth, Venkatesh Sainath, Vishwanatha Subbanna, Dhruvaraj Subhashchandran
  • Publication number: 20200110658
    Abstract: One example method includes exposing a block storage which is distributed across a group of multiple sites, receiving a primary write request that identifies data to be stored, separating data identified in the primary write request into multiple data pieces, encoding the data pieces by creating multiple new blocks of data based on the multiple data pieces, where the data pieces are encoded in such a way that when a sufficient number, but fewer than all, of the multiple new blocks of data are retrieved, the data identified in the write request is recoverable by decoding, and writing the new blocks of data to different respective sites of the group, where writing of the new blocks of data is performed in conjunction with a plurality of secondary write requests, each of which corresponds to one of the new blocks of data.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Saar Cohen, Assaf Natanzon
  • Publication number: 20200110659
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventor: David Peter Foley
  • Publication number: 20200110660
    Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventors: Giuseppe Cariello, Fulvio Rori
  • Publication number: 20200110661
    Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Harish Reddy Singidi, Xiangang Luo, Preston Thomson, Michael G. McNeeley
  • Publication number: 20200110662
    Abstract: An error-handling method, an associated data storage device and the controller thereof are provided. The error-handling method may include: uploading an error-handling program to a buffer memory equipped with error correction code (ECC) protection capability; in response to at least one error, interrupting execution of a current procedure and activating an interruption service; executing the error-handling program on the buffer memory; disabling a transmission interface circuit; resetting at least one hardware engine and at least one NV memory element; performing cache rearrangement regarding a data cache within the data storage device, and programming rearranged cache data into the NV memory element, to perform data recovery; and through activating a watchdog module and the transmission interface circuit and relinking with a host device, completing soft reset to make the data storage device operate normally again.
    Type: Application
    Filed: September 11, 2019
    Publication date: April 9, 2020
    Inventors: Che-Ming Kuo, Yen-Ting Yeh
  • Publication number: 20200110663
    Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Om RANJAN, Riccardo GEMELLI, Denis DUTEY
  • Publication number: 20200110664
    Abstract: Embodiments of the present disclosure relate to method and apparatus for data protection. For example, there is provided a computer-implemented method. According to the computer-implemented method, it only needs to read the changed data to be protected rather than the entire data to be protected during the procedure of generating a redundant data portion for the changed data to be protected. Thus, I/O and memory consumptions can be reduced.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventors: Ronnie Yu Cai, Ao Sun, Gary Jialei Wu, Lu Lei, Chen Wang
  • Publication number: 20200110665
    Abstract: A technique for handling uncorrected memory errors (UEs) inside a kernel text section, the kernel text section being stored in a memory that is operably coupled to a CPU executing kernel program instructions. In an embodiment, a UE is detected that affects the kernel text section. The current instruction affected by the UE is identified. The UE-affected instruction is recovered by loading a copy thereof into the memory from a kernel image maintained in persistent storage. The UE-affected instruction is emulated using the copy of the UE-affected instruction. The instruction pointer of the CPU is then incremented to point to a next instruction in the memory that would normally be executed by the UE-affected instruction had there been no UE.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventors: Mahesh J. Salgaonkar, Anshuman Khandual, Srikar Dronamraju, Haren Myneni
  • Publication number: 20200110666
    Abstract: A method of performing data recovery of a first virtual machine (VM) hosted on a first hypervisor to a second hypervisor that is different from the first hypervisor is provided. The method identifies information indicating format of a first virtual disk in a backup of the first VM, and creates a second virtual disk using the information indicating format of the first virtual disk. The method also accesses information indicating configuration of the first VM and metadata of the first virtual disk, and creates a second VM hosted on the second hypervisor using the information indicating configuration of the first VM and the metadata of the first virtual disk. The method further attaches the second virtual disk to the second VM.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventors: Aaditya Rakesh, Sudha Hebsur
  • Publication number: 20200110667
    Abstract: One example method includes receiving an indication that an application has experienced a problem, where the application comprises a plurality of microservices, discovering that one of the microservices is a partial cause of the problem, identifying one or more connections among the microservices, where one or more of the connections indicates a dependency, or lack of dependency, among two or more microservices, and restoring the microservice that is a partial cause of the problem, and also restoring any other microservices that are dependent on that microservice.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Luay Al-Alem, Antony Bett, Assaf Natanzon, Michael Rhodes
  • Publication number: 20200110668
    Abstract: A method of performing backup for a group of virtual machines (VMs) is provided. The method identifies at least a first VM of the group of VMs based on a threshold and removes the at least first VM from the group of VMs such that the group of VMs includes first remaining VMs. The method also initiates creating a first snapshot for the first remaining VMs at the first level of consistency and identifies a failure of creating the first snapshot for at least a second VM of the first remaining VMs. The method further removes the at least second VM from the first remaining VMs such that the group of VMs includes one or more second remaining VMs and creates a second snapshot for the one or more second remaining VMs at the first level of consistency.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 9, 2020
    Inventors: Aaditya Rakesh, Sunil Yadav
  • Publication number: 20200110669
    Abstract: Aspects include prefetching a plurality of high-level information, high-level metadata, low-level metadata, and low-level information including a plurality of components associated with a monitored entity for disaster recovery. A subsequent instance of the high-level information, the high-level metadata, and the low-level metadata is requested. The subsequent instance of the high-level information is fetched based on detecting a change in the high-level metadata. A subsequent instance of one or more of the components of the low-level information corresponding to one or more changes in the low-level metadata is fetched for updating a plurality of disaster recovery data of the monitored entity in a persistent database.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Juliet Candee, Jes Kiran Chittigala, Ravi A. Shankar, Bradley J. Smith, Taru Varshney
  • Publication number: 20200110670
    Abstract: An illustrative embodiment includes a method for checkpointing and restarting an application executing at least in part on one or more central processing units coupled to one or more hardware accelerators. The method comprises checkpointing the application at least in part by: transferring checkpoint data of the application to the one or more hardware accelerators; performing distributed compression of the application checkpoint data at least in part using the one or more hardware accelerators; and writing the compressed application checkpoint data to a storage device. The method further comprises restarting the application at least in part by: reading the compressed application checkpoint data from the storage device; transferring the compressed checkpoint data to one or more hardware accelerators; and performing distributed decompression of the application checkpoint data at least in part using said one or more hardware accelerators.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: FAUSTO ARTICO, BRYAN S. ROSENBURG
  • Publication number: 20200110671
    Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 9, 2020
    Inventors: Steven Woo, David A. Secker, Ravindranath Kollipara
  • Publication number: 20200110672
    Abstract: In a backup system for a virtual infrastructure, the actual number of virtual machines protected by a backup server is determined for a given instant of time, and is used to calculate the number of virtual proxies required to protect the that actual number of virtual machines, and to deploy automatically the required virtual proxies in the virtual infrastructure.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Applicant: EMC IP Holding Company LLC
    Inventor: Sharath Talkad Srinivasan
  • Publication number: 20200110673
    Abstract: Provided are a method, system, and computer program product in which a computational device stores a data structure that includes identifications of a plurality of volumes and identifications of one or more time locks associated with each of the plurality of volumes. The data structure is indexed into, to determine whether an input/output (I/O) operation from a host with respect to a volume is to be permitted.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 9, 2020
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Carol S. Mellgren
  • Publication number: 20200110674
    Abstract: A computer implemented method is provided for determining a delay between a first database and an associated replicated database by replicating transactions of the first database in the replicated database, determining a delay between the two databases based on a commit timestamp from the first database and a timestamp associated with the commit transaction becoming visible in the replicated database. Then, after a predefined period of time has elapsed since replicating the commit transaction, determining a second delay based on a timestamp associated with a heartbeat log and a replicated database system time. And, selectively determining to execute or deny a statement received by the replicated database based on the second delay. Related apparatus, systems, techniques and articles are also described.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Kyu Hwan Kim, Deok Hoe Kim, Beomsoo Kim, Juchang Lee, Werner Thesing, Christoph Roterring
  • Publication number: 20200110675
    Abstract: A data management and storage (DMS) cluster of peer DMS nodes manages data backup and disaster recovery using a service level agreement. The backup data can be replicated from a primary compute infrastructure to the secondary compute infrastructure. For example, primary snapshots of virtual machines of the application in the primary compute infrastructure are generated, and provided to the secondary compute infrastructure. If the primary compute infrastructure is lost, the secondary compute infrastructure is initialized to replicate the primary compute infrastructure. Applications that were running in the primary compute infrastructure can failover to run in the secondary compute infrastructure. The replicated backup data is used to facilitate the migration. During a failover, the primary snapshots are deployed in the secondary compute infrastructure as virtual machines.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Zhicong Wang, Benjamin Travis Meadowcroft, Biswaroop Palit, Hardik Vohra, Mudit Malpani
  • Publication number: 20200110676
    Abstract: Exemplary embodiments herein describe programming models and frameworks for providing parallel and resilient tasks. Tasks are created in accordance with predetermined structures. Defined tasks are stored as data objects in a shared pool of memory that is made up of disaggregated memory communicatively coupled via a high performance interconnect that supports atomic operations as descried herein. Heterogeneous compute nodes are configured to execute tasks stored in the shared memory. When compute nodes fail, they do not impact the shared memory, the tasks or other data stored in the shared memory, or the other non-failing compute nodes. The non-failing compute nodes can take on the responsibility of executing tasks owned by other compute nodes, including tasks of a compute node that fails, without needing a centralized manager or schedule to re-assign those tasks. Task processing can therefore be performed in parallel and without impact from node failures.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 9, 2020
    Inventors: Haris Volos, Kimberly Keeton, Sharad Singhal, Yupu Zhang
  • Publication number: 20200110677
    Abstract: A storage device includes an integrity checking module checking integrity of data stored in a first host memory buffer (HMB) address of an HMB in a host coupled to the storage device, and an HMB mapping module mapping, if the integrity checking module determines the data as corrupted, the first HMB address to a second address
    Type: Application
    Filed: July 10, 2019
    Publication date: April 9, 2020
    Inventors: Yeon Woo KIM, Jea Young KWON, Walter JUN
  • Publication number: 20200110678
    Abstract: A monitoring system includes a baseboard management controller (BMC) disposed on a same baseboard as a system under test; an administrator device electrically connected to the BMC; and a software test fixture stored in the BMC, the software test fixture generating an electrical signal, which is transferred to a corresponding target device of the system under test to access a register of the corresponding target device.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 9, 2020
    Inventors: Bing-Han Yang, Po-Shen Kuo
  • Publication number: 20200110679
    Abstract: A vehicle includes a data communication network, a serial data bus, and a plurality of electronic nodes in signal communication with the serial data bus. The vehicle further includes a node identification system configured to store a several different diagnostic tests, along with expected operating data corresponding to a given diagnostic test. The node identification system sorts the plurality of nodes into individual node groups in response to performing one or more diagnostic tests among the different available diagnostic tests.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 9, 2020
    Inventors: Erin K. Doan, Matthew R. Danielson, Addison M. Moran, Michael J. Worden
  • Publication number: 20200110680
    Abstract: A method of simulating device state changes in an integrated system includes receiving a transaction request from a client device, storing the transaction request as a first event in an event log, transmitting the transaction request to a terminal device, storing the transmission of the transaction request as a second event in the event log, receiving a device response from the terminal device, storing the device response as a third event in the event log, and when the integrated system is under test, a simulator replays the stored events in the integrated system under test.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventor: Jared WOOD
  • Publication number: 20200110681
    Abstract: Aspects include receiving, at a central controller, a stimulation request from a first autonomous test bench of a plurality of autonomous test benches configured to stimulate a device under test that is a functional unit of a microprocessor. A set of conditions is accessed based on one or more states of the device under test and the autonomous test benches, the set of conditions mapping to a stimulation event type. A set of programmable controls is accessed based on collating past behavior of the autonomous test benches to determine a stimulation pattern for the autonomous test benches and a plurality of stimulation event types. The central controller provides a response to the first autonomous test bench indicating whether the first autonomous test bench is authorized to drive the device under test with the stimulation event type based on the set of conditions and the set of programmable controls.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventors: Akash Giri, Gaurav Sulagodu Venkatagiri
  • Publication number: 20200110682
    Abstract: A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Jayakrishna Guddeti, Deepa Chandran, Shivaprasad Sadashivaiah
  • Publication number: 20200110683
    Abstract: A computer system includes a circuit board, one or more connectors/sockets and a first controller. The connectors/sockets are disposed on the circuit board. The first controller is configured to receive information corresponding to parameters of the circuit board and/or the connectors/sockets before booting up the computer system to run an operating system (OS).
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: MAO SUI WANG, PAO-TING AN
  • Publication number: 20200110684
    Abstract: A method of verifying execution sequence integrity of an execution flow includes receiving, by a local monitor of an automated device monitoring system from one or more sensors of an automated device, a unique identifier for each function in a subset of an execution flow for which the local monitor is responsible for monitoring. The method includes combining the received unique identifiers to generate a combination value, applying a hashing algorithm to the combination value to generate a temporary hash value, retrieving, from a data store, a true hash value, determining whether the temporary hash value matches the true hash value, and in response to the temporary hash value not matching the true hash value, generating a fault notification. The true hash value represents a result of applying the hashing algorithm to a combination of actual unique identifiers associated with each function in the subset.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventor: Ching Yee Hu