Patents Issued in April 9, 2020
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Publication number: 20200111636Abstract: A radio frequency (RF) modulating signal splitter used by a multi-beam electron beam RF amplification system includes an RF input port and a plurality of RF output ports. A body frame distributes the RF modulating signal from the input port to the of output ports. The body frame and each one of the RF output ports have dimensions so that each one of the plurality of RF output ports is impedance matched with each other. In a method of modulating a RF input signal onto a plurality of electron beams, the RF input signal is split into a plurality of different paths directed to a plurality of output ports that are impedance matched to each other. RF energy is directed from each output port to a different input cavity of electronic beam RF amplification devices of a multi-beam electronic beam RF amplification system.Type: ApplicationFiled: October 3, 2019Publication date: April 9, 2020Inventors: Walter Sessions, Henry P. Freund
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Publication number: 20200111637Abstract: A photocathode can include a body fabricated of a wide bandgap semiconductor material, a metal layer, and an alkali halide photocathode emitter. The body may have a thickness of less than 100 nm and the alkali halide photocathode may have a thickness less than 10 nm. The photocathode can be illuminated with a dual wavelength scheme.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Katerina Ioakeimidi, Gildardo R. Delgado, Michael E. Romero, Frances Hill, Rudy F. Garcia
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Publication number: 20200111638Abstract: A measuring apparatus that irradiates a sample with a charged particle beam to observe the sample includes a particle source that outputs the charged particle beam, a lens that collects the charged particle beam, a detector that detects a signal of emitted electrons emitted from the sample which is irradiated with the charged particle beam, and a control device that controls the output of the charged particle beam and the detection of the signal of the emitted electrons in accordance with an observation condition, in which the control device sets, as the observation condition, a first parameter for controlling an irradiation cycle of the charged particle beam, a second parameter for controlling a pulse width of the pulsed charged particle beam, and a third parameter for controlling detection timing of the signal of the emitted electron within the irradiation time of the pulsed charged particle beam, and the third parameter is determined in accordance with a difference in intensity of signals of the pluraliType: ApplicationFiled: May 12, 2017Publication date: April 9, 2020Inventors: Ryoko ARAKI, Natsuki TSUNO, Yohei NAKAMURA, Masahiro SASAJIMA, Mitsuhiro NAKAMURA, Toshihide AGEMURA
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Publication number: 20200111639Abstract: This cross-section observation device bombards an object with a charged particle beam to repeatedly expose cross-sections of the object, bombards at least some of the cross-sections from among the plurality of the exposed cross-sections with a charged particle beam to acquire cross-sectional image information describing each of the at least some of the cross-sections, generates for each of these cross-sections a cross-sectional image described by the cross-sectional image information acquired, and generates a three-dimensional image in which the generated cross-sectional images are stacked together.Type: ApplicationFiled: March 27, 2018Publication date: April 9, 2020Inventors: XIN MAN, Junzo AZUMA
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Publication number: 20200111640Abstract: Disclosed is an apparatus for treating a substrate. The apparatus includes a chamber having a space therein in which the substrate is treated, a support unit that supports the substrate in the chamber, a gas supply unit that supplies gas into the chamber, and a plasma generation unit that excites the gas in the chamber into a plasma state. The support unit includes a support plate on which the substrate is placed, a high-frequency power supply that supplies high-frequency power to the support plate, and a high-frequency transmission line through which the high-frequency power is supplied from the high-frequency power supply to the support plate. Characteristic impedance of the high-frequency transmission line is variable.Type: ApplicationFiled: October 2, 2019Publication date: April 9, 2020Inventors: Jae-Bak SHIM, Youngjae LIM
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Publication number: 20200111641Abstract: An inductively-coupled plasma (ICP) generation system may include a dielectric tube, a first inductive coil structure to enclose the dielectric tube, an RF power supply, a first main capacitor between a positive output terminal of the RF power supply and one end of the first inductive coil structure, and a second main capacitor between a negative output terminal of the RF power supply and an opposite end of the first inductive coil structure. The first inductive coil structure may include inductive coils connected in series to each other and placed at different layers, the inductive coils having at least one turn at each layer, and auxiliary capacitors, which are respectively provided between adjacent ones of the inductive coils to distribute a voltage applied to the inductive coils.Type: ApplicationFiled: December 4, 2019Publication date: April 9, 2020Inventors: Sae Hoon UHM, Yun Seong LEE
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Publication number: 20200111642Abstract: According to one embodiment, a gas supply device includes at least one reservoir tank, which is to be connected to a process chamber configured to process a substrate and is configured to store a process gas to be supplied to the process chamber. A gas generator is configured to generate the process gas. A plurality of supply spaces is provided between the reservoir tank and the gas generator, is configured to receive the process gas from the gas generator, and supply the process gas in a pressurized state to the reservoir tank.Type: ApplicationFiled: February 19, 2019Publication date: April 9, 2020Applicant: Toshiba Memory CorporationInventor: Daiki IINO
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Publication number: 20200111643Abstract: An apparatus for plasma processing includes a first plasma source, a first planar electrode, a gas distribution device, a plasma blocking screen and a workpiece chuck. The first plasma source produces first plasma products that pass, away from the first plasma source, through first apertures in the first planar electrode. The first plasma products continue through second apertures in the gas distribution device. The plasma blocking screen includes a third plate with fourth apertures, and faces the gas distribution device such that the first plasma products pass through the plurality of fourth apertures. The workpiece chuck faces the second side of the plasma blocking screen, defining a process chamber between the plasma blocking screen and the workpiece chuck. The fourth apertures are of a sufficiently small size to block a plasma generated in the process chamber from reaching the gas distribution device.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: Applied Materials, Inc.Inventors: Toan Q. Tran, Soonam Park, Zilu Weng, Dmitry Lubomirsky
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Publication number: 20200111644Abstract: A direct drive circuit for providing RF power to a component of a substrate processing system includes a clock generator to generate a clock signal at a first frequency, a gate driver to receive the clock signal and a half bridge circuit. The half bridge circuit includes a first switch with a control terminal connected to the gate driver, a first terminal and a second terminal; a second switch with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal; a first DC supply to supply a first voltage to the first terminal of the first switch; and a second DC supply to supply a second voltage to the second terminal of the second switch. The first and the second voltages have opposite polarities and are approximately equal in magnitude.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventors: Maolin LONG, Alexander PATERSON
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Publication number: 20200111645Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.Type: ApplicationFiled: December 10, 2019Publication date: April 9, 2020Applicant: TOKYO ELECTRON LIMITEDInventors: Akira KOSHIISHI, Masaru SUGIMOTO, Kunihiko HINATA, Noriyuki KOBAYASHI, Chishio KOSHIMIZU, Ryuji OHTANI, Kazuo KIBI, Masashi SAITO, Naoki MATSUMOTO, Yoshinobu OHYA, Manabu IWATA, Daisuke YANO, Yohei YAMAZAWA, Hidetoshi HANAOKA, Toshihiro HAYAMI, Hiroki YAMAZAKI, Manabu SATO
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Publication number: 20200111646Abstract: An apparatus for processing reaction products that are deposited when an etching target film contained in a target object to be processed is etched is provided with: a processing chamber; a partition plate; a plasma source; a mounting table; a first processing gas supply unit; a second processing gas supply unit. The processing chamber defines a space, and the partition plate is arranged within the processing chamber and divides the space into a plasma generating space and a substrate processing space, while suppressing permeation of ions and vacuum ultraviolet rays. The plasma source generates a plasma in the plasma forming space. The mounting table is arranged in the substrate processing space to mount the target object thereon.Type: ApplicationFiled: September 11, 2019Publication date: April 9, 2020Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi NISHIMURA, Akitaka SHIMIZU, Fumiko YAMASHITA, Daisuke URAYAMA
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Publication number: 20200111647Abstract: The invention relates to a plasma-treatment device, in which a plasma electrode unit can be inserted into and removed from a processing chamber, and in which high-frequency power generated by a generator is transmitted to the plasma electrode unit by means of one or more electromagnetic fields and without an electrical ohmic contact. For this purpose, the plasma-treatment device comprises a transmission apparatus, which contains a primary coupling part, which is arranged inside the processing chamber and can generate an electromagnetic field. The plasma electrode unit contains a secondary coupling part, which is rigidly connected to the plasma electrode unit and is suitable for receiving the electromagnetic field and converting it into alternating electrical power. Furthermore, a method for operating such a plasma-treatment device is provided.Type: ApplicationFiled: May 18, 2017Publication date: April 9, 2020Inventors: Hermann Schlemm, Mirko Kehr, Uwe Scheit, Erik Ansorge, Daniel Decker
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Publication number: 20200111648Abstract: In a plasma processing apparatus, a mounting table have a first mounting surface on which a target object or a jig is mounted and a second mounting surface on which a ring member is mounted. The jig is used for measuring a thickness of the ring member disposed around the target object and having a facing portion facing an upper surface of the ring member. Elevating mechanisms lift or lower the ring member with respect to the second mounting surface. An acquisition unit acquires gap information indicating a gap dimension between the second mounting surface and the facing portion of the jig. A measurement unit measures a lifted distance of the ring member from the second mounting surface. A thickness calculation unit calculates the thickness of the ring member based on the gap dimension and the measured lifted distance of the ring member.Type: ApplicationFiled: October 2, 2019Publication date: April 9, 2020Applicant: TOKYO ELECTRON LIMITEDInventor: Atsushi OGATA
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Publication number: 20200111649Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.Type: ApplicationFiled: December 11, 2019Publication date: April 9, 2020Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung Jui Chang, Chin-Hsing Lin
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Publication number: 20200111650Abstract: A plasma processing apparatus includes a storage unit, an acquisition unit and a monitoring unit. The storage unit stores change information indicating a change in a value for a temperature of a mounting table when a processing condition of plasma processing for a target object mounted on the mounting table is changed. The acquisition unit acquires the value for the temperature of the mounting table in a predetermined cycle. The monitoring unit monitors, based on the change information, a change in the processing condition of the plasma processing from the change in the value for the temperature of the mounting table acquired by the acquisition unit.Type: ApplicationFiled: October 3, 2019Publication date: April 9, 2020Applicant: TOKYO ELECTRON LIMITEDInventor: Shinsuke Oka
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Publication number: 20200111651Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Otto Chen, Chi-Ying Wu, Chia-Chih Chen
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Publication number: 20200111652Abstract: Some embodiments relate to a system. The system includes a radio frequency (RF) generator configured to output a RF signal. A transmission line is coupled to the RF generator. A plasma chamber is coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal. A micro-arc detecting element is configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventors: Feng-Kuang Wu, Chih-Kuo Chang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sing-Tsung Li
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Publication number: 20200111653Abstract: A method of identifying a microorganism by mass spectrometry, including acquiring at least one mass spectrum of said microorganism; for each acquired mass spectrum: detecting peaks of the spectrum in a predetermined mass range; generating a list of peaks identifying at most one peak in each interval of a predetermined subdivision of the range of mass-to-charge ratios, the width of the intervals of the subdivision logarithmically increasing along with the mass-to-charge ratio, and analyzing the list(s) of peaks obtained according to a knowledge base of previously-identified microorganisms and/or types of microorganisms.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Applicant: BIOMERIEUX, INC.Inventors: Grégory Strubel, Maud Arsac, Denis Desseree, Pierre-Jean Cotte-Pattat
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Publication number: 20200111654Abstract: An ion analyzer that generates product ions from precursor ions derived from a sample component and analyzes the product ions includes a reaction chamber (2) into which the precursor ion is introduced, a radical generation chamber (51), a material gas supply source (52) configured to introduce material gas into the radical generation chamber (51), a vacuum evacuator (57) configured to evacuate the radical generation chamber (51), a vacuum discharge unit (53) configured to generate a vacuum discharge in the radical generation chamber (51), a radical irradiation unit (54) configured to irradiate an inside of the reaction chamber (2) with radicals generated from the material gas in the radical generation chamber (51), and a separation and detection (3) configured to separate and detect product ions generated from the precursor ion by reaction with the radicals according to at least one of a mass-to-charge ratio and ion mobility.Type: ApplicationFiled: March 29, 2018Publication date: April 9, 2020Applicants: SHIMADZU CORPORATION, THE DOSHISHAInventors: Hidenori TAKAHASHI, Motoi WADA
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Publication number: 20200111655Abstract: An ion transfer device that transfers ions from at least one ion inlet to at least one ion outlet of the ion transfer device such that the ion transfer device includes an enclosure configured to maintain reduced pressure, and a plurality of electrodes disposed at least in part inside the enclosure.Type: ApplicationFiled: July 12, 2018Publication date: April 9, 2020Inventor: Mazdak Taghioskoui
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Publication number: 20200111656Abstract: A method for modifying a carbon thermal ionization filament is disclosed. In particular, the method requires a step of reacting a fluorine-containing compound with the carbon thermal ionization filament to provide a fluorinated carbon thermal ionization filament. Such method can result in a fluorinated carbon thermal ionization filament that can be employed in a system, such as a thermal ionization mass spectrometer, for ionizing a sample.Type: ApplicationFiled: October 9, 2018Publication date: April 9, 2020Inventors: Joseph M. Mannion, Randall M. Achey
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Publication number: 20200111657Abstract: A multipole assembly configured to be disposed in a mass spectrometer includes a plurality of elongate electrodes arranged about an axis extending along a longitudinal trajectory of the plurality of elongate electrodes and configured to confine ions radially about the axis, and a piezoelectric actuator configured to adjust a position of a first electrode included in the plurality of elongate electrodes.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Edward B. McCAULEY, Scott T. QUARMBY, George B. GUCKENBERGER, James M. HITCHCOCK
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Publication number: 20200111658Abstract: A wafer processing method includes: a bonding step of bonding a front surface side of a first wafer chamfered at a peripheral edge portion thereof to a front surface side of a second wafer; a grinding step of holding a back surface side of the second wafer by a chuck table and grinding a back surface of the first wafer to thin the first wafer to a finished thickness, after the bonding step; and a modified layer forming step of applying along a boundary between a device region and a peripheral surplus region of the first wafer a laser beam of such a wavelength as to be transmitted through the first wafer to form an annular modified layer inside the first wafer in the vicinity of the front surface of the first wafer, before the grinding step.Type: ApplicationFiled: September 25, 2019Publication date: April 9, 2020Inventor: Tetsukazu SUGIYA
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Publication number: 20200111659Abstract: A method of modifying a layer in a semiconductor device is provided. The method includes depositing a low quality film on a semiconductor substrate, and exposing a surface of the low quality film to a first process gas comprising helium while the substrate is heated to a first temperature, and exposing a surface of the low quality film to a second process gas comprising oxygen gas while the substrate is heated to a second temperature that is different than the first temperature. The electrical properties of the film are improved by undergoing the aforementioned processes.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Wei LIU, Theresa Kramer GUARINI, Linlin WANG, Malcolm BEVAN, Johanes S. SWENBERG, Vladimir NAGORNY, Bernard L. HWANG, Kin Pong LO, Lara HAWRYLCHAK, Rene GEORGE
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Publication number: 20200111660Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.Type: ApplicationFiled: May 9, 2019Publication date: April 9, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-woon Park, Jin-su Lee, Hyung-suk Jung
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Publication number: 20200111661Abstract: The present invention relates to a method for manufacturing semiconductor manufacturing parts used in a dry etching process, and a jig usable therein, and the method for manufacturing semiconductor manufacturing parts by using the jig, of the present invention, comprises the steps of: preparing a base material; supporting at least one surface of the base material by the jig; forming a deposition layer by spraying source gas on the base material supported by the jig; and processing the base material on which the deposition layer is formed, wherein the jig has a tapered cross-section of which the width increases in the direction of approaching the surface of the base material.Type: ApplicationFiled: December 18, 2017Publication date: April 9, 2020Inventor: Ki Won Kim
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Publication number: 20200111662Abstract: A method for forming a foreign oxide or foreign nitride layer (6) on a substrate (1) of a semiconductor comprises providing a semiconductor substrate (1) having an oxidized or nitridized surface layer (3), supplying a foreign element (5) on the oxidized or nitridized surface layer; and keeping the oxidized or nitridized surface layer (3) at an elevated temperature so as to oxidize or nitridize at least partially the foreign element by the oxygen or nitrogen, respectively, initially present in the oxidized or nitridized surface layer (3).Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Applicant: Turun YliopistoInventors: Mikhail KUZMIN, Pekka LAUKKANEN, Yasir MUHAMMAD, Marjukka TUOMINEN, Johnny DAHL, Veikko TUOMINEN, Jaakko MAKELA, Marko PUNKKINEN, Kalevi KOKKO
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Publication number: 20200111663Abstract: The present disclosure provides a calcium copper titanate film preparation method and a calcium copper titanate film, where the calcium copper titanate film has excellent step coverage, film thickness uniformity and film continuity, is particularly suitable for a high aspect ratio structure. The calcium copper titanate film preparation method includes: forming a layered deposition structure on a substrate, where the layered deposition structure includes at least one titanium dioxide layer, at least one copper oxide layer and at least one calcium oxide or calcium carbonate layer; and subjecting the layered deposition structure to high-temperature annealing treatment in an oxygen-containing atmosphere to obtain a calcium copper titanate film.Type: ApplicationFiled: November 1, 2019Publication date: April 9, 2020Inventors: Bin LU, Jian SHEN
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Publication number: 20200111664Abstract: Provided are a composition for depositing a silicon-containing thin film containing a bis(aminosilyl)alkylamine compound and a method for manufacturing a silicon-containing thin film using the same, and more particularly, a composition for depositing a silicon-containing thin film, containing the bis(aminosilyl)alkylamine compound capable of being usefully used as a precursor of the silicon-containing thin film, and a method for manufacturing a silicon-containing thin film using the same.Type: ApplicationFiled: March 28, 2018Publication date: April 9, 2020Inventors: Sung Gi KIM, Jeong Joo PARK, Joong Jin PARK, Se Jin JANG, Byeong-il YANG, Sang-Do LEE, Sam Dong LEE, Sang Ick LEE, Myong Woon KIM
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Publication number: 20200111665Abstract: Provided are a composition containing a silylamine compund and a method for manufacturing a silicon-containing thin film using the same, and more particularly, a composition for depositing a silicon-containing thin film, containing a silylamine compound capable of forming a silicon-containing thin film having a significantly excellent water vapor transmission rate to thereby be usefully used as a precursor of the silicon-containing thin film and an encapsulant of a display, and a method for manufacturing a silicon-containing thin film using the same.Type: ApplicationFiled: March 29, 2018Publication date: April 9, 2020Inventors: Sung Gi KIM, Jeong Joo PARK, Joong Jin PARK, Se Jin JANG, Byeong-il YANG, Sang-Do LEE, Sam Dong LEE, Sang Ick LEE, Myong Woon KIM
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Publication number: 20200111666Abstract: A substrate is positioned in exposure to a plasma generation region within a plasma processing chamber. A first plasma is generated within the plasma generation region. The first plasma is configured to cause deposition of a film on the substrate until the film deposited on the substrate reaches a threshold film thickness. The substrate is then exposed to ultraviolet radiation to resolve defects within the film deposited on the substrate. The ultraviolet radiation can be supplied in-situ using either a second plasma configured to generate ultraviolet radiation or an ultraviolet irradiation device disposed in exposure to the plasma generation region. The ultraviolet radiation can also be supplied ex-situ by moving the substrate to an ultraviolet irradiation device separate from the plasma processing chamber. The substrate can be exposed to the ultraviolet radiation in a repeated manner to resolve defects within the deposited film as the film thickness increases.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventor: Shankar Swaminathan
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Publication number: 20200111667Abstract: A method is presented for fabricating a substrate comprised of a compound semiconductor. The method includes: growing a sacrificial layer onto a parent substrate; growing an epitaxial template layer on the sacrificial layer; removing the template layer from the parent substrate using an epitaxial lift-off procedure; and bonding the removed template layer to a host substrate using Van der Waals forces and thereby forming a compound semiconductor substrate.Type: ApplicationFiled: October 8, 2019Publication date: April 9, 2020Inventors: Stephen R. FORREST, Kyusang LEE
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Publication number: 20200111668Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.Type: ApplicationFiled: October 8, 2018Publication date: April 9, 2020Inventors: Martin O'Toole, Keith Donegan, Brendan O'Brien, Hsueh-Chung Chen, Terry A. Spooner, Craig Child, Sean Reidy, Ravi Prakash Srivastava, Louis Lanzerotti, Atsushi Ogino
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Publication number: 20200111669Abstract: A method of depositing an oxide film on a template for patterning in semiconductor fabrication, includes: (i) providing a template having patterned structures thereon in a reaction space; and (ii) depositing an oxide film on the template by plasma-enhanced atomic layer deposition (PEALD) using nitrogen gas as a carrier gas and also as a dilution gas, thereby entirely covering with the oxide film an exposed top surface of the template and the patterned structures.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Masaru Zaitsu, Atsuki Fukazawa, Gama Trigagema
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Publication number: 20200111670Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
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SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20200111671Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Publication number: 20200111672Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.Type: ApplicationFiled: October 3, 2018Publication date: April 9, 2020Applicant: Ideal Power Inc.Inventors: Richard A. Blanchard, William C. Alexander
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Publication number: 20200111673Abstract: A method of forming a semiconductor device comprises patterning a mask material adjacent to an array of transistors, forming an electrically conductive material between adjacent portions of the patterned mask material, forming an additional mask material over the patterned mask material to form a mask structure, the additional mask material having an arcuate cross-sectional shape, removing a portion of the additional mask material to reduce a spacing between adjacent portions of the additional mask material, and forming capacitor structures in openings between the mask structure. Additional methods of forming a semiconductor device, and related semiconductor devices and related systems are also disclosed.Type: ApplicationFiled: October 8, 2018Publication date: April 9, 2020Inventor: Guangjun Yang
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Publication number: 20200111674Abstract: There is provided an etching method including: a step of disposing a substrate in a chamber, the substrate having a silicon nitride film, a silicon oxide film, a silicon, and a silicon germanium; a step of setting a pressure in the chamber to 1,333 Pa or more; and a step of selectively etching the silicon nitride film with respect to the silicon oxide film, the silicon, and the silicon germanium by supplying a hydrogen fluoride gas into the chamber.Type: ApplicationFiled: March 28, 2018Publication date: April 9, 2020Inventors: Reiko SASAHARA, Satoshi TODA, Takuya ABE, Tsuhung HUANG, Yoshie OZAWA, Ken NAKAGOMI, Kenichi NAKAHATA, Kenshiro ASAHI
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Publication number: 20200111675Abstract: There is provided a method of performing a surface processing on a substrate having a metal layer formed on a bottom portion of a recess formed in an insulating film, the method including: supplying a halogen-containing gas into a processing chamber in which the substrate is loaded; and removing a metal oxide from the bottom portion of the recess using the halogen-containing gas.Type: ApplicationFiled: September 30, 2019Publication date: April 9, 2020Inventors: Koichi TAKATSUKI, Tadahiro ISHIZAKA, Mikio SUZUKI, Toshio HASEGAWA
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Publication number: 20200111676Abstract: Methods of self-aligned multiple patterning. A mandrel is formed over a hardmask, and a planarizing layer is formed over the mandrel and the hardmask. The planarizing layer is patterned to form first and second trenches exposing respective first and second lengthwise sections of the mandrel. A portion of the patterned planarizing layer covers a third lengthwise section of the mandrel arranged between the first and second lengthwise sections of the mandrel. After patterning the planarizing layer, the first and second lengthwise sections of the mandrel are removed with an etching process to define a pattern including a mandrel line exposing respective first portions of the hardmask. The third lengthwise section of the mandrel is masked by the portion of the planarizing layer during the etching process, and the third lengthwise section covers a second portion of the hardmask arranged along the mandrel line between the first portions of the hardmask.Type: ApplicationFiled: October 8, 2018Publication date: April 9, 2020Inventors: Hsueh-Chung Chen, Brendan O'Brien, Martin O'Toole, Keith Donegan
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Publication number: 20200111677Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.Type: ApplicationFiled: October 8, 2018Publication date: April 9, 2020Inventors: Ravi Prakash Srivastava, Hsueh-Chung Chen, Steven McDermott, Martin O'Toole, Brendan O'Brien, Terry A. Spooner
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Publication number: 20200111678Abstract: A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.Type: ApplicationFiled: June 26, 2019Publication date: April 9, 2020Inventors: Sanggyo Chung, Kyoung Ha Eom, Hyunchul Lee, Sounghee Lee, Jiseung Lee
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Publication number: 20200111679Abstract: A method for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride, includes: preparing a target object including the first region and the second region in a processing chamber of a plasma processing apparatus; and generating a plasma of a processing gas containing a fluorocarbon gas and a rare gas in the processing chamber. In the generating the plasma of the processing gas, a self-bias potential of a lower electrode on which the target object is mounted is greater than or equal to 4V and smaller than or equal to 350V and a flow rate of the rare gas in the processing gas is 250 to 5000 times of a flow rate of the fluorocarbon gas in the processing gas.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Applicant: TOKYO ELECTRON LIMITEDInventors: Masahiro TABATA, Takayuki KATSUNUMA, Masanobu HONDA
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Publication number: 20200111680Abstract: An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.Type: ApplicationFiled: October 8, 2018Publication date: April 9, 2020Inventors: Raymond Albert Fillion, Kaustubh Ravindra Nagarkar
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Publication number: 20200111681Abstract: A method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer, and forming an upper re-distribution layer on the semiconductor chip and the stack.Type: ApplicationFiled: May 17, 2019Publication date: April 9, 2020Inventor: KYOUNG LIM SUK
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Publication number: 20200111682Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventors: Chen-Yu Tsai, Tsung-Shang Wei, Yu-Sheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
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Publication number: 20200111683Abstract: A method may include forming a set of walls on a surface of a substrate, the set of walls dividing the substrate into multiple sections, each of the multiple sections having at least one respective semiconductor device. The method may further include depositing a molding compound onto the substrate, the molding compound at least partially filling a space defined by the set of walls over each of the multiple sections and covering the respective semiconductor device of each of the multiple sections.Type: ApplicationFiled: October 9, 2018Publication date: April 9, 2020Inventor: John F. Kaeding
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Publication number: 20200111684Abstract: A method of fabricating a semiconductor may include forming on a substrate a mold structure including a mold layer, a buffer layer, and a support layer, performing on the mold structure an anisotropic etching process to form a plurality of through holes in the mold structure, and forming a plurality of bottom electrodes in the through holes. The buffer layer has a nitrogen content amount that increases as approaching the support layer from the mold layer. The buffer layer has an oxygen content amount that increases as approaching the mold layer from the support layer.Type: ApplicationFiled: April 30, 2019Publication date: April 9, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Byoungdeog CHOI, Jangseop Kim
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Publication number: 20200111685Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.Type: ApplicationFiled: October 9, 2018Publication date: April 9, 2020Inventors: Wiwat Tanwongwan, Amornthep Saiyajitara, Nathapop Lappanitpullpol