Abstract: An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.

Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.

Abstract: A device maintenance apparatus includes a setting operator configured to allow for setting a test pattern, the test pattern being set to define a change of output signals output from a device over time, and an execution operator configured to make the device output the output signals based on the set test pattern.

Abstract: A method for analyzing and prioritizing configuration parameters in an information technology system, including collecting configuration parameters from computer stations connected in a network implementing the information technology system, storing the collected configuration parameters in a database, analyzing the configuration parameters by a set of anomaly routines, wherein each anomaly routine checks for a specific type of anomaly and provides a score representing a level of conformity of the value of the configuration parameters to the anomaly, aggregating the anomaly scores; and outputting a list of configuration parameters with an aggregated anomaly score.

Abstract: A container monitoring method and apparatus, which are used for monitoring a plurality of monitored objects running on a physical machine. The type of plurality of monitored objects comprising at least one of a container, a process-in-container, or a thread-in-container. The physical machines comprising a primary monitor. The primary monitor receives monitoring information respectively reported by the multiple monitored objects. Monitoring information of monitored objects of a same type in the multiple monitored objects is reported by using a same channel. The primary monitor determines respective service statuses of the multiple monitored objects according to the monitoring information and unique identifiers. This can reduce resources consumed during monitoring in the prior art, and resolve a problem that a requirement for multidimensional monitoring on a container cannot be met due to high resource consumption.

Abstract: Systems and methods for maintaining data integrity across multiple applications are disclosed. In one example, a computer-implemented method includes monitoring, by a computing device, user data across multiple computer applications to detect trackable data, the trackable data including a first data set associated with a first application and a second data set associated with a second application; tracking, by the computing device, the trackable data; determining, by the computing device, that the first data set is similar to the second data set; identifying, by the computing device, a discrepancy between the first data set and the second data set; and implementing, by the computing device, a change to the first data set based on the second data set to automatically maintain integrity of the first and second data sets across the respective first and second applications.

Abstract: A method, performed by a computing device, includes (a) building a data structure that describes dependence relationships between components of a virtual appliance, the components comprising respective computational processes which may be invoked during booting, a dependence relationship indicating that one component must complete before a second component may be invoked, (b) identifying, with reference to the data structure and an essential set of components which were pre-defined to be essential to the virtual appliance, a set of components that must complete for booting to be considered finished, and, after identifying the required set of components, repeatedly (c) querying each required component for its respective completion status, (d) calculating an estimated completion percentage for booting the virtual appliance with reference to the respective completion statuses of each required component versus all required components, and (e) displaying an indication of the completion percentage to a user via a u

Abstract: In a computing environment having multiple application servers each having at least one connection agent and at least one pause agent and a database node, detecting an error condition between a first application server from the multiple application servers and the database node. Indicating that the database node is unavailable to stop attempts to access the database node by a first application server. The attempts to access the database node are paused without an indication of the database node being unavailable to a source of the attempt to access the database node. Checking periodically, with the first application server, availability of the database node. Indicating that the database node is available in response to a pre-selected number of successful attempts to contact the database node with the first application server.

Abstract: A first device comprises: a memory configured to store a first sub-graph that is part of a distributed graph associated with a distributed graph processing network; a processor coupled to the memory and configured to: process the first sub-graph; and save, independently of a second device in the distributed graph processing network, a first snapshot of a first execution state of the first device at a first iteration time; and a transmitter coupled to the processor and configured to transmit the first snapshot to the second device or to a third device.

Abstract: Systems and methods for performing unsupervised baselining and anomaly detection using time-series data are described. In one or more embodiments, a baselining and anomaly detection system receives a set of time-series data. Based on the set of time-series, the system generates a first interval that represents a first distribution of sample values associated with the first seasonal pattern and a second interval that represents a second distribution of sample values associated with the second seasonal pattern. The system then monitors a time-series signals using the first interval during a first time period and the second interval during a second time period. In response to detecting an anomaly in the first seasonal pattern or the second seasonal pattern, the system generates an alert.

Abstract: A computer readable medium storing a computer program for providing a method for evaluating the performance of a software application, the computer program executable by at least one or the one or more processors. The computer program comprising a set of instructions for receiving an indication of the initiation of a workflow transaction in an Application, determining whether the workflow transaction is to be marked as a traceable transaction based on a Measurement Marker Algorithm, tracking the performance of operations executed for the workflow transaction, and storing raw Call Metrics based on the tracked performance in an Intermediate memory.

Abstract: A system, includes: a distributed cache that stores state information for a plurality of configuration items (CIs). Management, instrumentation, and discovery (MID) servers form a cluster, each of the MID servers including one or more processors that receive, from the distributed cache, a subset of the state information associated with assigned CIs and perform a statistical analysis on the subset of the state information.

Abstract: In one embodiment, an integrated development environment (IDE) is maintained on a computing device for managing software code for one or more software programs. At the IDE on the computing device, one or more code changes to the software code are determined between a given version of the software code and a subsequent version of the software code, and then a performance impact of each of the one or more code changes is determined. The IDE (or IDE plugin) prepares user-understandable indications of the performance impact of the one or more code changes, and displays the user-understandable indications of the performance impact in a graphical user interface (GUI) when a respective code change is displayed in the GUI.

Abstract: Techniques are described for sampling across trusted and untrusted distributed components. In accordance with embodiments, a first computing device receives a request from a second computing device, the first request including an operation identifier (ID) and a sampling ID that was generated by transforming a telemetry scope ID from a first value in a first domain to a second value in a second domain. The transformation may serve to anonymize and compress the telemetry scope ID. The first computing device determines whether or not to sample by comparing a ratio between the sampling ID and a size of the second domain with a sampling rate associated with the first computing device. The first computing device records telemetry about its processing of the first request in response to determining to sample and does not record any telemetry about its processing of the first request in response to determining not to sample.

Abstract: A method and a system for monitoring batch processing of applications executed in IT infrastructure. The method being implemented by monitoring software configured for detection of at least one congestion incident of the computing resources of said infrastructure and for identification of at least one batch at the origin of said incident, by way of the following steps: recording of the usual consumption of said resources by the batches; follow-up of the execution of the batches over time; measuring, by a monitoring tool, of the instantaneous consumption of said resources; comparison, for said identification, between the instantaneous consumption and the usual consumption of each of the batches executed during a period close to the incident.

Abstract: A streams analysis tool allows a user to define one or more buckets according to a specified tuple collection criteria for each bucket. The specified tuple collection criteria for each bucket defines some way to distinguish one data tuple from another. The specified tuple collection criteria for each bucket is therefore used to distinguish data tuples that satisfy the specified tuple collection criteria from data tuples that do not satisfy the specified tuple collection criteria. When a data tuple satisfies the specified tuple collection criteria for a bucket, the data tuple is stored in the bucket. In addition, data tuples preceding or succeeding the data tuple may also be stored in the bucket, as determined by the specified tuple collection criteria. The data tuples in each bucket are analyzed, and based on the analysis a streams manager can change how future data tuples are processed by the streaming application.

Abstract: Techniques for profiling memory leaks are described. In one or more embodiments, a memory profiling system identifies a set of one or more objects on the heap during application runtime. For each respective object in the subset of objects, the memory profiling system stores a set of sample information including timestamp that identifies a time associated with an allocation on the heap memory was performed for the respective object and a stack trace identifying at least one subroutine that triggered the allocation on the heap memory. Responsive to detecting a memory leak, the memory profiling system generates a memory leak profile for at least one object in the subset of objects that is causing the memory leak. The memory leak profile identifies when the allocation on the memory store for the at least one object was performed and information about object that remained live after the potential memory leak.

Abstract: An apparatus with a standard zone and a test zone, where the standard zone includes a standard execution environment providing access to genuine resources of the apparatus and the test zone includes a test execution environment providing access to mock resources, with a mock resource modeling a genuine resource of the apparatus. The application has access to the genuine resources when the application is executed in the standard zone. The application has access to the mock resources when the application is executed in the test zone and the application does not have access to the genuine resources when the application is executed in the test zone.

Abstract: Example implementations described herein are directed to systems and methods for validating and deploying microservices. In an example implementation, a plurality of similarities are calculated between a user environment and multiple pilot environments from application deployment test results. The test results are based on compatibility of catalogs of applications with each of the pilot environments. A list is presented with one or more of the catalogs of applications that are indicated as compatible and similar to the user environment based on the calculated similarities. The user can select catalog from the list that is deployed in the user environment.

Abstract: A method and system including a display; at least one application programming interface (API) including one or more parameters, wherein the API communicates with a code of a system under test; a code testing module including a multiple variant generation and handling module; and a code testing processor in communication with the code testing module and operative to execute processor-executable process steps to cause the system to: receive data identifying the API; display one or more parameters associated with the API; generate, with the multiple variant generation and handling module, one or more variants based on values associated with the one or more parameters; receive the one or more generated variants at a variant injector; inject the one or more generated variants into the code via the API; and execute the code with the one or more injected generated variants. Numerous other aspects are provided.

Abstract: A method is disclosed for testing launched applications on a desktop environment. The method captures a screenshot from the launched application. The screenshot may then be analyzed to determine whether it is a modal screenshot or a clean screenshot. In the event the screenshot is determined to be a modal screenshot, the modal screenshot may be classified, and, if classified, information may be sought to resolve the problem with the modal screenshot. In the screenshot is determined to be a clean screenshot, the clean screenshot is evaluated against stored reference screenshots to identify a match.

Abstract: Application servers, AS, for use in live and test enterprise resource planning, ERP, systems and a test ERP system for testing an update to the live ERP system are described. A system transaction recorder of the live ERP system captures live system transaction data comprising a plurality of live system transaction inputs and a plurality of live system transaction outputs. A receiver of an AS of the test ERP system receives the system transaction data and a system tester applies the plurality of live system transaction inputs to a plurality of test ERP system transactions corresponding to the plurality of system transactions undertaken in the live ERP system, such that a plurality of test system transaction outputs are produced. An error detector determines whether there has been any error in the test ERP system based on the plurality of test system transaction outputs.

Abstract: According to some examples, computer-implemented methods for branch coverage guided symbolic execution for hybrid fuzzing are described. An example computer-implemented method may include receiving a seed input of a binary program under analysis (BPUA) that is discovered during testing by a greybox fuzzer. The method may also include concretely executing the seed input in the BPUA, and collecting a trace resulting from the concrete execution of the seed input. The method may further include determining whether the concrete execution of the seed input discovers a new branch. The method may include, responsive to a determination that the concrete execution of the seed input discovers a new branch, updating a bitmap to indicate that the new branch is discovered, wherein the bitmap is utilized by the greybox fuzzer to maintain a record of discovered branches in BPUA, and providing the seed input to the greybox fuzzer.

Abstract: A computer-implemented method may include: receiving a request to integrate a commit; obtaining analytics data of an author that developed the commit; executing a simulation using the analytics data of the author as inputs to the simulation; obtaining results from the simulation, wherein the results indicate error rates when one or more testing stages are omitted from a testing procedure of the commit; comparing the results of the simulation with a threshold; determining, by the computing the device, the testing procedure based on the comparing, wherein the testing procedure identifies the one or more testing stages that are omitted and one or more testing stages that are included in the testing procedure; and outputting information regarding the determined testing procedure, wherein the outputting causes an integration server to test the commit in accordance with the testing procedure as part of an integration process for integrating the commit to a project.

Abstract: A system, method, and computer program product are provided for periodic memory leak detection. In operation, a system monitors one or more processes that perform dynamic memory allocations. The system receives a data type indicator indicating a type of data associated with the dynamic memory allocations to collect. The system receives a time indicator indicating a time period for monitoring and collecting data associated with the data type indicator. The system collects the data associated with the data type indicator for the one or more processes for the time period. Moreover, the system generates a report based on the collected data associated with the data type indicator for the one or more processes.

Abstract: A system and method of optimizing tree pruning for a decision tree may include splitting, a first dataset into a training dataset and a testing dataset, growing the training dataset into a first decision tree, sampling the training dataset by creating a plurality of sampling datasets from the training dataset, pruning the first decision tree using the plurality of sampling datasets, creating a plurality of models, at least one for each of the plurality of sampling datasets, and verifying the accuracy of each of the plurality of models, using the testing dataset.

Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.

Abstract: A garbage collection method comprises selecting one or blocks in a SSD of a hybrid drive for garbage collection; determining a state of data of the one or more selected blocks, wherein the state suggests a location and temperature of data; and executing a garbage collection efficiency and caching efficiency action on the data of the one or more selected blocks based on the determined state. The garbage collection process may utilize the state information provided by the cache layer of the hybrid drive to make decisions regarding data in the one or more selected blocks.

Abstract: A memory system includes: a memory device suitable for including a plurality of pages where data are stored and a plurality of memory blocks including the pages; and a controller suitable for receiving a plurality of commands from a host, performing command operations in response to the commands in the memory blocks, updating map data for the memory blocks according to the command operations being performed, and registering information on the map data in a data table for each of the memory blocks.

Abstract: A memory management method is provided. The method includes in response to completion of a garbage collection operation, identifying one or more recycled block stripes subjected to the garbage collection operation among a plurality of block stripes of a rewritable non-volatile memory module; updating a garbage collection information table in a buffer memory according to the one or more recycled block stripes; and writing the garbage collection information table into the rewritable non-volatile memory module.

Abstract: Systems and methods for host system memory translation are disclosed. The memory system may send a logical-to-physical address translation table to the host system. Thereafter, the host system may send commands that include a logical address and a physical address (with the host system using the logical-to-physical address translation table previously sent to generate the physical address). After sending the table to the host system, the memory system may monitor changes in the table, and record these changes in an update table. The memory system may use the update table in determining whether to accept or reject the physical address sent from the host system in processing the host system command. In response to determining to reject the physical address, the memory system may internally generate the physical address using the logical address sent from the host system and a logical-to-physical address translation table resident in the memory system.

Abstract: In an on-chip copy process, performed by a storage device, data is copied from a plurality of Single Level Cell (SLC) blocks of non-volatile three-dimensional memory (e.g., 3D flash memory) in a respective memory die to a Multilevel Cell (MLC) block of the same memory die. A copy of source data from a respective SLC block is interleaved with a copy of source data from one or more other SLC blocks in the memory die to produce interleaved source data. Each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respective SLC block in the plurality of SLC blocks is assigned a distinct offset. Each distinct set of the interleaved source data is written to a distinct respective MLC page of the MLC block.

Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

Abstract: According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.

Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

Abstract: Systems and methods selectively filter, buffer, and process cache coherency probes. A processor includes a probe buffering unit that includes a cache coherency probe buffer. The probe buffering unit receives cache coherency probes and memory access requests for a cache. The probe buffering unit identifies and discards any of the probes that are directed to a memory block that is not cached in the cache, and buffers at least a subset of the remaining probes in the probe buffer. The probe buffering unit submits to the cache, in descending order of priority, one or more of: any buffered probes that are directed to the memory block to which a current memory access request is also directed; any current memory access requests that are directed to a memory block to which there is not a buffered probe also directed; and any buffered probes when there is not a current memory access request.

Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization. Based on determining that the rate is to be changed, the rate of prefetching is changed.

Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.

Abstract: One embodiment is related to a method for redistributing cache space, comprising: determining utility values associated with all of a plurality of clients, each client being associated with a respective utility value, the utility value being indicative of an efficiency of cache space usage of the associated client; and redistributing cache space among the plurality of clients based on the utility values.

Abstract: Systems and methods for handling operation requests in a computing device. The methods comprise: queuing a first I/O operation and first TRIM operation in a first list of operations; analyzing the first TRIM operation for a plurality of block portions of a disk cache to determine a size thereof; estimating a first amount of time to complete the first TRIM operation; comparing the first amount of time to a first threshold value; selectively dividing the first TRIM operation into at least a second TRIM operation for first block portions contained in the plurality of block portions and at least a third TRIM operation for second block portions contained in the plurality of block portions, if the first amount of time is greater than the first threshold value; performing the first I/O operation followed by the second TRIM operation; and queuing the third TRIM operation in a second list of operations.

Abstract: Disclosed herein is an information processing device including a host unit adapted to request data access by specifying a logical address of a secondary storage device, and a controller adapted to accept the data access request and convert the logical address into a physical address using an address conversion table to perform data access to an associated area of the secondary storage device, in which an address space defined by the address conversion table includes a coarsely granular address space that collectively associates, with logical addresses, physical addresses that are in units larger than those in which data is read.

Abstract: A technique for managing a read cache in an eventually-consistent data store includes, in response to a read request for a specified data element, receiving the specified data element from the read cache as well as a remaining TTL (time to live) of the data element, as indicated by a timer for that data element in the read cache. If the remaining TTL falls below a predetermined value, the technique triggers an early refresh of the specified data element, prior to its expiration. Consequently, later-arriving read requests to the same data element that arrive before the data element has been refreshed experience cache hits, thus avoiding the need to perform their own time-consuming refresh operations.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine one or more logical block addresses for a persistent storage media, determine one or more addresses for a physical memory space, and define a memory-mapped input/output region for the physical memory space with a direct mapping between the one or more addresses for the physical memory space and the one or more logical block addresses for the persistent storage media. Other embodiments are disclosed and claimed.

Abstract: An apparatus includes a storage controller, a non-volatile memory die comprising a set of memory elements and a memory die controller associated with the non-volatile memory die. The memory die controller is configured to identify a portion of the non-volatile memory die for mapping logical addresses, read a header of a sub-portion of the identified portion, for a logical address, map a physical address corresponding to the logical address of the sub-portion to a physical-to-logical mapping and transmit the physical-to-logical mapping to the storage controller.

Abstract: The disclosure provides an approach for tracking metadata (e.g., accessed and dirty bits) of page tables at finer granularity than the size of the page tables. A disclosed herein, modification to existing hardware design may enable finer page table granularity of metadata, leading to more precise representation of the state of memory and an improvement to system performance and efficiency. Finer grain dirty metadata can dramatically improve the efficiency and simplicity of subsystems.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

Abstract: Address translation of a base address prior to receiving a storage reference to use the address. A determination is made that an address has been obtained that is to be used as a base address for a memory location at which one or more in-memory configuration state registers are stored. Based on the determining, the address is translated into another address, and the translating is performed prior to receiving a storage reference to use the base address.

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.