Patents Issued in April 30, 2020
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Publication number: 20200135218Abstract: A signal processing method and device includes obtaining spectral coefficients of a current frame of an audio signal, in which N sub-bands of the current frame comprises at least one of the spectral coefficients. A total energy of M successive sub-bands of the N sub-bands, a total energy of K successive sub-bands of the N sub-bands, and an energy of a first sub-band are obtained to determine whether to modify original envelope values of the M sub-bands. When the original envelope values of the M sub-bands are modified, encoding bits are allocated to each of the N sub-bands according to the modified envelope values of the M sub-bands.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Inventors: Bin Wang, Lei Miao, Zexin Liu
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Publication number: 20200135219Abstract: A audio signal encoding method and apparatus includes: obtaining an audio signal comprising a plurality of sub-bands, wherein each sub-band has an index; obtaining a spectrum energy of each sub-band of at least a part of the plurality of sub-bands; obtaining a highest index of a sub-band to be allocated bits according to the spectrum energy and a ratio factor, wherein the ratio factor is greater than 0 and less than 1; allocating at least one bit for a sub-band having an index no greater than the highest index; and encoding a spectrum coefficient of the sub-band having the index no greater than the highest index with the allocated at least one bit. In this manner, the signal bandwidth is effectively coded and decoded by centralizing the bits.Type: ApplicationFiled: December 31, 2019Publication date: April 30, 2020Inventors: Fengyan QI, Zexin LIU, Lei MIAO
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Publication number: 20200135220Abstract: Disclosed are an audio signal encoding method and audio signal decoding method, and an encoder and decoder performing the same. The audio signal encoding method includes applying an audio signal to a training model including N autoencoders provided in a cascade structure, encoding an output result derived through the training model, and generating a bitstream with respect to the audio signal based on the encoded output result.Type: ApplicationFiled: August 16, 2019Publication date: April 30, 2020Applicants: Electronics and Telecommunications Research Institute, THE TRUSTEES OF INDIANA UNIVERSITYInventors: Mi Suk LEE, Jongmo SUNG, Minje KIM, Kai ZHEN
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Publication number: 20200135221Abstract: A wireless digital audio system includes a portable audio source with a digital audio transmitter operatively coupled thereto and an audio receiver operatively coupled to a headphone set. The audio receiver is configured for digital wireless communication with the audio transmitter. The digital audio receiver utilizes fuzzy logic to optimize digital signal processing. Each of the digital audio transmitter and receiver is configured for code division multiple access (CDMA) communication. The wireless digital audio system allows private audio enjoyment without interference from other users of independent wireless digital transmitters and receivers sharing the same space.Type: ApplicationFiled: November 1, 2019Publication date: April 30, 2020Inventor: C. Earl Woolfork
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Publication number: 20200135222Abstract: In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for formatting a payload for transmission of multi-mode speech/audio codec data. The method comprises deciding whether a header-less or a header-full payload format is used for transmission of a coded frame. The decision is based on a codec mode and a required functionality. The payload data is packetized with or without the payload header depending on the decision.Type: ApplicationFiled: December 26, 2019Publication date: April 30, 2020Applicant: Telefonaktiebolaget LM Ericsson (publ)Inventor: Stefan BRUHN
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Publication number: 20200135223Abstract: A system and method are provided for very short pitch detection and coding for speech or audio signals. The system and method include detecting whether there is a very short pitch lag in a speech or audio signal that is shorter than a conventional minimum pitch limitation using a combination of time domain and frequency domain pitch detection techniques. The pitch detection techniques include using pitch correlations in time domain and detecting a lack of low frequency energy in the speech or audio signal in frequency domain. The detected very short pitch lag is coded using a pitch range from a predetermined minimum very short pitch limitation.Type: ApplicationFiled: October 30, 2019Publication date: April 30, 2020Inventors: Yang Gao, Fengyan Qi
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Publication number: 20200135224Abstract: An audio cancellation system includes a voice enabled computing system that is connected to an audio output device using a wired or wireless communication network. The voice enabled computing device can provide media content to a user and receive a voice command from the user. The connection between the voice enabled computing system and the audio output device introduces a time delay between the media content being generated at the voice enabled computing device and the media content being reproduced at the audio output device. The system operates to determine a calibration value adapted for the voice enabled computing system and the audio output device. The system uses the calibration value to filter the user's voice command from a recording of ambient sound including the media content, without requiring significant use of memory and computing resources.Type: ApplicationFiled: October 4, 2019Publication date: April 30, 2020Applicant: Spotify ABInventors: Daniel Bromand, Richard Mitic
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Publication number: 20200135225Abstract: One or more processors identify one or more users expected to consume media content having associated subtitle data. A user profile associated with each of the one or more users is received, and one or more features are extracted from each user profile. The one or more features are representative of a characteristic of the user. A group profile is created for the one or more users based upon the extracted features. The subtitle data associated with the media content is received, and one or more portions of the subtitle data are modified based upon the group profile to generate augmented subtitle data. The augmented subtitle data is sent to a display device for being rendered in the display device.Type: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Applicant: International Business Machines CorporationInventors: Garfield Vaughn, Moncef Benboubakeur, Julija Narodicka, Aaron K. Baughman
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Publication number: 20200135226Abstract: A computer-implemented technique for animating a visual representation of a face based on spoken words of a speaker is described herein. A computing device receives an audio sequence comprising content features reflective of spoken words uttered by a speaker. The computing device generates latent content variables and latent style variables based upon the audio sequence. The latent content variables are used to synchronized movement of lips on the visual representation to the spoken words uttered by the speaker. The latent style variables are derived from an expected appearance of facial features of the speaker as the speaker utters the spoken words and are used to synchronize movement of full facial features of the visual representation to the spoken words uttered by the speaker. The computing device causes the visual representation of the face to be animated on a display based upon the latent content variables and the latent style variables.Type: ApplicationFiled: October 29, 2018Publication date: April 30, 2020Inventors: Gaurav MITTAL, Baoyuan WANG
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Publication number: 20200135227Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying the language of a spoken utterance. One of the methods includes receiving input features of an utterance; and processing the input features using an acoustic model that comprises one or more convolutional neural network (CNN) layers, one or more long short-term memory network (LSTM) layers, and one or more fully connected neural network layers to generate a transcription for the utterance.Type: ApplicationFiled: December 31, 2019Publication date: April 30, 2020Inventors: Tara N. Sainath, Andrew W. Senior, Oriol Vinyals, Hasim Sak
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Publication number: 20200135228Abstract: The present application relates to a method and device for recognizing the state of a human body meridian by utilizing a voice recognition technology, the method comprising: receiving an input voice of a user; preprocessing the input voice; extracting a stable feature of the preprocessed input voice; primarily classifying the stable feature on the basis of a feature recognition model, and determining a basic classification pitch, wherein the basic classification pitch comprises Gong, Shang, Jue, Zhi and Yu (respectively equivalent to do, re, mi, sol and la); secondarily classifying the stable feature on the basis of the feature recognition model, and determining a secondary classification tone in the basic classification pitch; and recognizing the state of a meridian according to the secondary classification tone.Type: ApplicationFiled: October 23, 2019Publication date: April 30, 2020Inventor: Zhonghua CI
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Publication number: 20200135229Abstract: A method including receiving one or more datasets of audio data of a key child captured in a natural sound environment of the key child. The method also includes segmenting each of the one or more datasets of audio data to create audio segments. The audio segments include cry-related segments and non-cry segments. The method additionally includes determining periods of the cry-related segments that satisfy one or more threshold non-sparsity criteria. The method further includes performing a classification on the periods to classify each of the periods as either a cry period or a fussiness period. Other embodiments are described.Type: ApplicationFiled: December 26, 2019Publication date: April 30, 2020Applicant: LENA FoundationInventors: Jeffrey A. Richards, Stephen M. Hannon
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Publication number: 20200135230Abstract: System and method for acoustic signal processing are disclosed. An exemplary device for acoustic signal processing includes a voice activity detector configured to detect a speech of a user. The device includes a microphone configured to receive acoustic signals from the user. The device further includes at least one processor configured to process the acoustic signals in response to detecting the speech of the user. The at least one processor is in an idle state before the speech of the user is detected.Type: ApplicationFiled: April 29, 2019Publication date: April 30, 2020Applicant: BESTECHNIC (SHANGHAI) CO., LTD.Inventors: Weifeng Tong, Qian Li, Liang Zhang
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Publication number: 20200135231Abstract: according to one embodiment, in a storage device, a selection circuit selects one mapping rule from a plurality of mapping rules in which each of bit labels having a bit length of (n+1) or more is mapped to n M-ary symbols, when M is defined as an integer of 3 or more and n is defined as an integer of or more. A first conversion circuit converts a data block in data into an M-ary symbol sequence using the selected one mapping rule. A second conversion circuit converts the converted M-ary symbol sequence into an M-step pulse width signal. The recording medium records the converted M-step pulse width signal. A readback circuit equalizes the signal read from the recording medium to the M-ary symbol sequence and restores the data.Type: ApplicationFiled: August 28, 2019Publication date: April 30, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Kohsuke HARADA
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Publication number: 20200135232Abstract: Provided herein is an apparatus including a disk drive base, wherein the disk drive base includes a first metal composition with a first CTE (“coefficient of thermal expansion”). A disk drive cover is attached to the disk drive base, wherein the disk drive cover includes a second metal composition with a second CTE that are different from the first metal composition and the first CTE. An arm is connected to a reader and a writer, wherein the arm is coupled to the disk drive base, the reader and the writer are separated by a distance, and the distance affects an MR (“magnetoresistive”) offset. In response to temperature changes between 0° C. and 60° C., the first material and the second material expand and contract comparably and proportionally. In further response to the temperature changes between 0° C. and 60° C., a change in the MR offset is less than 10% or a preferably defined range of a track pitch on a recording medium attached to the disk drive base.Type: ApplicationFiled: October 29, 2018Publication date: April 30, 2020Inventors: Xiong LIU, Lihong ZHANG
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Publication number: 20200135233Abstract: A storage medium controller has been designed to maintain thermal stability of a heat source based on a history of heat source active/inactive durations so that a variation in spot size generated by the heat source is reduced during Heat Assisted Magnetic Recording (HAMR). The storage medium controller modulates power to the heat source based on these active/inactive durations. While the heat source is inactive, the storage medium controller increases a thermal compensation value and after the heat source is activated, the storage medium controller drives the heat source according to a current parameter proportional to the thermal compensation value. As the heat source continues being active, the storage medium controller decreases the thermal compensation value and proportional current parameter so that thermal stability of the heat source is maintained.Type: ApplicationFiled: October 29, 2019Publication date: April 30, 2020Applicant: Marvell World Trade Ltd.Inventors: Mats Oberg, Hao Fang
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Publication number: 20200135234Abstract: A calibration system includes a moveable arm configured for movement within an optical disc storage system. A disc kicker device includes a stop portion, an actuator and an actuator tip that contacts an optical disc. The disc kicker device is connected to the moveable arm. The calibration system: determines an operation state based on a stop position for the actuator tip in response to an applied torque to the disc kicker device, and performs alignment of the actuator tip with the optical disc.Type: ApplicationFiled: November 22, 2019Publication date: April 30, 2020Inventors: Daniel F. Smith, David Jame Altknecht
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Publication number: 20200135235Abstract: The present technology is a video recording system and method of recording a video while applying special effects in real time prior to and/or while recording. The system includes a processing unit in communication with a camera and a memory unit. The processor receives a raw video data at a native speed rate from the camera or remote video stream, and an input from an interface. The system determines if the native speed rate of the raw video data is to be changed, and if so then modifies at least one frame in the raw video data to create a modified video data at a modified speed rate that is different to the native speed rate. The system then generates an output video recording data and writes it to memory. This allows for the continuous recording of video from the camera or video feed at different speed rates without altering camera operations or settings.Type: ApplicationFiled: June 28, 2019Publication date: April 30, 2020Inventors: Henry M. Pena, Thomas F. Bryant, III
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Publication number: 20200135236Abstract: A mobile device enables a user to edit a video containing a human figure, such that an original human pose is modified into a target human pose in the video. In response to a user command, the mobile device first identifies key points of the human figure from a frame of the video. The user command indicates a target position of a given key point of the key points. The mobile device generates a target frame including the target human pose, with the given key point of the target human pose at the target position. An edited frame sequence is generated on the display including the target frame. The edited frame sequence shows the movement of the human pose transitioning into the target human pose.Type: ApplicationFiled: October 29, 2018Publication date: April 30, 2020Inventors: Shih-Jung Chuang, Cheng-Lung Jen, Chih-Chung Chiang, Hsin-Ying Ko
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Publication number: 20200135237Abstract: Embodiments involve harmonising one or more geographically or temporally distributed renditions with at least one backing clip, comprising a calibration module for selecting a parameter of one or more aural or visual characteristics of the first rendition, a backing clip selector in communication with a backing clip database, a reference selector for selecting reference clip for modification of the first rendition, a modification module for applying a computational process to the first rendition or the backing clip to modify an aural characteristic of the first rendition or the backing clip to reduce the difference between the first rendition or the backing clip and the reference clip in the aural characteristic, and a mixing module to combine one or multiple renditions with the backing clip after modification.Type: ApplicationFiled: June 29, 2018Publication date: April 30, 2020Inventors: Marty Gauvin, Andrew Downing, Patricia Rix
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Publication number: 20200135238Abstract: A spherical content capture system captures spherical video and audio content. In one embodiment, captured metadata or video/audio processing is used to identify content relevant to a particular user based on time and location information. The platform can then generate an output video from one or more shared spherical content files relevant to the user. The output video may include a non-spherical reduced field of view such as those commonly associated with conventional camera systems. Particularly, relevant sub-frames having a reduced field of view may be extracted from each frame of spherical video to generate an output video that tracks a particular individual or object of interest. For each sub-frame, a corresponding portion of an audio track is generated that includes a directional audio signal having a directionality based on the selected sub-frame.Type: ApplicationFiled: December 19, 2019Publication date: April 30, 2020Inventors: Scott Patrick Campbell, Zhinian Jing, Timothy Macmillan, David A. Newman, Balineedu Chowdary Adsumilli
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Publication number: 20200135239Abstract: A shock absorber apparatus is provided. The shock absorber apparatus includes an elastic device and at least one mounting device connected to the elastic device. Each mounting device includes two securing elements. Each securing element is configured to secure an opposing portion of a structure. Each mounting device can also include two sliders. Each slider can have at least two surfaces, which are interconnected by an inclined surface facing an opposing slider, and a ground surface. The inclined surface can be slidably connected to one of the at least two securing elements. Each slider can be arranged to move in response to an applied force. The ground surface is configured to slidably connect to an inner wall of a box.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Inventors: Chao-Jung CHEN, Ming-Sheng CHANG, Po-Yu YANG, Sheng-Wei TANG
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Publication number: 20200135240Abstract: A slider is provided with a conformal coating (e.g., an oxide) on the air-bearing surface (ABS) to provide a consistent surface energy to the ABS. The conformal coating may be formed by an atomic layer deposition (ALD) process. A consistent surface energy inhibits accumulation of contaminants on the slider ABS, such as at topographical transition areas.Type: ApplicationFiled: December 20, 2019Publication date: April 30, 2020Inventors: Byung Seok KWON, David ELLISON
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Publication number: 20200135241Abstract: A memory structure includes a first memory cell, a first word line and a second word line. The first word line includes a first portion, a second portion and a third portion. The first portion extends from an end of the second portion along a first direction, and the third portion extends from an another end of the second portion along a second direction. An angle between the first direction and the second direction is less than 180°. The second word line includes a forth portion, a fifth portion and a sixth portion. The forth portion extends from an end of the fifth portion along a third direction, and the sixth portion extends from an another end of the fifth portion along a forth direction. An angle between the third direction and the forth direction is less than 180°.Type: ApplicationFiled: October 28, 2018Publication date: April 30, 2020Inventors: Wei-Chih WANG, Tseng-Fu LU
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Publication number: 20200135242Abstract: According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer.Type: ApplicationFiled: July 3, 2019Publication date: April 30, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Fumitaka ARAI, Keiji HOSOTANI, Nobuyuki MOMO
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Publication number: 20200135243Abstract: A semiconductor integrated circuit includes a sense amplifier circuit suitable for generating differential output signals by sensing and amplifying a level difference of differential input signals in response to a clock signal, and outputting the differential output signals to first and second nodes, respectively, a latch circuit suitable for feeding back and latching the differential output signals between the first and second nodes, and a control circuit suitable for controlling the feedback of the differential output signals between the first and second nodes in response to an initialization signal.Type: ApplicationFiled: October 10, 2019Publication date: April 30, 2020Inventors: SungWoo KIM, InHwa JUNG
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Publication number: 20200135244Abstract: The present disclosure relates to a driving circuit including a first circuit, a transistor switch, and a voltage level conversion circuit. The first circuit includes an operational amplifier and a feedback circuit, and is configured to output a first signal (e.g., an analog signal). The feedback circuit is configured to feed back the first signal to the operational amplifier. A source terminal and a drain terminal of the transistor switch are respectively electrically coupled to the operational amplifier and an output pin of the driving circuit. The voltage level conversion circuit is connected to the source terminal and a gate terminal of the transistor switch. When the voltage level conversion circuit is enabled, a voltage difference between the gate terminal and the source terminal of the transistor switch is controlled to a set value, so that the first signal is output to the output pin through the transistor switch.Type: ApplicationFiled: July 16, 2019Publication date: April 30, 2020Inventors: Chia-Ling CHANG, Wei-Cheng TANG, Li-Lung KAO, Che-Hung LIN
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Publication number: 20200135245Abstract: A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.Type: ApplicationFiled: July 26, 2019Publication date: April 30, 2020Inventor: Ed McCombs
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Publication number: 20200135246Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.Type: ApplicationFiled: November 5, 2019Publication date: April 30, 2020Inventors: Steven Craig Bartling, Sudhanshu Khanna
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Publication number: 20200135247Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: ApplicationFiled: December 19, 2019Publication date: April 30, 2020Inventors: YOUNG-HOON SON, SI-HONG KIM, CHANG-KYO LEE, JUNG-HWAN CHOI, KYUNG-SOO HA
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Publication number: 20200135248Abstract: A semiconductor device includes a control circuit and an address generation circuit. The control circuit generates a write column address signal, a write bank selection signal and an internal write bank selection signal from a command/address signal during a write operation. The control circuit also generates a read column address signal, a read bank selection signal and an internal read bank selection signal from the command/address signal during a read operation. The address generation circuit outputs the write column address signal as a bank group address signal in synchronization with the write bank selection signal and the internal write bank selection signal or outputs the read column address signal as the bank group address signal in synchronization with the read bank selection signal and the internal read bank selection signal.Type: ApplicationFiled: April 30, 2019Publication date: April 30, 2020Applicant: SK hynix Inc.Inventor: Woongrae KIM
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Publication number: 20200135249Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state.Type: ApplicationFiled: December 27, 2019Publication date: April 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventor: Christopher Kawamura
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Publication number: 20200135250Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Dean K. Nobunaga, Ebrahim Abedifard
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Publication number: 20200135251Abstract: A memory cell includes a memory cell stack, a first word line, a second word line, a bit line coupled to one end of the memory cell stack, a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line, and a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line. Current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other.Type: ApplicationFiled: October 1, 2019Publication date: April 30, 2020Inventors: Randy OSBORNE, Kevin Xiaoqiang ZHANG
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Publication number: 20200135252Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.Type: ApplicationFiled: July 3, 2019Publication date: April 30, 2020Inventors: Gaurav Gupta, Zhiqiang Wu
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Publication number: 20200135253Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.Type: ApplicationFiled: October 16, 2019Publication date: April 30, 2020Inventors: Gaurav Gupta, Zhiqiang Wu, Yih Wang
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Publication number: 20200135254Abstract: A memory is capable of storing coupled qubits. The memory includes a plurality of memory cells, wherein each of the memory cells is for storing values of one of the qubits. The memory also includes an electronic controller electrically connected to operate said memory cells. The controller is able to selectively store a qubit value to any of the memory cells in either a first state or a second state. The controller is configured to read any one of the memory cells in a manner dependent on whether the first state or the second state was previously used to store a qubit value in the same one of the memory cells.Type: ApplicationFiled: October 17, 2019Publication date: April 30, 2020Inventor: Robert L. Willett
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Publication number: 20200135255Abstract: A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.Type: ApplicationFiled: December 24, 2018Publication date: April 30, 2020Inventors: Chih-Yen LO, Jenn-Shiang LAI
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Publication number: 20200135256Abstract: A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and a DAC in which the signal processing circuit is used are also provided. A recognition circuit includes a serial port to which a bit signal is input and 2N output ports recognizing an input N-bit word and corresponding uniquely to 2N bit combinations. Output ports of the recognition circuit are connected to 2N input ports of an electric circuit. With no signal input to the recognition circuit, all outputs are constantly in a Low level state. In a case where a bit signal is input to the serial port of the recognition circuit, only one of the output ports corresponding to the bit combinations turns to a High level state.Type: ApplicationFiled: April 19, 2018Publication date: April 30, 2020Inventors: Salaheldin Ahmed Ezzeldin Ibrahim Mohamed, Youhei Sakamaki, Shinsuke Nakano, Kota Shikama, Yuko Kawajiri
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Publication number: 20200135257Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.Type: ApplicationFiled: October 24, 2018Publication date: April 30, 2020Inventor: Kazutaka Miyano
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Publication number: 20200135258Abstract: A memory device include one or more sections of memory banks. Each of the one or more sections may include multiple sensing amplifiers and a digit line to supply voltages to the sensing amplifiers during a refresh of the respective section. The memory device may also include transmission circuitry configured to transmit excess charge remaining on a first digit line of a first section to a second digit line of a second section after a refresh of the first section and before a refresh of the second section.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventor: Scott E. Smith
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Publication number: 20200135259Abstract: An embodiment of an electronic apparatus may include a silicon substrate and a memory circuit coupled to the silicon substrate, the memory circuit including an array block of memory tiles coupled to the silicon substrate, a first set of global amplifiers coupled to the silicon substrate and the memory tiles and arranged along a first side of the array block, a first set of write drivers coupled to the silicon substrate and coupled to the memory tiles and arranged along the first side of the array block, a second set of global amplifiers coupled to the silicon substrate and coupled to the memory tiles and arranged along a second side of the array block opposite to the first side of the array block, and a second set of write drivers coupled to the silicon substrate and coupled to the memory tiles and arranged along the second side of the array block. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Applicant: Intel CorporationInventor: Shigeki Tomishima
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Publication number: 20200135260Abstract: Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Inventor: Harish N. Venkata
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Publication number: 20200135261Abstract: According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device.Type: ApplicationFiled: March 6, 2017Publication date: April 30, 2020Inventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
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Publication number: 20200135262Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.Type: ApplicationFiled: October 29, 2019Publication date: April 30, 2020Inventor: Frederick A. Ware
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Publication number: 20200135263Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Jason M. Brown, Daniel B. Penney
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Publication number: 20200135264Abstract: A temporal attribute of user data stored in a memory component is identified. It is determined that the identified temporal attribute satisfies a time condition. An indication is provided whether a refresh operation of the user data improves performance of the memory component. A user input is received indicating to perform the refresh operation of the memory component. The refresh operation of the memory component is performed.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventor: Michael T. Brady
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Publication number: 20200135265Abstract: A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takahiko Ishizu, Hikaru Tamura
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Publication number: 20200135266Abstract: A loaded capacitance static random-access memory (C-SRAM) is provided. The C-SRAM is configured to prevent full bit line discharge during a functional reads even where the number of bit cells on the bit lines is small. The C-SRAM includes one or more loaded capacitance structures that may take any of a variety of physical configurations designed to provide additional capacitance to the bit lines. For instance, the loaded capacitance structures may take the form of a MIM capacitor in which a ferroelectric layer is formed from one or more high K materials. In addition, the loaded capacitance structures may be positioned in a variety of locations within the C-SRAM, including the back end of line.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Applicant: INTEL CORPORATIONInventors: Raghavan Kumar, Sasikanth Manipatruni, Gregory Chen, Huseyin Ekin Sumbul, Phil Knag, Ram Krishnamurthy, Ian Young, Mark Bohr, Amrita Mathuriya
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Publication number: 20200135267Abstract: An Orthogonal Dual Port Ram (ORAM) memory cell may be provided. The ORAM memory cell may comprise a data storage element, a first port bit line, and a second port bit line that may be substantially perpendicular to first port bit line. The ORAM memory cell may further comprise a first word line that may be substantially perpendicular to first port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the first port bit line when the first word line is enabled. The ORAM memory cell may further comprise a second word line being substantially perpendicular to the second port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the second port bit line when the second word line is enabled.Type: ApplicationFiled: September 26, 2019Publication date: April 30, 2020Inventor: Cormac Michael O'Connell