Patents Issued in June 2, 2020
  • Patent number: 10671392
    Abstract: Systems, apparatuses, and methods for performing delta decoding on packed data elements of a source and storing the results in packed data elements of a destination using a single packed delta decode instruction are described. A processor may include a decoder to decode an instruction, and execution unit to execute the decoded instruction to calculate for each packed data element position of a source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of a destination operand, and for each calculated value, store the value into a corresponding packed data element position of the destination operand.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 2, 2020
    Assignee: INTEL CORPORATION
    Inventors: Elmoustapha Ould-Ahmed-Vall, Thomas Willhalm, Tracy Garrett Drysdale
  • Patent number: 10671393
    Abstract: A technique includes determining whether one or more instructions in an instruction group require cracking. Whether the instructions that require cracking are associated with a decode-time instruction optimization (DTIO) sequence is also determined. In response to a first instruction, included in the one or more instructions, requiring cracking and the first instruction not being part of a DTIO sequence, the first instruction is cracked into internal operations (IOPs). In response to a second instruction, included in the one or more instructions, requiring cracking and the second instruction being part of a DTIO sequence, an IOP sequence (that includes at least one IOP that is associated with at least a cracked version of the second instruction and at least a third instruction that is included in the one or more instructions and at least one other IOP that is associated with the cracked version of the second instruction) is generated.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10671394
    Abstract: A computer system for prefetching data in a multithreading environment includes a processor having a prefetching engine and a stride detector. The processor is configured to perform requesting data associated with a first thread of a plurality of threads, and prefetching requested data by the prefetching engine, where prefetching includes allocating a prefetch stream in response to an occurrence of a cache miss. The processor performs detecting each cache miss, and based on detecting the cache miss, monitoring the prefetching engine to detect subsequent cache misses and to detect one or more events related to allocations performed by the prefetching engine. The processor further performs, based on the stride detector detecting a selected number of events, directing the stride detector to switch from the first thread to a second thread by ignoring stride-1 allocations for the first thread and evaluating stride-1 allocations for potential strided accesses on the second thread.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivek Britto, George W. Rohrbaugh, III, Mohit Karve, Brian Thompto
  • Patent number: 10671395
    Abstract: The invention provides an application specific instruction set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for simultaneously executing a plurality of operations. For simultaneously executing the plurality of operations, the ASIP processor comprises a fetching unit to fetch a long instruction word from an instruction memory unit and an instruction decoder unit that interfaces with the fetching unit and a program address counter. The instruction decoder unit decodes the long instruction word fetched from the instruction memory unit and enables a plurality of sub blocks responsible for execution of a plurality of simultaneous independent operations. The instruction decoder unit of the ASIP is capable of decoding a 32-bit instruction word and executing up to six simultaneous independent operations.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 2, 2020
    Assignee: The King Abdulaziz City for Science and Technology—KACST
    Inventors: Mohammed S BenSaleh, Abdulfattah M Obeid, Yousef A Alzahrani, Ahmed F Shalash, Hossam A Fahmy, Hossam A Sayed, Mohamed A Aly
  • Patent number: 10671396
    Abstract: A method for operating a processing unit, including a memory and at least one processor core that executes a plurality of program functions of a computer program, includes ascertaining all program instructions that belong to a program function to be executed at a future execution point in time and providing the ascertained program instructions in the memory before the execution point in time.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 2, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Jens Gladigau, Dirk Ziegenbein
  • Patent number: 10671397
    Abstract: A method and associated computer program product are disclosed for generating an executable file from an object file, the object file being associated with an architecture having a predefined calling convention designating one or more call-clobbered registers. The method comprises identifying, from a first annotation included in the object file with a function call instruction, at least one restore instruction that follows the function call instruction, the function call instruction associated with a predefined function of the object file. The at least one restore instruction corresponds to at least one of the one or more call-clobbered registers. The method further comprises determining, based on at least a first list of registers that are referenced by the predefined function, the first list being included in the object file, whether to eliminate the at least one restore instruction.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Ulrich Weigand
  • Patent number: 10671398
    Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
  • Patent number: 10671399
    Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
  • Patent number: 10671400
    Abstract: A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions; in response to executing an instruction to commit inserted into the plurality of instructions units, incrementally commit a portion of the one or more memory modification instructions that have been atomically executed so far; and subsequent to incrementally committing the portion of the memory modification instructions that have been atomically executed so far, continue atomic execution of the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 2, 2020
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf, Cliff N. Click, Jr.
  • Patent number: 10671401
    Abstract: An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into a plurality of operators and (iii) schedule the operators in one or more data paths based on a readiness of the operators to be processed. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 2, 2020
    Assignee: Ambarella International LP
    Inventors: Leslie D. Kohn, Robert C. Kunz
  • Patent number: 10671402
    Abstract: A method for notifying a subset of users of a messaging channel may include publishing one or more shadow channels for the messaging channel. Each shadow channel is configured to prevent transmission of an event notification to one or more unregistered user devices. The method may also include broadcasting one or more event notifications to one or more registered user devices when an event associated with the one or more shadow channels is triggered. The one or more registered user devices are subscribers to the one or more shadow channels.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: June 2, 2020
    Inventors: Navneet Kumar, Shahabudeen Sajith, Vikram Chaitanya, Nisha Oarath
  • Patent number: 10671403
    Abstract: A method for identifying a hardware device in an operating system and a computer apparatus are provided. The method includes determining a unique index identifier of a hardware device, and establishing a mapping relationship between the unique index identifier and a device number of the hardware device. The method also includes obtaining the unique index identifier of the hardware device, in response to a status change of a hardware interface. Further, the method includes according to the mapping relationship, obtaining and allocating the device number to the hardware device to enable an access to the hardware device according to the device number of the hardware device.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 2, 2020
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventors: Haiyang He, Siyuan Wang, Aili Yao
  • Patent number: 10671404
    Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri
  • Patent number: 10671405
    Abstract: A monitoring system receives information from agents that monitors (e.g., unprivileged) containers, or applications in containers, executing across hosts to generate aggregated state information on a per-host basis. The system receives state information for each container, boot identifiers associated with the hosts of the container, and container identifiers. State information includes data describing the state of a container, or an application executing in the container. The boot identifier includes an identifier for a boot session of the host. The container identifier uniquely identifies each container. The monitoring system compares boot identifiers to determine containers that are co-located. If containers share a boot identifier, the monitoring system determines that the containers are co-located on the host that generated the boot identifier.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 2, 2020
    Assignee: New Relic, Inc.
    Inventors: Sean P. Kane, Peter Vinh, Erika Arnold
  • Patent number: 10671406
    Abstract: A server for automatically determining whether to enable a remote control function and a method for automatically enabling the remote control function are provided. The method for automatically enabling the remote control function includes: executing, by a board management controller (BMC), a firmware program to determine a logic level of a general-purpose input/output (GPIO) pin of the BMC; enabling, by the BMC, a remote control function according to a first logic level of the GPIO pin; and skipping enabling, by the BMC, the remote control function according to a second logic level of the GPIO pin.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 2, 2020
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventor: Chia-An Huang
  • Patent number: 10671407
    Abstract: Suspending and resuming a card runtime environment for a card computing device are disclosed. A card computing device obtains a suspension request. The suspension request includes a proposed value for a minimum suspension interval and/or a proposed value for a maximum suspension interval. The suspension request is accepted or rejected, by the card computing device, based on the proposed value for the minimum suspension interval and/or the proposed value for the maximum suspension interval. The card computing device may negotiate a different value for the maximum suspension interval. Additionally, a card computing device obtains a resumption request. The resumption request includes a resume token. The card computing device determines whether the resume token in the resumption request is valid. The card computing device determines whether the suspension interval is valid. The card computing device resumes the state that was associated with the card computing device at the time of suspension.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Oracle International Corporation
    Inventors: Sebastian Jürgen Hans, Vlad Victor Petrovici, Andrei Gabriel Serban
  • Patent number: 10671408
    Abstract: Automatic storage system configuration for mediation services that includes: determining that a particular storage system of the storage systems is not configured to request mediation from a mediation target for mediation between storage systems synchronously replicating a dataset; requesting, by the particular storage system from a configuration service, configuration information indicating one or more service handles for a mediation service; and configuring, in dependence upon the one or more service handles received from the configuration service, a mediation handler to communicate with the mediation service responsive to detecting a communication fault with one of the storage systems.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 2, 2020
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Thomas Gill, David Grunwald, Ronald Karr, Aditya Sethuraman, Kunal Trivedi, Eric Tung
  • Patent number: 10671409
    Abstract: A method, system, and program product for generating and processing application settings for a software application using an application configuration component operating on a computer system. An application settings object containing a plurality of application settings is generated for the software application. The application settings object are serialized and stored into an Extensible Markup Language (XML) application settings file on the computer system. A new instance of the application configuration component is generated. A request is received from the software application for an application settings object for a specific environment and module. If located on the computer system, the XML application settings file is deserialized into the application settings object. Each property of the application settings object is then processed and the application settings object is returned to the software application.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 2, 2020
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Gregory R. Floyd, Nathan R. Jones
  • Patent number: 10671410
    Abstract: Techniques for generating plug-in application recipe (PIAR) extensions are disclosed. A PIAR management application discovers a particular data type within one or more data values for a particular field of a plug-in application, where the particular data type is (a) different from a data type of the particular field as reported by the plug-in application and (b) narrower than the data type of the particular field while complying with the data type of the particular field. The PIAR management application identifies one or more mappings between (a) the particular data type and (b) one or more data types for fields accepted by actions of plug-in applications. The PIAR management application presents a user interface including one or more candidate PIAR extensions based on the mapping(s). Based on a user selection of a candidate PAIR extension, the PIAR management application executes a PIAR that includes the selected PIAR extension.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 2, 2020
    Assignee: Oracle International Corporation
    Inventors: Eric L. Sutton, Tuck Chang
  • Patent number: 10671411
    Abstract: Provided are systems and methods for generating a copy of an object in an object-oriented programming architecture. In one example, the method may include one or more of receiving a command to copy a model object comprising a hierarchical object-oriented architecture that references one or more underlying data objects, freezing a state of the one or more underlying data objects to generate a frozen data store of underlying object data, generating a first proxy object that references the frozen data store and a second proxy object that references the frozen data store, modifying the model object to reference the first proxy object instead of referencing the one or more underlying data objects, and generating a copy of the model object that references the second proxy object and storing the copy of the model object.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 2, 2020
    Assignee: SAP SE
    Inventor: Marco Pesarese
  • Patent number: 10671412
    Abstract: A programmable device including a memory and at least one processor coupled to the memory is provided. The memory stores a plurality hybrid objects. Each hybrid object of the plurality of hybrid objects includes a native object wrapped by an interpreted object. The at least one processor can be coupled to the memory. The at least one processor can be configured to identify a message to execute an operation on one or more hybrid objects of the plurality of hybrid objects; clone, in response to reception of the message, each native object within the one or more hybrid objects to create one or more cloned native objects; wrap each cloned native object of the one or more native objects with a new interpreted object to create one or more new hybrid objects; and execute the operation on the one or more new hybrid objects.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 2, 2020
    Assignee: Adobe Inc.
    Inventors: Stavila Radu-Bogdan, Grecescu Ioan Vladimir
  • Patent number: 10671413
    Abstract: In one embodiment, a method includes identifying a content object for display based at least in part on one or more filtering criteria. The filtering criteria is a measure of suitability of each content object for presentation based at least in part on social-graph information between a first user and one or more second users or a current geo-location of the first user. The method also includes applying the filtering criteria to the content object; and providing for display on a user interface (UI) the content object based on whether the content object is suitable for presentation based at least in part on the filtering criteria.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Facebook, Inc.
    Inventor: Luke St. Clair
  • Patent number: 10671414
    Abstract: Disclosed is a Cross Domain Desktop Compositor (CDDC) that allows separate graphical user interfaces (GUIs) from independent computing domains to be combined and accessed from a single physical use interface. The CDDC provides a unified desktop experience, whilst preventing data leakage between isolated domains, compositing application windows from each separate GUI and providing natural keyboard and mouse interaction with every displayed window.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: June 2, 2020
    Assignee: THE COMMONWEALTH OF AUSTRALIA
    Inventor: Mark Robert Beaumont
  • Patent number: 10671415
    Abstract: Non-limiting examples of the present disclosure relate to generation and surfacing of user-specific contextual insights from analysis of telemetry data that is associated with user interaction with an exemplary application/service. Processing operations described herein extend to generation of any type of contextual insights from any type of telemetry data. In one example, user-specific contextual insights are generated to provide users with writing assistance to digital documents created through exemplary applications/services. A user interface is presented through a productivity service. Writing assistance telemetry data, associated with one or more users, is analyzed. Writing assistance telemetry data comprises, data evaluating, for the user(s), spelling, grammar and a writing style across content of one or more digital documents. User-specific insight analytics are generated for the user(s) based on analysis of the writing telemetry data.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 2, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Anand Balachandran
  • Patent number: 10671416
    Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 2, 2020
    Assignee: INTEL CORPORATION
    Inventors: Mahesh S. Natu, Shamanna M. Datta
  • Patent number: 10671417
    Abstract: An optimizer controller controls a hypervisor optimizer to regulate operation of the optimizer to insure the optimizer does not negatively impact operation of software applications. The optimizer controller monitors applications and application performance to determine whether to turn on or off specific optimization features for specific applications. The optimizer may also notify a user of potential problems. The optimizer controller may utilize optimization rules for specific applications that set the conditions for controlling the optimizer. The rules may be dynamically changed based on observed performance and trends of the applications.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lisa Dierkhising, Lee N. Helgeson, Justin K. King, Michelle A. Schlicht
  • Patent number: 10671418
    Abstract: A server computer system identifies a set of image templates for building a cloud server image and a compatible deployable template for launching the cloud server image in a template repository. The server computer system associates the set of image templates with the compatible deployable template in the template repository. Upon receiving a user selection, the server computer system obtains the set of image templates and the compatible deployable temple.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: June 2, 2020
    Assignee: Red Hat, Inc.
    Inventors: Dan Macpherson, Scott Wayne Seago
  • Patent number: 10671419
    Abstract: A system and method of emulated input-output memory management units includes a management software associating a first device with a first input-output memory management unit having a first security designation, and associating a second device with a second input-output memory management unit having a second security designation different from the first security designation. A hypervisor constructs a table that describes associations between the plurality of devices and the plurality of input-output memory management units. The hypervisor provides the table to a guest virtual machine having a plurality of guest addresses including a first guest address and a second guest address. The first device accesses the first guest address through the first input-output memory management unit and the second device accesses the second guest address through the second input-output memory management unit.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 2, 2020
    Assignee: Red Hat Israel, Ltd.
    Inventors: Marcel Apfelbaum, Gal Hammer
  • Patent number: 10671420
    Abstract: A Virtual Network Function Descriptor (VNFD) parameter may include subfields that allow a management entity to determine whether the VNFD parameter can be updated. The subfields may include a write-ability subfield that indicates whether the VNFD parameter is a dynamic/configurable VNFD parameter or a fixed/static VNFD parameter. The VNFD parameter may also include an access permission subfield that indicates which entities are authorized to modify/update the VNFD parameter. The VNFD parameter may also include an administrative priority subfield that indicates a priority of an entity that set an attribute of the VNFD parameter. The VNFD parameter may also include a constraints subfield that indicates one or more conditions that are required to occur in order for the VNFD parameter to be updated.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: June 2, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Haitao Xia, Zhixian Xiang, Xu Yang
  • Patent number: 10671421
    Abstract: A virtual machine start method and apparatus is presented, where the method includes determining N types of virtualized network function components (VNFCs) according to a first service; obtaining a distribution relationship between the N types of VNFCs and virtual machines, where the distribution relationship indicates a quantity of each type of VNFC distributed in each virtual machine; selecting at least one to-be-started virtual machine from unstarted virtual machines according to the distribution relationship, so that a total quantity of each type of VNFC included in a started virtual machine and the at least one to-be-started virtual machine meets a corresponding preset quantity; and starting the at least one to-be-started virtual machine. In the present disclosure, types and a quantity of VNFCs running on each virtual machine are first obtained.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 2, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lifu Chen, Dehan Li, Tizheng Wang
  • Patent number: 10671422
    Abstract: A security module in a memory access path of a processor of a processing system protects secure information by verifying the contents of memory pages as they transition between one or more virtual machines (VMs) executing at the processor and a hypervisor that provides an interface between the VMs and the processing system's hardware. The security module of the processor is employed to monitor memory pages as they transition between one or more VMs and a hypervisor so that memory pages that have been altered by a hypervisor or other VM cannot be returned to the VM from which they were transitioned.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 2, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David Kaplan, Jeremy W. Powell, Richard Relph
  • Patent number: 10671423
    Abstract: A network device may include various cards and modules, such as management modules, line cards, and switch fabric modules. In various implementations, these components can be “hot-plugged” meaning that the components can be inserted into and removed from the network device while the network device is powered on. In various implementations, hardware in the network device can identify when a component has been added. The hardware can notify a virtual machine, which can then notify the host operating system. The host operating system can added the component, and then notify the virtual machine to also add the component. Once the virtual machine has added the component, the component becomes available for use by processes executing on the virtual machine.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 2, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Changbai He, Samir Bhattacharya
  • Patent number: 10671424
    Abstract: Some embodiments provide a local network controller that manages a first managed forwarding element (MFE) operating to forward traffic on a host machine for several logical networks and configures the first MFE to forward traffic for a set of containers operating within a container virtual machine (VM) that connects to the first MFE. The local network controller receives, from a centralized network controller, logical network configuration information for a logical network to which the set of containers logically connect. The local network controller receives, from the container VM, a mapping of a tag value used by a second MFE operating on the container VM to a logical forwarding element of the logical network to which the set of containers connect. The local network controller configures the first MFE to apply the logical network configuration information to data messages received from the container VM that are tagged with the tag value.
    Type: Grant
    Filed: April 22, 2018
    Date of Patent: June 2, 2020
    Assignee: NICIRA, INC.
    Inventors: Somik Behera, Donghai Han, Jianjun Shen, Justin Pettit
  • Patent number: 10671425
    Abstract: A system and method for programming a timer in a virtualized system are disclosed. In accordance with one embodiment, a virtual machine executed by a processing device detects a need to request an interrupt at a first time and reads, from the first memory location, a second time that is associated with a next interrupt of the physical host machine scheduled by a hypervisor executed by the processing device. The virtual machine determines whether the first time is less than the second time. Responsive to the first time being less than the second time, the virtual machine transfers execution control to the hypervisor. Responsive to the first time not being less than the second time, the virtual machine stores the first time in a second memory location that is writeable by the virtual machine.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 2, 2020
    Assignee: Red Hat Israel, LTD.
    Inventor: Michael Tsirkin
  • Patent number: 10671426
    Abstract: Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: June 2, 2020
    Assignee: ARM Limited
    Inventors: Curtis Glenn Dunham, Jonathan Curtis Beard, Roxana Rusitoru
  • Patent number: 10671427
    Abstract: Snapshot Isolation (SI) is an established model in the database community, which permits write-read conflicts to pass and aborts transactions only on write-write conflicts. With the Write Skew Anomaly (WSA) correctly eliminated, SI can reduce the occurrence of aborts, save the work done by transactions, and greatly benefit long transactions involving complex data structures. Embodiments include a multi-versioned memory subsystem for hardware-based transactional memory (HTM) on the GPU, with a method for eliminating the WSA on the fly, and incorporates SI. The GPU HTM can provide reduced compute time for some compute tasks.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 2, 2020
    Assignee: BOARD OF SUPERVISORS OF LOUISIANA STATE UNIVERSITY AND AGRICULTURAL AND MECHANICAL COLLEGE
    Inventors: Lu Peng, Sui Chen
  • Patent number: 10671428
    Abstract: An exemplary method for using a virtual assistant may include, at an electronic device configured to transmit and receive data, receiving a user request for a service from a virtual assistant; determining at least one task to perform in response to the user request; estimating at least one performance characteristic for completion of the at least one task with the electronic device, based on at least one heuristic; based on the estimating, determining whether to execute the at least one task at the electronic device; in accordance with a determination to execute the at least one task at the electronic device, causing the execution of the at least one task at the electronic device; in accordance with a determination to execute the at least one task outside the electronic device: generating executable code for carrying out the least one task; and transmitting the executable code from the electronic device.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: June 2, 2020
    Assignee: Apple Inc.
    Inventor: Nicolas Zeitlin
  • Patent number: 10671429
    Abstract: An information processing apparatus includes: a reconfiguration device which can change a circuit configuration through a dynamic partial reconfiguration; and a controller which controls a circuit arrangement in the reconfiguration device, in which when a processing circuit related to a new task is arranged in the reconfiguration device, the controller determines a circuit assignment of a processing circuit related to an existing task in execution and the processing circuit related to the new task with respect to an area as a result of combining an area used for the processing circuit related to the existing task in execution and a space area, based on a predicted end time of the processing of the respective tasks, and arranges the processing circuits related to the respective tasks in the reconfiguration device in accordance with the determined circuit assignment.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 2, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kentaro Katayama
  • Patent number: 10671430
    Abstract: Techniques are disclosed relating to inter-process communication. In some embodiments, a kernel receives a notification of a communication to be sent from a first thread of a first application to a second thread of a second application. The kernel provides a reply port to the first thread for receiving a reply to the communication from the second thread. The kernel facilitates sending the communication from the first thread to the second thread. The kernel increases an execution priority of the second thread in response to the kernel determining that the reply port and a destination port associated with the second thread are identified in the communication. In some embodiments, the kernel creates the reply port in response to receiving the notification and, in response to detecting the reply has been communicated to the reply port, decreases the execution priority of the second thread and removes the reply port.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 2, 2020
    Assignee: Apple Inc.
    Inventors: Daniel A. Steffen, Jainam A. Shah, James M. Magee, Jeremy C. Andrus, Russell A. Blaine
  • Patent number: 10671431
    Abstract: Forecasting workload activity for data stored on a data storage device includes selecting at least one metric for measuring workload activity, providing at least one grouping of portions of the data according to a workload affinity determination provided for each of the portions at a subset of a plurality of time steps, where the workload affinity determination is based on each of the data portions in the group experiencing above-average workload activity during same ones of the subset of the plurality of time steps, the subset corresponding to at least one business cycle for accessing the data, and forecasting workload activity for all of the portions of data in the group based on forecasting workload activity for a subset of the data portions that is less than all of the data portions.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 2, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sean C. Dolan, Dana Naamad, Marik Marshak, Hui Wang, Xiaomei Liu
  • Patent number: 10671432
    Abstract: A method, system and computer program product for optimizing memory management. An analytics engine receives from a computing device an execution sequence that led to the detected execution of an operation to create a new process, which involves copying of the parent process. The analytics engine searches profiles stored in a repository for patterns of execution sequences that match the received execution sequence. Upon identifying a stored pattern with an execution sequence within a threshold degree of similarity as the received execution sequence, the analytics engine instructs the computing device to handle the operation to create the new process in a certain manner based on the contents of the profile containing the matching stored pattern. For example, the computing device may be instructed to preemptively fail the operation in response to the profile indicating that the execution of the operation resulted in an out of memory error.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel M. Hursh, Jonathan L. Kaus, David M. Koster, Jason A. Nikolai
  • Patent number: 10671433
    Abstract: This disclosure relates generally to systems and methods for load balancing, resource allocation, and job scheduling within a high-performance computing (HPC) environment. In one implementation, the system may include a processor configured to execute instructions and a memory storing the instructions. Furthermore, the instructions may include commands to receive at least one job from a user; receive at least one preference from a user; automatically generate, in a language compatible with the load balancer, at least one command based on the at least one job and the at least one preference; transmit the at least one job and the at least one command to the load balancer; and notify the user that the received at least one job and the received at least one preference have been transmitted to the load balancer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 2, 2020
    Assignee: Tata Consultancy Services Limited
    Inventors: Piyush Kumar Singh, Prasoon Sangwan
  • Patent number: 10671434
    Abstract: Data transformation offloading in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (‘GPU’) servers, including: storing, within the storage system, a dataset; identifying, in dependence upon one or more machine learning models to be executed on the GPU servers, one or more transformations to apply to the dataset; and generating, by the storage system in dependence upon the one or more transformations, a transformed dataset.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 2, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Brian Gold, Emily Watkins, Ivan Jibaja, Igor Ostrovsky, Roy Kim
  • Patent number: 10671435
    Abstract: Data transformation caching in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (‘GPU’) servers, including: identifying, in dependence upon one or more machine learning models to be executed on the GPU servers, one or more transformations to apply to a dataset; generating, in dependence upon the one or more transformations, a transformed dataset; storing, within one or more of the storage systems, the transformed dataset; receiving a plurality of requests to transmit the transformed dataset to one or more of the GPU servers; and responsive to each request, transmitting, from the one or more storage systems to the one or more GPU servers without re-performing the one or more transformations on the dataset, the transformed dataset.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 2, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Brian Gold, Emily Watkins, Ivan Jibaja, Igor Ostrovsky, Roy Kim
  • Patent number: 10671436
    Abstract: A method is provided for improving a hit ratio of a buffer cache in a system in which vertices of a DAG have tasks that generate intermediate data stored in the buffer cache. The method tracks (i) a buffer cache usage by vertices that have finished running and (ii) a current available buffer cache space. Responsive to a new task being runnable and having dependent parent vertices, the method estimates a total buffer cache usage of current running vertices based on a partial result of the current running vertices. Responsive to the estimate exceeding current available buffer cache space, the method (i) selects a vertex having a most amount of intermediate data stored in the buffer cache for its dependent parent vertices, and (ii) increases a priority of the tasks in the selected vertex to obtain prioritized tasks. The method executes the prioritized tasks earlier than other remaining runnable tasks.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tatsuhiro Chiba, Takeshi Yoshimura
  • Patent number: 10671437
    Abstract: A method for controlling application and related devices are provided. The method includes the follows. A CPU utilization of a system of a terminal device is obtained in response to a selection operation for a target application of the terminal device. When the CPU utilization of the system is greater than or equal to a preset utilization, a state of at least one of applications in the background is changed, so as to decrease the CPU utilization of the system. The target application is then launched.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 2, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Yuanqing Zeng
  • Patent number: 10671438
    Abstract: A plurality of processing entities of a processor complex is maintained, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory. One of the plurality of processing entities is allocated for execution of a critical task. In response to the allocating of one of the plurality of processing entities for the execution of the critical task, other processing entities of the plurality of processing entities are folded. The critical task utilizes the local cache of the other processing entities that are folded, the shared memory, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 10671439
    Abstract: Workload planning with quality-of-service (‘QoS’) integration, including: determining, for each of a plurality of entities, one or more QoS thresholds associated with the entity; determining, for each of the plurality of entities, one or more resource utilization levels associated with the entity; and determining, in dependence upon the one or more QoS thresholds associated with the plurality of entities, the one or more resource utilization levels associated with the plurality of entities, and one or more overprovisioning factors associated with the storage system, a risk factor that identifies the likelihood that one or more system resources will be overconsumed by the plurality of entities.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 2, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Yuval Frandzel, Ivan Iannaccone, Kiron Vijayasankar
  • Patent number: 10671440
    Abstract: A system for provisioning resources includes an input interface and a processor. The input interface is configured to receive a time series of past usage data. The past usage data comprises process usage data and instance usage data. The processor is configured to determine an upcoming usage data based at least in part on the time series of the past usage data, and provision a computing system according to the upcoming usage data.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 2, 2020
    Assignee: Workday, Inc.
    Inventors: Montiago Xavier LaBute, Teng Qu, James Michael Stratton
  • Patent number: 10671441
    Abstract: A communication system according to the present disclosure includes: a management apparatus (30) configured to manage positional information regarding a communication terminal (10); a server (50) configured to provide a communication service for the communication terminal (10), and a control apparatus (60) configured to control start or stop of a communication function included in a communication apparatus (40). The server (50) is arranged in the vicinity of a base station (20), the management apparatus (30) transmits the positional information regarding the communication terminal (10) to the control apparatus (60), the control apparatus (60) controls start or stop of the communication function that the communication apparatus (40) includes based on the positional information, and the control apparatus (60) notifies the communication terminal (10) of start or stop of the communication function that the communication apparatus (40) includes via the management apparatus (30).
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: June 2, 2020
    Assignee: NEC CORPORATION
    Inventors: Yoshinobu Ohta, Kazuhiro Egashira