Patents Issued in July 21, 2020
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Patent number: 10719402Abstract: Power loss in a client device is detected. In response to the detecting of the power loss, an electronic card is alerted that the power loss is about to occur, where the electronic card includes a volatile storage and a non-volatile storage. A transfer of data from the volatile storage to the non-volatile storage is triggered in response to the alert.Type: GrantFiled: August 5, 2019Date of Patent: July 21, 2020Assignee: Hewlett-Packard Development Company, L.P.Inventors: Byron A. Alcorn, Scott W. Briggs, Joel Pierre Lefebvre
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Patent number: 10719403Abstract: Recovery support techniques for storage virtualization environments are described. In one embodiment, for example, a method may be performed that comprises defining, by processing circuitry, a storage container comprising one or more logical storage volumes of a logical storage array of a storage system, associating the storage container with a virtual volume (vvol) datastore, identifying metadata for a vvol of the vvol datastore, and writing the metadata for the vvol to the storage system. Other embodiments are described and claimed.Type: GrantFiled: January 31, 2016Date of Patent: July 21, 2020Assignee: NetApp Inc.Inventors: Deepak Thomas, Dan Sarisky, Nagender Somavarapu, Santosh Lolayekar
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Patent number: 10719404Abstract: Techniques to back up data are disclosed. In various embodiments, a shadow copy of a source volume is created. An excluded file is deleted from the shadow copy. One or more blocks modified in the shadow copy in connection with deleting the excluded file from the shadow copy are tracked.Type: GrantFiled: October 20, 2017Date of Patent: July 21, 2020Assignee: EMC IP Holding Company LLCInventors: Kiran Kumar Madiraju Varadaraju, Neelabh Mam
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Patent number: 10719405Abstract: Methods and systems for efficiently capturing snapshots of a computing application or environment over time and transferring the snapshots to an integrated data management and storage system are described. A snapshot agent may detect that one or more electronic files associated with the computing application or environment are greater than a threshold file size and in response perform an incremental backup optimization in which the snapshot agent may identify files that have been touched since a previous snapshot by accessing file system metadata (e.g., last modified timestamps) or utilizing a tracking agent to detect potential file changes that have occurred since the previous snapshot was captured. The snapshot agent may then generate fingerprints for data blocks of the touched files, which may reduce the total number of fingerprints needing to be generated to identify the changed data blocks corresponding with a current snapshot to be transferred.Type: GrantFiled: December 11, 2017Date of Patent: July 21, 2020Assignee: RUBRIK, INC.Inventors: Jiangbin Luo, Biswaroop Palit, Guilherme Vale Ferreira Menezes
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Patent number: 10719406Abstract: One embodiment provides a computer implemented method of data identification within a deduplication storage system, the method comprising processing multiple units of a segment of data within the deduplication storage system using a fingerprint generation algorithm; storing the internal state generated while processing the multiple units of the segment of data; generating a first fingerprint for the segment of data based on the internal state; reloading the internal state after generating the first fingerprint for the segment of data; and generating a second fingerprint for the segment of data based on a transformed unit of the segment of data.Type: GrantFiled: June 23, 2016Date of Patent: July 21, 2020Assignee: EMC IP HOLDING COMPANY LLCInventors: Kedar Shrikrishna Patwardhan, Mangesh Sudhir Nijasure, Veeral Shah
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Patent number: 10719407Abstract: Backing up availability group databases configured on multi-node virtual servers is described. A system identifies an availability group scheduled for backup. The system determines whether the availability group is configured on at least one virtual server in a cluster of nodes associated with the availability group. If the availability group is configured on at least one virtual server in the cluster of nodes, the system retrieves information from a server in the cluster of nodes. The system uses the retrieved information to identify a database replica that is preferred for backing up the availability group. The system identifies a virtual server, in the cluster of nodes, that is associated with the identified database replica. The system identifies a node for backing up the availability group by identifying an active node from the nodes in the identified virtual server. The system backs up the availability group via the identified node.Type: GrantFiled: June 5, 2017Date of Patent: July 21, 2020Assignee: EMC IP HOLDING COMPANY LLCInventors: Elango Chockalingam, Gajendran Raghunathan, Yashomathi Krishnamurthy, Arathi Bhandari
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Patent number: 10719408Abstract: Cloud-based storage services are provided for storing and/or sharing content across multiple devices, where the content is periodically synchronized between the devices and the storage service. Conventionally, if locally stored content is deleted from a device, the delete would be propagated to the storage service causing the content to not only be deleted from the storage service but from any other devices where the content was locally stored and synchronized with the storage service. Embodiments are directed to retainment of locally deleted content at the storage service to prevent accidental or nefarious deletions of locally stored content on a device from further causing the content to be deleted universally from the storage service and/or multiple other devices. For example, the storage service may be configured to receive content stored locally on the device, detect a deletion of the content on the device, and retain the content at the storage service.Type: GrantFiled: August 3, 2016Date of Patent: July 21, 2020Assignee: Microsoft Technology Licensing, LLCInventors: John Rodrigues, Steven Bailey, Adam Czeisler
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Patent number: 10719409Abstract: Cloud-based storage services are provided for storing and/or sharing content across multiple devices, where the content is periodically synchronized between the devices and the storage service. Embodiments are directed to retainment of locally deleted content at the storage service to prevent accidental or nefarious deletions of locally stored content on a device from being propagated to the storage service. For example, a selectable feature to retain locally deleted content, at the storage service may be presented through a display of a client device. A deletion of the content from the client device may be detected. The retained content may be prevented from being downloaded and stored locally on the client device when content at the storage service and the client device are synchronized if the feature was selected. If the feature was not selected, deletion options for the content may be presented through the display.Type: GrantFiled: August 18, 2016Date of Patent: July 21, 2020Assignee: Microsoft Technology Licensing, LLCInventors: John D. Rodrigues, Adam Czeisler, Steven Bailey
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Patent number: 10719410Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate distributed data backup. An example apparatus includes a controller to detect a trigger event for a distributed backup mode; and, in response to detection of the trigger event, trigger the distributed backup mode. When in the distributed backup mode, the controller of the example apparatus is to identify one or more receiving devices within communication range of the apparatus available to receive a data backup from the apparatus. The example apparatus includes a data distributor to distribute data from the apparatus among the one or more receiving devices. The controller of the example apparatus is to confirm receipt of the distributed data by the one or more receiving devices.Type: GrantFiled: June 21, 2018Date of Patent: July 21, 2020Assignee: Intel CorporationInventor: Mateusz Bronk
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Patent number: 10719411Abstract: A method of performing error recovery of encrypted data frames is disclosed. A data packet is received, and a decryption operation is performed on the data packet. The data packet is compared with one or more data packets stored in a recovery buffer to identify a duplicate of the data packet when the decryption operation fails. One or more bits affected by one or more bit errors are identified based on a comparison between the data packet and the duplicate of the data packet. Different combinations of bit values for the one or more bits are determined. The decryption operation is performed on the data packet with the different combinations to identify a correct combination of bit values for the one or more bits. The data packet is recovered (e.g., corrected so that it can be decrypted and consumed) based on the correct combination of bit values.Type: GrantFiled: April 1, 2019Date of Patent: July 21, 2020Assignee: Rockwell Collins, Inc.Inventors: TJ T. Kwon, Robert W. Hartney, Dayton G. Smith
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Patent number: 10719412Abstract: An image forming apparatus capable of automatically rolling back the system to an appropriate state. The image forming apparatus updates system data set therein. History information of the system data is managed, and execution of rollback processing for replacing the system data by system data which was set before the system data is controlled based on the history information of the system data.Type: GrantFiled: March 8, 2018Date of Patent: July 21, 2020Assignee: CANON KABUSHIKI KAISHAInventor: Takumi Michishita
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Patent number: 10719413Abstract: A unified backup workflow process for different hypervisor configurations of virtual machines on different storage of a cluster leverages RCT-based backup functionality so that backup operations can be performed by a single host of the cluster. The process enables backing up together virtual machines that are local, as well as part of CSV or SMB storage using virtual machine level snapshots as checkpoints rather than volume level snapshots that were traditionally used. Backup data is sent to a backup server as a data stream rather than a file, which avoids the necessity of maintaining chains or structures that identify parent-child disks on the server.Type: GrantFiled: April 17, 2018Date of Patent: July 21, 2020Assignee: EMC IP Holding Company, LLCInventors: Sunil Yadav, Aaditya R. Bansal, Soumen Acharya, Suman C. Tokuri, Sudha V. Hebsur
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Patent number: 10719414Abstract: In one embodiment, a sequence of microservice steps may be performed according to a programmed microservice workflow, while determining which executed tasks within the performed sequence of microservice steps have an individually corresponding rollback defined within the particular task. As such, a rollback path is stored corresponding to reversing the sequence of those executed tasks having an individually corresponding rollback, and, for each executed task having an individually corresponding rollback, a current status of the microservice workflow is also stored as a respective rollback status within the rollback path.Type: GrantFiled: May 11, 2018Date of Patent: July 21, 2020Assignee: Cisco Technology, Inc.Inventor: Fabio Giannetti
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Patent number: 10719415Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.Type: GrantFiled: December 7, 2018Date of Patent: July 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Christian Jacobi, Timothy J. Slegel
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Patent number: 10719416Abstract: A method/device for recognizing a microprocessor hardware error, including comparing a first application's first result, running on a first microprocessor, with a second application's second result, running on the first/second microprocessor, with a microcontroller, providing comparison strategies, the hardware error being recognized as a function of the comparison, the microcontroller receiving a first message from the first microprocessor, and receiving a second message from the first microprocessor if the second application runs on the first microprocessor, or receives a first message from the second microprocessor if the second application runs thereon, the first message containing first comparison strategy information and first result information of a first function calculation, the second message containing second comparison strategy information and second result information of a second function calculation, the first and second strategy information being compared, the first and second result informatioType: GrantFiled: May 17, 2018Date of Patent: July 21, 2020Assignee: Robert Bosch GmbHInventors: Gunnar Piel, Peter Munk
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Patent number: 10719417Abstract: A hierarchical multi-level heterogeneous cluster data system having processing nodes at each of a plurality of cluster levels configured for different data tiers having different availability, accessibility and protection requirements. Each cluster level comprises groups of processing nodes arranged into a plurality of failover domains of interconnected nodes that exchange heartbeat signals to indicate that the nodes are alive and functioning. A master node of each failover domain is connected to a master node of a parent failover domain for exchanging heartbeat signals to detect failures of nodes at lower cluster levels. Upon a network partition, the nodes of the failover domain may be merged into another failover domain at the same or a higher cluster level to continue providing data services. The cluster has a global namespace across all cluster levels, so that nodes that are moved to different failover domains can be accessed using the same pathname.Type: GrantFiled: January 30, 2018Date of Patent: July 21, 2020Assignee: EMC IP Holding Company, LLCInventors: Peng Wu, Yong Zou
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Patent number: 10719418Abstract: Embodiments for disaster recovery in a disaggregated computing system. A memory is allocated at a secondary, disaster recovery site for data received from a primary site. A degree of resiliency is defined for respective workloads associated with the data at the primary site to specify how critical each respective workload is to execute in case of disaster, and the data is replicated to the allocated memory at the disaster recovery site according to the degree of resiliency.Type: GrantFiled: May 31, 2018Date of Patent: July 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Valentina Salapura, John A. Bivens, Min Li, Ruchi Mahindru, Eugen Schenfeld
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Patent number: 10719419Abstract: One or more techniques and/or computing devices are provided for communicating storage controller failures utilizing service processor traps. A first storage controller, of a first storage cluster, has a disaster recovery relationship with a second storage controller of a second storage cluster. The first storage controller comprise a first service processor configured to monitor health of the first storage controller. Responsive to identifying a failure of the first storage controller, the first service processor uses stored communication configuration of a second service processor of the second storage controller to send a service processor trap to the second service processor. In this way, the second service processor initiates a switchover operation by the second storage controller to provide clients with failover access to data previously available through the first storage controller before the failure.Type: GrantFiled: May 24, 2018Date of Patent: July 21, 2020Assignee: NetApp Inc.Inventors: Hrishikesh Keremane, Vijay Singh, David Andrew Allender
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Patent number: 10719420Abstract: A testing facility is provided to test the multithreading functionality of a computing environment. The testing of this functionality includes building independent instruction streams to test threads of a multi-threaded environment while honoring architecturally imposed common fields and constraints, if any, of the threads. Certain features may be enabled/disabled for all threads. The instruction streams generated for testing this functionality may vary from being identical for all the threads being tested to being totally different, such as having different architectures.Type: GrantFiled: February 10, 2015Date of Patent: July 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Y Duale, Shailesh R. Gami, Dennis Wittig
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Patent number: 10719421Abstract: An example method for monitoring different data storage devices across a network includes receiving data storage access requests made to different data storage devices across a network. A subset of the access requests to a taxon of a taxonomy of access request characteristics. For the taxon, a taxon threshold is determined for a parameter based upon the subset of access requests. The parameter of a sample of observed access requests, made to a data storage device and belonging to the taxon, is compared to the taxon threshold. A notification regarding the data storage device is made based upon the comparison.Type: GrantFiled: October 23, 2015Date of Patent: July 21, 2020Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christoph J Graham, Thomas J Flynn, Virginia Q Herrera
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Patent number: 10719422Abstract: A system performance monitor displays the performance of a system that carries out one or more tasks. The monitor has a front end including an input and output device, a back end, and one or more subsystem schema databases for storing data about said tasks. The system that carries out the tasks has subsystem schemas that have members that carry out the tasks. The records of each database are indexed by the members of the corresponding subsystem schemas. When a user selects a member of a subsystem schema, the back end retrieves the records from the database using the member index. After the records are retrieved, they are formatted to be graphically displayed on the output device. The graphical display may be a time-cloud scatter plot where each data point is located according to the start time and end time of a particular task in the retrieved records.Type: GrantFiled: April 23, 2019Date of Patent: July 21, 2020Assignee: Markets, Patents & Alliances LLCInventor: Mark S. Nowotarski
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Patent number: 10719423Abstract: An apparatus and associated method are provided for application deployment assessment. In use, a plurality of deployment parameters associated with one or more applications, and a workload profile are received. Further, an application deployment specification is generated, based on the workload profile and the deployment parameters. Still yet, a type of one or more orchestrators on one or more systems is identified. The application deployment specification is processed, based on the identified type of the one or more orchestrators on the one or more systems. Further, the one or more processors execute the instructions to deploy, via an application program interface (API), the one or more applications to the one or more orchestrators on at least one of the one or more systems, and at least one workload generator to at least one of the one or more systems, utilizing the processed application deployment specification. Operational data is collected from one or more monitoring agents on the one or more systems.Type: GrantFiled: July 12, 2017Date of Patent: July 21, 2020Assignee: Futurewei Technologies, Inc.Inventors: Xiaoyun Zhu, Jinzhong Zhang, Huichao Zhao, Sid Askary, Daniel Chen, CJ Hersh, Yue Chen, Shu Zhang, Jing Ye
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Patent number: 10719424Abstract: A method for performing a static analysis may include extracting, from a caller function in code, a context-free inter-procedural rule including a callsite and a return value of a callee function. The callsite may invoke the callee function. The method may further include extracting, from the caller function, a context-sensitive parameter mapping rule that maps an input parameter of the callee function to an invocation value provided by the caller function at the callsite, deriving a derived value for the callsite using the context-free inter-procedural rule and the context-sensitive parameter mapping rule, and identifying a defect in the code by performing the static analysis using the derived value for the callsite.Type: GrantFiled: March 18, 2019Date of Patent: July 21, 2020Assignee: Oracle International CorporationInventors: Padmanabhan Krishnan, Raghavendra Kagalavadi Ramesh, Yang Zhao
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Patent number: 10719425Abstract: A method may include generating, for a concurrent application, an execution trace that includes operations, extracting actor pairs from the execution trace, assigning each of the operations to an actor pair, and generating vector clocks for the operations. Each vector clock may include a clock value for each of the actor pairs.Type: GrantFiled: June 13, 2018Date of Patent: July 21, 2020Assignee: Oracle International CorporationInventors: Nicholas John Allen, Yang Zhao, Cristina Nicole Cifuentes, Nathan Robert Albert Keynes
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Patent number: 10719426Abstract: A system and method for utilizing metadata of a client computer in form of transactions and/or software operations (e.g., actions) in an enterprise system hosted by a host entity, such as in a cloud environment for testing the software operations is disclosed. The host entity stores metadata (e.g., response time, delay, processing time, usage) about the transactions in a database for the client computer system's actions. The host entity then uses the stored metadata to automatically generate a test script based on actual user interactions with the software operations of the enterprise resource planning system for specific data range and environment in order to test functionality of a plurality of software operations in the enterprise resource planning systems being operated by users of the client computers.Type: GrantFiled: March 29, 2018Date of Patent: July 21, 2020Assignee: Velocity Technology Solutions, Inc.Inventors: Travis Tuttle, John Waite, Ping-Haur Jen, Pritesh Gaikwad, Chen-Feng Yang
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Patent number: 10719427Abstract: A contributed test management system receives a first request from a consumer system, where the first request comprises a request for a contributed test to be added to a deployment pipeline of a producer system, and where the contributed test is associated with an application component in the deployment pipeline. The contributed test management system causes the contributed test to test a code update provided by the producer system for the application component in the deployment pipeline, detects whether the first test fails during execution, and, if so indicates to the consumer system that the first test has failed.Type: GrantFiled: May 4, 2017Date of Patent: July 21, 2020Assignee: Amazon Technologies, Inc.Inventors: Carlos Alejandro Arguelles, Simon Kurt Johnston, Wes McDaniel, David Panko, Darrin Prutsman, Harpreet Singh
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Patent number: 10719428Abstract: A user interface automation framework is described. A system records multiple user interface screenshots during a session of a user interacting with a user interface application executing on a host computer. The system records metadata associated with the host computer during the session. The system executes a test of the user interface application based on the multiple user interface screenshots and the metadata.Type: GrantFiled: July 20, 2016Date of Patent: July 21, 2020Assignee: salesforce.com, inc.Inventor: Vikas Taneja
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Patent number: 10719429Abstract: A system and method for dynamic load testing on a target application are provided. The method includes, receiving a request for varying load on a target application in running load-testing environment. The running load-testing environment has a plurality of threads being executed for load-testing. The plurality of threads has a coordinator thread and one or more waiting threads. Further, the one or more waiting threads are locked from accessing the target application and the coordinator thread capable of unlocking the one or more waiting threads. The coordinator thread is executed based on the request to unlock the one or more waiting threads. The unlocked threads access the target application to test the load.Type: GrantFiled: February 2, 2017Date of Patent: July 21, 2020Assignee: Tata Consultancy Services LimitedInventor: Lutfur Rahaman
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Patent number: 10719430Abstract: A testing system for testing a touch screen graphical user interface is disclosed. The testing system includes a touch screen for displaying the graphical user interface under test and for receiving a first plurality of touch inputs from at least one user, a first module for recognizing the first plurality of touch inputs received by the touch screen as a second plurality of data structures, a second module for receiving the second plurality of data structures from the first module and constructing at least one test model, a third module for generating a third plurality of test cases based on the at least one test model constructed by the second module, and a fourth module for executing the third plurality of test cases generated by the third module.Type: GrantFiled: April 10, 2018Date of Patent: July 21, 2020Assignee: NANJING UNIVERSITYInventors: Enyi Tang, Linzhang Wang, Chucheng Zhang, Haoliang Cheng, Xin Chen, Xuandong Li
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Patent number: 10719431Abstract: Techniques are described for graph based code performance analysis of software, such as software that is being developed and tested in a development environment. Implementations provide a technique for instrumenting code by adding various annotations into the code. Each annotation may be a function call that executes with the annotated code, but does not alter the behavior and/or functionality of the annotated code apart from outputting call tracking information during execution. The call tracking information generated by annotations can be analyzed to generate a call graph that depicts calling relationships between functions in the code. The call graph can be presented within a user interface and/or automatically analyzed to develop recommendations regarding code coverage for testing, impact information describing how changes to one function impact another function, code optimization recommendations, and so forth.Type: GrantFiled: December 18, 2018Date of Patent: July 21, 2020Assignee: SAP SEInventors: Yang Peng, Yueling Wang, Jieying Zhang, Yunfeng Jiang, Junshan Xu
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Patent number: 10719432Abstract: Systems and methods for performing automated software testing on user interface elements are disclosed. For instance, a first element of an application can be identified. A signature can be generated for the first element. The signature for the first element can include one or more attributes descriptive of the first element. After an update of the application, a candidate element signature can be generated for one or more candidate elements in the updated application. The signature for the first element can be compared to each candidate element signature to determine whether the first element matches each candidate element, thereby enabling the first element to be located after the update of the application.Type: GrantFiled: October 22, 2019Date of Patent: July 21, 2020Assignee: Softesis Inc.Inventors: Ivan Konyshev, Dmytro Shamatrin, Pavlo Grebeniuk
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Patent number: 10719433Abstract: An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit includes an array of software-configurable general purpose processors, a globally-shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors has access to the globally-shared memory to execute one or more portions of at least one of (i) a decoding program, (ii) an encoding program, and (iii) an encoding and decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a map array describing a position of block data in one or more associated arrays.Type: GrantFiled: November 12, 2018Date of Patent: July 21, 2020Assignee: Amazon Technologies, Inc.Inventors: Jeffrey K. Lassahn, Timothy B. Prins
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Patent number: 10719434Abstract: A cache stores 2{circumflex over (?)}J-byte cache lines has an array of 2{circumflex over (?)}N sets each holds tags each X bits and 2{circumflex over (?)}W ways. An input receives a Q-bit address, MA[(Q?1):0], having a tag MA[(Q?1):(Q?X)] and index MA[(Q?X?1):J]. Q is at least (N+J+X?1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2{circumflex over (?)}W ways of the selected set when operating in a first mode; and into a subset of the 2{circumflex over (?)}W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion.Type: GrantFiled: December 14, 2014Date of Patent: July 21, 2020Assignee: VIA ALLIANCE SEMICONDUCTORS CO., LTD.Inventor: Douglas R. Reed
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Patent number: 10719435Abstract: A storage device includes nonvolatile memory devices, a connector that includes connection terminals, and a controller that communicates with an external host device through the connector and to control the nonvolatile memory devices. The connector provides the external host device with detection information in response to the connector being connected with the external host device. Power is supplied from the external host device to the controller and the nonvolatile memory devices through the connector in response to the providing of the detection information. The connector provides the external host device with information of a communication type in which the controller communicates with the external host device, after the power is supplied. The communication type is one of a first communication type and a second communication type. The controller configures the connection terminals to correspond to a single or dual port based on a signal received from the external host device.Type: GrantFiled: January 5, 2018Date of Patent: July 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gwangman Lim, Eun-Jin Yun
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Patent number: 10719436Abstract: According to an embodiment, a management device includes a counter storage unit, a first management information storage unit, and an update unit. The first management information storage unit stores a first management table capable of storing first management information about each of a predetermined number of first areas. The first management information indicates whether each second area included in a corresponding first area has data written therein. In response to writing of first data into the nonvolatile memory, when a state of a target second area indicated in the first management information about a target first area is an unwritten state, the update unit changes the state of the target second area to a written state; while when the state of the target second area indicated in the first management information is the written state, the update unit updates the counter value for the target first area.Type: GrantFiled: August 29, 2017Date of Patent: July 21, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Shiyo Yoshimura, Tatsunori Kanai, Yusuke Shirota, Satoshi Shirai
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Patent number: 10719437Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.Type: GrantFiled: May 21, 2018Date of Patent: July 21, 2020Assignee: Toshiba Memory CorporationInventors: Hideki Yoshida, Shinichi Kanno
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Patent number: 10719438Abstract: A memory controller is for controlling operations of a nonvolatile memory including a first memory block group for storing a first type of data and a second memory block group for storing a second type of data. The memory controller includes a garbage collection management unit configured to execute a garbage collection policy in which a first garbage collection criteria is applied to the first memory block group, and a second garbage collection criteria is applied to the second memory block group, where first garbage collection criteria is different than the second garbage collection criteria.Type: GrantFiled: June 28, 2016Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: In-Hwan Choi
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Patent number: 10719439Abstract: A method operable with the storage device includes determining a workload to the storage device based on host Input/Output (I/O) requests to the storage device. When the workload is above a threshold, a first portion of the storage device is selected for garbage collection based on the I/O requests. Otherwise, when the workload is below the threshold, a second different portion of the storage device is selected for garbage collection based on a storage ability of the second portion of the storage device.Type: GrantFiled: September 6, 2017Date of Patent: July 21, 2020Assignee: Seagate Technology LLCInventors: Ryan James Goss, Siddhartha K. Panda, Daniel J. Benjamin, Ryan C. Weidemann
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Patent number: 10719440Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.Type: GrantFiled: August 7, 2018Date of Patent: July 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keisuke Matsumoto, Seiji Mochizuki, Hiroshi Ueda, Katsushige Matsubara
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Patent number: 10719441Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.Type: GrantFiled: February 12, 2019Date of Patent: July 21, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jieming Yin, Yasuko Eckert, Matthew R. Poremba, Steven E. Raasch, Doug Hunt
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Patent number: 10719442Abstract: An apparatus and method for prioritizing transactional memory regions. For example, one embodiment of a processor comprises: a plurality of cores to execute threads comprising sequences of instructions, at least some of the instructions specifying a transactional memory region; a cache of each core to store a plurality of cache lines; transactional memory circuitry of each core to manage execution of the transactional memory (TM) regions based on priorities associated with each of the TM regions; and wherein the transactional memory circuitry, upon detecting a conflict between a first TM region having a first priority value and a second TM region having a second priority value, is to determine which of the first TM region or the second TM region is permitted to continue executing and which is to be aborted based, at least in part, on the first and second priority values.Type: GrantFiled: September 10, 2018Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Ren Wang, Raanan Sade, Yipeng Wang, Tsung-Yuan Tai, Sameh Gobriel
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Patent number: 10719443Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.Type: GrantFiled: March 25, 2019Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
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Patent number: 10719444Abstract: The disclosure provides for a reactive cache coherence protocol that has efficiencies over proactive approaches. Rather than proactively performing remediation when a data item is invalidated, a destination endpoint checks cache coherence upon receiving an indication of a cache hit, and based at least on detecting a lack of coherence, performs a reactive remediation process. For example, the incoherence may be fixed by replacing, as a cached data item, a data block indicated by the cache hit with a replacement data block that triggered the cache hit.Type: GrantFiled: November 23, 2018Date of Patent: July 21, 2020Assignee: VMware, Inc.Inventor: Oleg Zaydman
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Patent number: 10719445Abstract: Systems and methods for permitting flexible use of volatile memory for storing read command prediction data in a memory device, or in a host memory buffer accessible by the memory device, while preserving accuracy in predicting read commands and pre-fetching data are disclosed. The read command prediction data may be in the form of history pattern match table having entries indexed to a search sequence of one or more commands historically preceding the read command in the indexed table entry. A host trigger requesting the limited volatile memory space, a lower power state that is detected, or a memory device-initiated need may trigger generation of and subsequent use of a smaller table for the prediction process while the larger table is released. The memory device may later regenerate the larger table when more space in the volatile memory becomes available.Type: GrantFiled: February 28, 2019Date of Patent: July 21, 2020Assignee: Western Digital Technologies, Inc.Inventors: Ariel Navon, Shay Benisty, Alex Bazarsky
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Patent number: 10719446Abstract: A method and apparatus for implementing a buffer cache for a persistent file system in non-volatile memory is provided. A set of data is maintained in one or more extents in non-volatile random-access memory (NVRAM) of a computing device. At least one buffer header is allocated in dynamic random-access memory (DRAM) of the computing device. In response to a read request by a first process executing on the computing device to access one or more first data blocks in a first extent of the one or more extents, the first process is granted direct read access of the first extent in NVRAM. A reference to the first extent in NVRAM is stored in a first buffer header. The first buffer header is associated with the first process. The first process uses the first buffer header to directly access the one or more first data blocks in NVRAM.Type: GrantFiled: August 31, 2017Date of Patent: July 21, 2020Assignee: Oracle International CorporationInventors: Juan R. Loaiza, J. William Lee, Wei-Ming Hu, Kothanda Umamageswaran, Neil J. S. MacNaughton, Adam Y. Lee
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Patent number: 10719447Abstract: Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.Type: GrantFiled: September 26, 2016Date of Patent: July 21, 2020Assignee: INTEL CORPORATIONInventors: Tomas G. Akenine-Moller, Prasoonkumar Surti, Altug Koker, David Puffer, Jim K. Nilsson
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Patent number: 10719448Abstract: A cache is presented. The cache comprises a tag array configured to store one or more tag addresses, a data array configured to store data acquired from a dynamic random access memory device, and a cache controller. The cache controller is configured to: receive a cache access request; determine, based on an indication associated with the cache access request, a cache access policy; and perform an operation to the tag array and to the data array based on the determined cache access policy.Type: GrantFiled: June 13, 2017Date of Patent: July 21, 2020Assignee: ALIBABA GROUP HOLDING LIMITEDInventor: Xiaowei Jiang
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Patent number: 10719450Abstract: A system in which a volatile random access memory stores first header data, second header data, a first logical array in a first contiguous memory block and a second logical array in a second contiguous memory block. Each array position of the first logical array stores a database column value, and each array position of the second logical array stores an indication of a number of consecutive occurrences of a database column value. The first header data includes a first pointer to the first memory block, and the second header data includes a second pointer to the second memory block.Type: GrantFiled: December 21, 2018Date of Patent: July 21, 2020Assignee: SAP SEInventors: Sebastian Seifert, Christian Lemke
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Patent number: 10719451Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.Type: GrantFiled: January 11, 2018Date of Patent: July 21, 2020Assignee: OPTIMUM SEMICONDUCTOR TECHNOLOGIES INC.Inventors: Mayan Moudgill, A. Joseph Hoane, Lei Wang, Gary Nacer, Aaron G. Milbury, Enrique A. Barria, Paul Hurtley
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Patent number: 10719452Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.Type: GrantFiled: June 22, 2018Date of Patent: July 21, 2020Assignee: XILINX, INC.Inventors: Ygal Arbel, Sagheer Ahmad, Gaurav Singh