Abstract: There is provided a substrate processing apparatus having a transfer arm configured to transfer two substrates between a transfer chamber and a processing chamber having two mounting tables, the transfer arm holding the two substrates in a state where the two substrates overlap each other with a gap between the two substrates. The substrate processing apparatus includes: a lower substrate detection sensor configured to detect an edge portion of a lower substrate when the lower substrate is transferred; and an upper substrate detection sensor configured to detect an edge portion of an upper substrate when the upper substrate is transferred.

Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.

Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

Abstract: A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.

Abstract: A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of reference chips with respect to the substrate in the images, obtaining relative offsets of subordinate chips with respect to the reference chips in the images, and calculating misalignments of the chips based on the absolute offsets and the relative offsets.

Abstract: A method for manufacturing a resistivity standard sample include the steps, preparing a first-conductivity-type silicon single crystal substrate, measuring a thickness of the silicon single crystal substrate by using a thickness measuring instrument having traceability to the national standard, growing a second-conductivity-type silicon epitaxial layer on the silicon single crystal substrate to fabricate an epitaxial wafer having a p-n junction, measuring a thickness of the epitaxial wafer by using the thickness measuring instrument having the traceability to the national standard, obtaining a thickness of the silicon epitaxial layer from the thicknesses of the epitaxial wafer and the silicon single crystal substrate, and measuring a resistivity of the silicon epitaxial layer by using a resistivity measuring instrument having traceability to a resistivity standard reference material.

Abstract: A method for process analysis includes acquiring first inspection data, using a first inspection modality, with respect to a substrate having multiple instances of a predefined pattern of features formed thereon using different, respective sets of process parameters. Characteristics of defects identified in the first inspection data are processed so as to select a first set of defect locations in which the first inspection data are indicative of an influence of the process parameters on the defects. Second inspection data are acquired, using a second inspection modality having a finer resolution than the first inspection modality, of the substrate at the locations in the first set. The defects appearing in the second inspection data are analyzed so as to select, from within the first set of the locations, a second set of the locations in which the second inspection data are indicative of an optimal range of the process parameters.

Abstract: A semiconductor device includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member that surrounds the insulating substrate and that is in contact with a surface of the base plate to which the insulating substrate is joined; a sealing resin provided in a region surrounded by the base plate and the case member; a cover member facing a surface of the sealing resin and fixed to the case member; and a holding plate, a lower surface of the holding plate and a portion of a side surface of the holding plate being in close contact with the surface of the sealing resin, an upper surface of the holding plate being fixed to and protruding from a surface of the cover member facing the surface of the sealing resin.

Abstract: A sensor package structure includes a substrate, an electronic chip fixed on the substrate by flip-chip bonding, a sealant disposed on the substrate and embedding the electronic chip therein, a sensor chip with a size larger than that of the electronic chip, a light-permeable sheet, a plurality of metal wires electrically connected to the substrate and the sensor chip, and a package body. A bottom surface of the sensor chip is disposed on the sealant to be spaced apart from the electronic chip. A lateral surface of the sensor chip is horizontally spaced apart from that of the sealant by a distance less than or equal to 3 mm. The package body is disposed on the substrate and covers the metal wires as well as the lateral sides of the sealant and the sensor chip. The light-permeable sheet is fixed above the sensor chip through the package body.

Abstract: Embodiments are generally directed to extended temperature operation for electronic systems using induction heating. An embodiment of an apparatus includes an electronic device including: a die or package; a thermal solution coupled with the die or package for cooling of the die or package; and ferromagnetic material, wherein the ferromagnetic material is to generate induction heating of the die or package in response to an alternating magnetic field.

Abstract: Disclosed is a cooling assembly for circuit boards. In one embodiment, the assembly includes a circuit board that is thermally and physically coupled to a heat spreader by a thermal interface. In one configuration, the circuit board is formed from a semiconductor material and includes a first board surface on which integrated circuits are mounted and a second board surface opposite the first board surface. The heat spreader is formed from a thermally conductive material and includes a plurality of vanes that are spaced apart from one another. The thermal interface is coupled between at least one area of the second board surface of the circuit board and a contact area of each of the plurality of vanes. Heat generated by the integrated circuits is conducted from at least one integrated circuit to the plurality of vanes of the heat spreader through the circuit board and the thermal interface.

Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.

Abstract: A semiconductor substrate according to the present invention includes a nitride semiconductor layer 203, an amorphous semiconductor layer 205 formed on one main surface side of the nitride semiconductor layer 203, a high-roughness layer 206 which is a semiconductor layer formed on the amorphous semiconductor layer 205 and has a surface roughness larger than the amorphous semiconductor layer 205, and a diamond layer 207 formed on the high-roughness layer 206. Damage to the nitride semiconductor layer can be reduced in forming the diamond layer on the nitride semiconductor layer and adhesion between the layers can be increased.

Abstract: A substrate for a power module (100) of the present invention includes a metal substrate (101), an insulating resin layer (102) provided on the metal substrate (101), and a metal layer (103) provided on the insulating resin layer (102). The insulating resin layer (102) includes a thermosetting resin (A) and inorganic fillers (B) dispersed in the thermosetting resin (A), a maximum value of a dielectric loss ratio of the insulating resin layer (102) at a frequency of 1 kHz and 100° C. to 175° C. is equal to or less than 0.030, and a change in a relative permittivity is equal to or less than 0.10.

Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.

Abstract: The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal.

Abstract: The base of an integrated circuit package comprises a first side, and a second side opposing the first side. The base further comprises, a base mounting section, a die mounting section, and a recessed section. The recessed section comprises a recess between the die mounting section and the base mounting section. The base further comprises an opening extending through the base from the first side to the second side. At least a portion of the recess intersects with the opening.

Abstract: A flip-chip wire bondless power device and method for using a two sided contact bare die power device as a single-connection-level power device. The device uses a top pad solder ball array for connecting a top pad electrically connected to the top contact of the bare die power device and a bottom pad solder ball array for connecting a bottom pad that is electrically through an electrically conductive bottom pad connector that is electrically connected to the bottom contact of the bare die power device using an electrically conductive die-attach material, the top pad and bottom pad, and thereby the top pad solder ball array and the bottom pad solder ball array are planar for flip chip mounting. A trench can be formed between the top pad and bottom pad for isolation and insulation purposes. A method of assembling a flip-chip wire bondless power device is also provided.

Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

Abstract: Disclosed are semiconductor package structure and semiconductor modules including the same. The semiconductor module includes a circuit board, a first semiconductor package over the circuit board, and a connection structure on the circuit board and connecting the circuit board and the first semiconductor package. The first semiconductor package includes a first package substrate. A difference in coefficient of thermal expansion between the connection structure and the circuit board may be less than a difference in coefficient of thermal expansion between the circuit board and the first package substrate.

Abstract: In a semiconductor device, a first semiconductor chip and a second semiconductor chip are aligned in a direction orthogonal to a plate thickness direction of the first semiconductor chip. A pair of first heat sinks is disposed on opposite sides of the first semiconductor chip in the first direction, and a pair of second heat sinks disposed on opposite sides of the second semiconductor chip in the first direction. The semiconductor chips and the heat sinks are sealed in a resin molded body. A plurality of main terminals are aligned in the second direction and project from a same side surface of a resin molded body. The main terminals includes a positive electrode terminal, a negative electrode terminal, an output terminal, and an auxiliary terminal. The first relay members are disposed in the resin molded body, and electrically connecting the main terminals and the corresponding heat sinks.

Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.

Abstract: A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.

Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.

Abstract: A wiring substrate includes a first insulating layer including a cavity, an electronic component in the cavity, and a second insulating layer on the first insulating layer. The second insulating layer covers the electronic component. A recess having a predetermined volume distribution is formed in an outermost layer of the electronic component that defines a surface of the electronic component facing away from the bottom of the cavity. The width of the gap between the side surface of the electronic component and the inner wall surface of the cavity in a plan view is determined based on the predetermined volume distribution. The second insulating layer is in the recess and the gap.

Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die. A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

Abstract: An electronic component mounting board includes an inorganic substrate, a wiring board, and a bond. The inorganic substrate includes an electronic component mounting portion in a central area of an upper surface of the inorganic substrate in which an electronic component is mountable. The wiring board is a frame surrounding the electronic component mounting portion on the upper surface of the inorganic substrate. The bond is located between the inorganic substrate and the wiring board. The inorganic substrate includes a downward bend outward from a bond area including the bond.

Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.

Abstract: A semiconductor chip including a substrate including a plurality of chip areas and a line-shaped scribe area defining the chip areas, an integrated circuit (IC) structure on the chip area, the IC structure including a plurality of transistors and a plurality of stacked wiring structures connected to the transistors, and a warpage protector in the line-shaped scribe area and corresponding to the stacked wiring structures, the warpage protector supporting at least one side of the IC structure may be provided.

Abstract: An anisotropic conductive sheet including: a sheet body including a material having an insulation property; and a plurality of conductive portions each including a material having a conductive property, each of the plurality of conductive portions being provided so as to penetrate one surface side and another surface side of the sheet body is provided. Each of the plurality of conductive portions includes a plurality of conductive fibrous members. In the plurality of conductive fibrous members in the conductive portion, a longitudinal direction (Q) of each conductive fibrous member is along a direction that is substantially same as a penetration direction (P) of the penetration between the one surface side and the other surface side and the conductive fibrous members are in contact with one another, providing electrical connection from the one surface side toward the other surface side.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a first redistribution structure, an insulating layer, and an antenna. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure is disposed on a first side the encapsulated semiconductor device and electrically connected to the semiconductor device. The insulating layer is disposed on a second side of the encapsulated semiconductor device and comprises a groove pattern. The antenna is filled the groove pattern, wherein an upper surface of the antenna is substantially coplanar with an upper surface of the insulating layer.

Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Abstract: A semifinished product includes a base structure, wafer structures, a cover structure and a further cover structure. The base structure has an electrically conductive layer and/or an electrically insulating layer. The wafer structures are on the base structure and have electronic components. The cover structure has at least one further layer and covers the wafer structures and part of the base structure. Separate electronic components are arranged on the cover structure and a further cover structure is provided to cover the separate electronic components and part of the cover structure. A component carrier includes a bare die with pads. The bare die is laminated between a base laminate and a cover laminate and has a lateral semiconductor surface being exposed from the base laminate and the cover laminate. A redistribution layer increases spacing of external electric contacts relative to spacing between pads of the bare die.

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.

Abstract: A semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips; and a connection region electrically connecting the semiconductor package to the module substrate, wherein the connection region comprises: a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the module substrate; a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the module substrate; and a third region electrically connected between command/address signal terminals of both the first and second chips of the semiconductor package and the module substrate, wherein the first region is closer to the electric connection element of the module substrate, compared with the third region.

Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.