Abstract: A controller can receive first and second metrics respectively indicating distributed computing system servers' CPU, memory, or disk utilization, throughput, or latency for a first time. The controller can receive third and fourth metrics for a second time. The controller can determine a first graph including vertices corresponding to the servers and edges indicating data flow between the servers, a second graph including edges indicating the first metrics satisfy a first threshold, a third graph including edges indicating the second metrics satisfy a second threshold, a fourth graph including edges indicating the third metrics fail to satisfy the first threshold, and a fifth graph including edges indicating the fourth metrics fail to satisfy the second threshold. The controller can display a sixth graph indicating at least one of first changes between the second graph and the fourth graph or second changes between the third graph and the fifth graph.

Abstract: Recording a replay-able trace of execution of a multi-threaded process includes identifying a trace memory model that defines one or more orderable events that are to be ordered across a plurality of threads of the multi-threaded process. The plurality of threads are executed concurrently across one or more processing units of one or more processors. During execution of the plurality of threads, a separate replay-able trace is recorded for each thread independently. Recording includes, for each thread, recording initial state for the thread, recording at least one memory read performed by at least one processor instruction executed by the thread that takes memory as input, and recording a least one orderable event performed by the thread with a monotonically increasing number that orders the event among other orderable events across the plurality of threads.

Abstract: A method for firmware debug trace capture includes creating a hand-off block (“HOB”), capturing first debug trace statements during a boot sequence of a computer and writing the first debug trace statements to the HOB. A trace memory buffer can be created and the first debug trace statements can be copied from the HOB to the trace memory buffer. Second debug trace statements are captured during the boot sequence and appended to the trace memory buffer. In some configurations, the first debug trace statements can be written to the HOB during the pre-Extensible Firmware Interface initialization (“PEI”) phase of the boot sequence and the second debug trace statements can be written to the trace memory buffer during the driver execution (“DXE”) phase of the boot sequence.

Abstract: A debugging tool comprises user input apparatus to receive user input from a debugging user, computer storage configured to hold a piece of code to be debugged, the code embodying a state machine defining a user input action, a display configured to display a timeline, and at least one processor configured to execute an iterative debugging process for visualising behaviour of the code on the timeline. The debugging process is driven by changes in the user input received at the user input apparatus and is performed so as to represent on the timeline a sequence of expected user input states of the state machine as they are actualized by the debugging user according to the permitted transitions.

Abstract: A script directing functional testing of an application specifies values for properties of a specific graphical user interface (GUI) and specifies an image of the specific GUI element. A computing device detects whether the application has displayed the specific GUI element by evaluating the values for the properties of the specific GUI element against GUI elements that the application has displayed. If unsuccessful, the computing device detects whether the application has displayed the specific GUI element by evaluating the image of the specific GUI element against a screen image including the GUI elements that the application has displayed.

Abstract: Debugger requests are for debugging a script injected into a web application during a debug session are received. Each of the debugger requests include the same debug session identifier. A different one of the debugger requests is associated with each of the break points set for debugging the script. For each of the debugger requests: a new stateless debugger node is connected with a single stateless target tester node. Stateless debugger nodes and stateless target tester nodes reside inside of the multi-node cloud system. The script is debugged on the same stateless target tester node while the debugging is controlled from a developer computer system that is outside of the multi-node cloud system. After completion of each of the debugger requests: a current stateless debugger node is disconnected, and state stored in the multi-node cloud system used for servicing a current debugger request is destroyed.

Abstract: Methods, systems and apparatuses may provide for technology that applies a functional safety test stimulus to a hardware level simulator, automatically compiles an output of the hardware level simulator into a software test library (STL), and iteratively verifies that the diagnostic coverage of the STL file approximates the diagnostic coverage of the functional safety test stimulus.

Abstract: Systems and methods for providing a testing chamber are provided herein. One embodiment of a testing chamber includes a chamber environment affecter and a chamber computing device that includes a processor and a memory component. The memory component may store logic that causes the testing chamber to receive a recipe program, where the recipe program defines a grow recipe for a grow pod. The logic may further cause the testing chamber to determine a difference between operation of the testing chamber and operation of the grow pod, adapt the recipe program for operation by the testing chamber, and execute the recipe program in the testing chamber. The logic may further cause the testing chamber to monitor operation of the testing chamber executing the recipe program to determine a malfunction in the recipe program and provide an indication of the malfunction of the recipe program.

Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first command and performing a first operation corresponding to the first command; transmitting a completion message to a host system corresponding to a completion of the first operation; detecting command processing information; determining a transmission mode of an interruption message according to the command processing information; and transmitting the interruption message to the host system according to the transmission mode.

Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

Abstract: A memory system includes a memory device, and a controller suitable for selecting at least one common operation necessary to be performed in first and second tasks, selecting the first or second task, and selectively performing one or more of a valid data scan operation, a valid data read operation, a valid data write operation, and a valid data map update operation based on selected information, wherein the first task is a garbage collection operation performed on a host data block, a system data block and a map data block, wherein the second task is a recovery operation performed after a sudden power-off (SPO) that occurs during the valid data map update operation.

Abstract: An instruction set architecture of a data processing system includes one or more persistent atomic instructions that provide failure-safe atomicity. When issued, a sequence of operations associated with the persistent atomic instruction are performed and first data, associated with a first address in a persistent memory of the data processing system, is written to a point of persistence in the data processing system. Access to data associated with the first address is controlled such that the first data is not available to other execution threads of the data processing system until completion of writing the first data to the point of persistence. The point of persistence may be the persistent memory itself or a persist buffer. The persist buffer may be a volatile or non-volatile buffer. One or more monitors may control access to data at memory addresses dependent upon a designated state of exclusivity.

Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, wherein each node includes at least one processor, a first cache private to the node, a second cache at a higher level than the first cache, and a cache location buffer (CLB) private to the node, wherein, for at least one node of the plurality of nodes, at least one of the first cache and the second cache included in the at least one node includes at least one cache location that is capable of storing a compressed data unit of varying size, the CLB included in the at least one node is configured to store a plurality of CLB entries, each of the CLB entries including a plurality of location information values.

Abstract: A memory cache controller includes a transaction arbiter circuit and a retry queue circuit. The transaction arbiter circuit may determine whether a received memory transaction can currently be processed by a transaction pipeline. The retry queue circuit may queue memory transactions that the transaction arbiter circuit determines cannot be processed by the transaction pipeline. In response to receiving a memory transaction that is a cache management transaction, the retry queue circuit may establish a dependency from the cache management transaction to a previously stored memory transaction in response to a determination that both the previously stored memory transaction and the cache management transaction target a common address. Based on the dependency, the retry queue circuit may initiate a retry, by the transaction pipeline, of one or more of the queued memory transactions in the retry queue circuit.

Abstract: A method for operating a database and a cache of at least a portion of the database may include receiving a plurality of read requests to read a data entity from the database and counting respective quantities of the requests serviced from the database and from the cache. The method may further include receiving a write request to alter the data entity in the database and determining whether to update the cache to reflect the alteration to the data entity in the write request according to the quantity of the requests serviced from the database and the quantity of the requests serviced from the cache. In an embodiment, the method further includes causing the cache to be updated when a ratio of the quantity of the requests serviced from the database to the quantity of the requests serviced from the cache exceeds a predetermined threshold.

Abstract: Systems and methods for controlling cache usage are described and include associating, by a server computing system, a tenant in a multi-tenant environment with a cache cluster formed by a group of cache instances; associating, by the server computing system, a memory threshold and a burst memory threshold with the tenant; enabling, by the server computing system, each of the cache instances to collect metrics information based on the tenant accessing the cache cluster, the metrics information used to determine memory usage information and burst memory usage information of the cache cluster by the tenant; and controlling, by the server computing system, usage of the cache cluster by the tenant based on comparing the memory usage information with the memory threshold and comparing the burst memory usage information with the burst memory threshold.

Abstract: A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.

Abstract: Prefetch apparatus and a method of prefetching are presented. The prefetch apparatus monitors access requests, each having an access request address, and has request tracking storage to store region entries for regions of memory space which each span multiple access request addresses. The request tracking storage keeps access information for access requests received in their corresponding region entries. When a new region access request is received, which belongs to a new region for which there is no region entry, and when the request tracking storage has an adjacent region entry for which the access information shows that at least a predetermined number of the access request addresses have been accessed, a page mode region prefetching process is initiated for all access request addresses in the new region.

Abstract: A method of storing data in a memory module including an in-module prefetcher, an in-module prefetch buffer, memory, and a memory controller, the method including sending address information from the in-module prefetcher to the memory controller and to the prefetch buffer, determining prefetch accuracy based on a comparison of the address information sent to the memory controller and the address information sent to the prefetch buffer, determining a prefetch mode based on the prefetch accuracy, and storing the data in the memory based on the prefetch mode.

Abstract: A memory system includes a non-volatile memory including a main area and a first cache area; and a controller suitable for controlling the non-volatile memory and including a second cache area. The controller includes a read manager suitable for performing a migration operation of moving data stored in the main area into the first cache area based on a list storing a plurality of logical block addresses (LBAs) based on a read data access pattern.

Abstract: A method and apparatus for controlling data organization in a tiered memory system, where the system comprises a lower and higher bandwidth memories. Accesses to the tiered memory system by an action of a computing device in a first time interval are monitored to determine a first measure of bandwidth utilization, from which it is determined if the action is in a high bandwidth phase for which a first measure of bandwidth utilization is greater than an upper value. It is further determined, from confidence counters, if a monitored access is consistent with respect to the first instructions or with respect to a memory address of the access. Data associated with the access is moved from the lower bandwidth memory to the higher bandwidth memory when the action is in a high bandwidth phase, the access is consistent, and bandwidth utilization of the higher bandwidth memory is below a threshold.

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

Abstract: A method for invalidating a track of data on a storage drive in preparation to unpin the track is disclosed. In one embodiment, such a method includes invalidating certain metadata associated with a track of data residing on a storage drive of a storage system. The method further creates, in cache of the storage system, an invalid track image associated with the track. The method destages, from the cache, the invalid track image to the storage drive. Once the invalid track image is destaged, the method may unpin the track in cache, thereby enabling destages of the track from the cache to the storage drive going forward. A corresponding system and computer program product are also disclosed.

Abstract: Processor, apparatus, and method for reordering a stream of memory access requests to establish locality are described herein. One embodiment of a method includes: storing in a request queue memory access requests generated by a plurality of execution units, the memory access requests comprising a first request to access a first memory page in a memory and a second request to access a second memory page in the memory; maintaining a list of unique memory pages, each unique memory page associated with one or more memory access requests stored the request queue and is to be accessed by the one or more memory access requests; selecting a current memory page from the list of unique memory pages; and dispatching from the request queue to the memory, all memory access requests associated with the current memory page before any other memory access request in the request queue is dispatched.

Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.

Abstract: There is provided an apparatus that includes an input address port to receive an input address from processor circuitry. Address storage stores a translation between the input address and an output address in an output address space. An output address port outputs the output address. An input data port receives data. Data storage stores the data. An output data port outputs the data stored in the data storage and control circuitry causes the data storage to store the translation between the input address and the output address. The control circuitry issues a signal to cause a page walk to occur in response to the input address being absent from the address storage and the data storage.

Abstract: Embodiments include a multi-stream storage device, a system including a multi-stream storage device, and a method, comprising: receiving an access to a multi-stream storage device; converting at least one parameter of the access into a stream identifier; and accessing the multi-stream storage device using the stream identifier.

Abstract: An address mapping method of a storage device which includes a plurality of sub-storage devices each including an over-provision area includes detecting mapping information of a received logical address from a mapping table, selecting a hash function corresponding to the received logical address depending on the mapping information, selecting any one, which is to be mapped onto the received logical address, of the plurality of sub-storage devices by using the selected hash function, and mapping the received logical address onto the over-provision area of the selected sub-storage device. The selected hash function is selected from a default hash function and a plurality of hash functions to provide a rule for selecting the any one of the plurality of sub-storage devices.

Abstract: A method comprising, in an image processing operation, identifying location data indicative of a read path for the image processing operation, the read path at least partly traversing a block of pixels of an image. Parameter data relating to a characteristic of the read path in the context of the block is generated from the location. Storage prioritization data is associated with the block at least partly on the basis of the parameter data. The storage prioritization data is for determining whether block data representative of the block is to be evicted from storage.

Abstract: A system and method is provided for probabilistic defense against remote exploitation of memory. In certain embodiments, the system comprises one or more processors, read and execute (RX) portions of memory, read and write (RW) portions of memory, execute only (XOM) portions of memory, and one or more programs stored in the memory. The one or more programs include instructions for maintaining all pointers to RX memory instructions in XOM memory. In addition, the one or more programs include instructions for preventing all direct references to RX memory in RW memory by forcing pointers in RW memory to reference XOM memory first, which then references RX memory instructions.

Abstract: Technologies for protecting virtual machine memory of a compute device include a virtual machine (VM) instantiated on the compute device, a virtual machine monitor (VMM) established on the compute device to control operation of the VM, a secured memory, and a memory manager. The memory manager receives a memory access request that includes a virtual linear address (LA) from the VM and performs a translation of the LA to a translated host physical address (HPA) of the compute device using one or more page tables associated with the VM and VMM. The memory manager determines whether a secured translation mapping of LA-to-HPA that corresponds to the LA is locked. If the mapping is locked, the memory manager verifies the translation based on a comparison of the translated HPA to a HPA translated using the secured translation mapping and, if verified, performs the memory access request using the translated HPA.

Abstract: Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. The controller may implement a hierarchical scheme comprising first-level arbitration(s) between submission queues of each of a plurality of input/output virtualization (IOV) functions, and a second-level arbitration between the respective IOV functions. Alternatively, or in addition, the controller may implement a flat arbitration scheme, which may comprise selecting submission queue(s) from one or more groups, each group comprising submission queues of each of the plurality of IOV functions. In some embodiments, the controller implements a credit-based arbitration scheme. The arbitration scheme(s) may be modified in accordance with command statistics and/or current resource availability.

Abstract: A method for establishing a connection in a non-volatile memory system is provided. A connection to a host is established. A request message with a target parameter of an NVM subsystem is received. A target NVM subsystem that meets the target parameter is determined. Routing information of the target NVM subsystem is determined. A response message that includes the routing information of the target NVM subsystem is sent. According to the method for establishing a connection in a non-volatile memory system, the host can establish a connection to an NVM subsystem that meets a requirement to improve connection reliability.

Abstract: In one embodiment, a heterogeneous integrated solid state drive includes a plurality of solid state memory devices including at least one solid state memory device of a first type and at least one solid state memory device of a second type, a controller coupled to each of the plurality of solid state memory devices and an interface coupled to the controller. The controller is configured to receive at least one user-defined memory parameter and to create at least one namespace satisfying the at least one user-defined memory parameter in at least one of the plurality of solid state memory devices. In one embodiment, the at least one user-defined memory parameter is one of a group consisting of a capacity, a quality of service level, an assured number of I/O operations per second, a bandwidth, a latency, and an endurance.

Abstract: The present technology relates to a communication device and a control method that allow variation of modes of connection between electronic devices to be increased. A transmission unit transmits a modulated signal obtained by frequency-converting a baseband signal into a signal of a frequency band higher than the baseband signal by using a predetermined carrier. A detecting unit detects a termination unit of a second electronic device having the termination unit to be detected by a first electronic device as a communication partner. A controller causes the transmission unit to transmit carriers in response to the detection of the termination unit. The present technology is applied to, for example, communication between optional electronic devices such as communication between a universal serial bus (USB) host and a USB device.

Abstract: An example electronic device includes memory for storing a program for unlocking the first electronic device using a wearable electronic device; wireless communication circuitry; and one or more processors configured to execute the program stored in the memory to cause the electronic device to at least establish wireless communication, via the wireless communication circuitry, with the wearable electronic device when the wearable electronic device is in a wireless communication range of the first electronic device; determine whether the wearable second electronic device is authenticated for unlocking the first electronic device; determine whether the wearable electronic device is in a specific range of the first electronic device based on a signal transmitted from the wearable electronic device being worn; and unlock the first electronic device based on determining that the wearable electronic device is authenticated and is in the specific range of the electronic device.

Abstract: A method for increasing compatibility of DisplayPort includes: providing a first source device, a second source device, a controller, and a sink device, wherein the first source device is connected to the controller; the first source device transmitting a first image signal to the sink device via a main link for displaying the first image signal on the sink device; causing the controller to disconnect from the first source device and connect to the second source device; executing a simulation process to generate a DC level variation on an auxiliary channel between the controller and the sink device; the second source device transmitting auxiliary data to the sink device; the sink device transmitting link data back to the second source device; and the second source device transmitting a second image signal to the sink device via a second main link for displaying the second image signal on the sink device.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: The present disclosure relates to techniques for facilitating communication and memory transfer between PCIe devices that permit access to an entire address space even though a limited address space is exposed and/or visible via the PCIe BAR registers. To this end, the present disclosure aims to permit memory transfer of large blocks of memory from one device to another including memory invisible to the system (i.e. not exposed via PCIe BAR registers). For example, in some embodiments, a data packet may be received at a port associated with a processor interconnect. The data packet includes a header which contains a first address associated with the port. In response to identifying the first address from the first data packet at the port, the data packet is decoded. During the decoding process, a second address is identified in a payload of the data packet.

Abstract: A system may include a data delivery pipeline communicatively coupled to one or more microservices that receive a dataset transmitted through the data delivery pipeline. The system may also include a first microservice that receives a first dataset corresponding to operation technology (OT) data or information technology (IT) data and determines a second dataset based on the first dataset. The system may also include a second microservice that receives the second dataset from the first microservice via the data delivery pipeline, determines an action to perform in an industrial automation component of an industrial automation system based on an analysis of the second dataset, and transmits the action to the industrial automation component via the data delivery pipeline.

Abstract: Embodiments of the present disclosure provide an APB (Advanced Peripheral Bus) bus-based SPI (Serial Peripheral Interface) communication device. The device comprises: an APB interface module, an SPI bus interface module, an encryption module, and a decryption module, wherein the encryption module receives plaintext data and a key from a master via the APB interface module, generates, when enabled, ciphertext data according to the plaintext data and the key, and sends the ciphertext data to a slave via the SPI bus interface module; the decryption module receives the ciphertext data from the slave via the SPI bus interface module and receives a key from the master via the APB interface module, generates, when enabled, plaintext data according to the ciphertext data and the key, and sends the plaintext data to the master via the APB interface module. The present disclosure can improve the security of data transmission.

Abstract: For adjusting a signal transmission direction in a cable, which is configured to be electrically coupled between a first interface port and a second interface port, an electric characteristic on at least a first pin of the first interface port is detected. Then a signal transmission direction of at least one pair of differential signal transmission channels in the cable is controlled to change from a first direction to a second direction different from the first direction, provided that a communication protocol between the first interface port and the second interface port is changed from a first communication protocol to a second communication protocol, and the electric characteristic complies with a first condition.

Abstract: The present disclosure includes apparatuses and methods for an operating system cache in a solid state device (SSD). An example apparatus includes the SSD, which includes an In-SSD volatile memory, a non-volatile memory, and an interconnect that couples the non-volatile memory to the In-SSD volatile memory. The SSD also includes a controller configured to receive a request for performance of an operation and to direct that a result of the performance of the operation is accessible in the In-SSD volatile memory as an In-SSD main memory operating system cache.

Abstract: Debug trace statements from a firmware are captured during a boot cycle of a computer executing the firmware. The debug trace statements are written to a motherboard's Serial Peripheral Interface (“SPI”) device. A microcontroller's SPI device receives the debug trace statements from the motherboard's SPI device, transforms the data format of the debug trace statements, and transmits the transformed debug trace statements over a serial communications port of the microcontroller.

Abstract: Systems, methods, apparatuses, and architectures for storage interposers are provided herein. In one example, an apparatus includes a host connector configured to couple to one or more host systems over associated host Peripheral Component Interconnect Express (PCIe) interfaces, and PCIe switch circuitry configured to receive storage operations over the host connector that are issued by the one or more host systems. The PCIe switch circuitry is configured to monitor when ones of the storage operations correspond to an address range and responsively indicate the ones of the storage operations to a control module. The control module is configured to selectively direct delivery of the ones of the storage operations to corresponding storage areas among one or more storage devices based at least on addressing information monitored for the ones of the storage operations in the PCIe switch circuitry.

Abstract: An example device comprises a central node for receiving vector data returned by leaf nodes, a plurality of leaf nodes for calculating and shifting the vector data, and forwarder modules comprising a local cache structure and a data processing component, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes; the central node is individually in communication connection with each group of leaf nodes by means of the forwarder modules; a communication structure constituted by each group of leaf nodes has self-similarity; the plurality of leaf nodes are in communication connection with the central node in a complete M-way tree approach by means of the forwarder modules of multiple levels; each of the leaf nodes comprises a setting bit.

Abstract: An apparatus, method, and computer program product for the improved identification of files subject to data loss prevention protocols in a network environment. Some example implementations provide for the generation and presentation of consolidated file sets in a user interface that allows a user to take direct action to operate on one or more files to enforce and/or otherwise comply with detected violations of data security protocols.

Abstract: The disclosed technology relates to a system configured to receive a first input into a search interface and perform a first search based on the first input, wherein the first search is performed on a first set of content items managed by a content management system. The system further receives a second input into the search interface and performs, in response to receiving the second input, a second search based on the first input, wherein the second search is performed on a second set of content items managed by the content management system.

Abstract: In some embodiments, a meta-data inspection data store may contain hierarchical components and subcomponents of an industrial asset and define points of interest. An industrial asset inspection platform may access that information and generate an inspection plan, including an association of at least one sensor type with each of the points of interest. The platform may then store information about the inspection plan in an inspection plan data store and receive inspection data (e.g., from a manual inspection, from an inspection robot, from a fixed sensor, etc.). A smart tagging algorithm may be executed to associate at least one point of interest with an appropriate portion of the received inspection data based on information in the inspection plan data store.

Abstract: Methods, non-transitory machine readable media, and computing devices that compare a hash value to a predefined value for sliding windows in parallel for segments partitioned from an input data stream. A bit array is parsed according to minimum and maximum chunk sizes to identify chunk boundaries for the input data stream. The bit array is populated based on a result of the comparison and portions of the bit array are parsed in parallel. Unique chunks of the input data stream defined by the chunk boundaries are stored in a storage device. Accordingly, this technology utilizes parallel processing in two stages. In a first stage, rolling window based hashing is performed concurrently to identify potential chunk boundaries. In a second stage, actual chunk boundaries are selected based on minimum and maximum chunk size constraints. This technology advantageously facilitates significant deduplication ratio improvement as well as improved parallel chunking performance.